JP4228250B2 - Compound semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a compound semiconductor device, and more particularly to a compound semiconductor device characterized by a configuration of an interface protective film for reducing interface state density and reducing contact resistance in a compound semiconductor MISFET or the like. .
[0002]
[Prior art]
Compound semiconductor field effect transistors such as MESFETs (Schottky barrier gate FETs) and HEMTs (high electron mobility transistors) and compound semiconductor devices such as HBTs (heterojunction bipolar transistors) are used as high-frequency operating elements. One of the applications is, for example, high-power FETs used for power amplifiers for transmission of mobile phone base stations, microwave and millimeter-wave amplifiers for mobile phones, and signal processing circuits for optical communication, etc. Application is expected.
[0003]
However, in a compound semiconductor device, SiO with respect to Si₂It has been difficult to form an insulating film interface having a low interface state density such as a film. For example, as an insulating film for GaAs, SiN, SiO₂Or Ga₂O_ThreeHowever, it is difficult to reduce the interface state density because GaAs has a unique interface state that causes pinning. MISFETs have not been put to practical use in group compound semiconductors, and interface problems have been avoided with MESFETs and HEMT structures.
Note that a normal interface state density in a compound semiconductor is 10¹³-10¹⁴eV^-1cm^-2Degree.
[0004]
Here, the pinning effect in GaAs will be described with reference to FIG.
See Fig. 7 (a)
FIG. 7A is a band diagram in the case where a metal and n-type GaAs are bonded, and no detailed causal relationship has been found when any metal is bonded to GaAs. Due to the pinning effect, there is a certain band bending that does not depend on the type of metal, whereby the barrier height is constant, a rectifying characteristic is generated at the semiconductor / metal interface, and the resistance of the ohmic contact to the n-type GaAs tends to increase.
[0005]
In order to improve such pinning effect, the surface of GaAs is changed to (NH_Four)₂S_xAnd Na₂Terminate (terminate) dangling bonds on the GaAs surface with S (sulfur) by treatment in a solution of S (see Japanese Patent Laid-Open No. 4-199518 if necessary), or treat the GaAs surface with H₂It is known to treat with S gas and terminate dangling bonds on the GaAs surface with S (if necessary, see JP-A-2-170417).
[0006]
In this way, the surface is stabilized by Ga-S bonds formed by terminating dangling bonds on the GaAs surface with S, and the PL (photoluminescence) intensity increases and the barrier height depends on the metal work function. This situation will be described with reference to FIG. 7 (b).
[0007]
See Fig. 7 (b)
FIG. 7B is a band diagram when the surface of the n-type GaAs is terminated with S and then a metal is bonded. The pinning of the n-type GaAs surface is released by the presence of GaS formed by the termination. Therefore, when a metal having a Schottky barrier reflecting the work function of the metal is formed and the barrier height is lowered, for example, Ti, band bending on the n-type GaAs surface is reduced, and the tunnel current in the GaS is reduced between the metal and the n-type GaAs. It will be connected ohmic through.
[0008]
However, since the GaS layer formed by such S termination is an extremely thin film with one atomic layer (monolayer), it is difficult to stably keep the surface stabilized by the S treatment as it is. There is.
For example, a SiN film or SiO as a surface protective film on the GaAs surface subjected to S treatment₂When a film is deposited, there is a problem that the PL intensity is remarkably reduced and the effect of releasing pinning is reduced.
[0009]
In addition, when an ohmic electrode is formed by depositing a metal on the surface of GaAs that has been subjected to S treatment, the metal and GaAs react with the heat treatment, and the Schottky characteristics change abruptly. At the same time, there is a problem that the effect of releasing pinning is reduced.
[0010]
In order to improve the stability in the S treatment, particularly the thermal stability, the present inventors have made tertiary butyl gallium sulfacuben [((t-Bu) GaS)._FourIn this case, it is proposed that a compound semiconductor MISFET is formed by releasing the pinning of the GaAs surface by using a thick amorphous GaS layer of about 30 nm formed by sublimation as a gate insulating film. No. 98185).
The GaS layer is amorphous in order to alleviate the lattice mismatch with GaAs. However, when GaS is crystallized, it has a cubic structure with a composition ratio of 1: 1.
[0011]
Furthermore, the present inventors have proposed that the release of pinning by such a thick GaS layer is used for forming an ohmic electrode (see Japanese Patent Application No. 9-351633, if necessary). Such an improved MISFET will be described with reference to FIG.
[0012]
Refer to FIG.
FIG. 8A is a cross-sectional view of a conventional improved MISFET. First, the C (carbon) concentration is 3 × on the semi-insulating GaAs substrate 61 by using the MOVPE method (metal organic vapor phase epitaxy). 10¹⁵cm^-3P with a thickness of 300 nm (= 3000 mm)^-After epitaxially growing the type GaAs channel layer 62, a solid source tertiary butyl gallium sulfacubene is sublimated in vacuum to deposit a GaS layer 63 having a thickness of 5 nm to 20 nm, and then plasma enhanced CVD A SiN layer 64 having a thickness of 50 nm is deposited by the method.
[0013]
Next, using the resist pattern (not shown) as a mask, etching was performed using buffered hydrofluoric acid to selectively remove the exposed SiN layer 64 to form openings for forming source / drain electrodes. After that, the resist pattern is removed, and then a gate electrode 66, a source electrode 67, and a drain electrode 68 made of a Ti / Pt / Au layer are formed by a lift-off method using a new resist pattern (not shown). Thus, the basic structure of the compound semiconductor MISFET is completed.
In this case, the gate insulating film 65 has a two-layer structure of the GaS layer 63 and the SiN layer 64.
[0014]
In such an improved MISFET, since the source electrode 67 and the drain electrode 68 are provided via a GaS layer that is considerably thicker than that of the monolayer, p^-The pinning effect on the surface of the type GaAs channel layer 62 remains released, and as a result, a low-resistance ohmic contact can be formed.
[0015]
The GaS film thickness dependence of the contact resistivity in this case has already been disclosed in the above Japanese Patent Application No. 9-351633, and this situation will be described again with reference to FIG.
Refer to FIG.
FIG. 8B shows the contact resistivity (Ω · cm) when a Ti electrode is formed on GaAs by changing the thickness of the GaS layer and then heat-treated at 300 ° C. for 10 minutes.²), And the resistivity at about 150 mm (= 15 nm) becomes the lowest through a quasi-Schottky barrier from a high resistance Schottky barrier with a film thickness of 0 mm. When the thickness is about 20 nm, it becomes a quasi-Schottky barrier again, and above that, it becomes a high-resistance insulating film.
Therefore, by appropriately selecting the thickness of the GaS layer, it can be used as an insulating film or a film for reducing contact resistance.
The film thickness of the GaS layer in this case is the film thickness at the time of deposition, and a reaction layer that has reacted with Ti is formed on the Ti electrode side by heat treatment, and the actual film thickness is reduced below this value. It is considered a thing.
[0016]
[Problems to be solved by the invention]
However, in the case where the gate insulating film is constituted only by the GaS layer as in the MISFET disclosed in Japanese Patent Laid-Open No. 10-98185, if the GaS layer serving as the gate insulating film is thinned, the dielectric breakdown voltage of the GaS layer is low. In addition, there is a problem that a large leak current flows in the MIS structure.
[0017]
Further, in the improved MISFET shown in FIG. 8A, in the heat treatment step for forming the ohmic electrode, the reaction between the GaS layer and the metal electrode proceeds, and the ohmic characteristics are optimized. If the GaS layer is used simultaneously as an insulating film and a film for reducing contact resistance, the film thickness of the GaS layer is about as follows. The insulation film and the contact resistance reduction are in a trade-off relationship with each other, and the film thickness to be employed becomes a problem, and furthermore, the heat treatment time is also a problem, so the degree of freedom of the process is limited. There is.
[0018]
Further, in the improved MISFET shown in FIG. 8A, since the growth apparatuses for depositing the GaS layer and the SiN layer are completely different, the configuration of the manufacturing apparatus becomes complicated, and the number of manufacturing processes increases accordingly. Therefore, there is a problem that the throughput is lowered.
[0019]
  Therefore, the present inventionIII- Group VIn compound semiconductorsWorldIt is an object of the present invention to reduce the surface state density and the ohmic resistance with a simple manufacturing apparatus configuration.
[0020]
[Means for Solving the Problems]
  FIG. 1 is an explanatory diagram of the principle configuration of the present invention. Means for solving the problems in the present invention will be described with reference to FIG.
  See Figure 1
  (1) In the compound semiconductor device of the present invention, the surface of the compound semiconductor layer 2 made of a III-V compound semiconductor is formed.coverMore than two atomic layers thickA first GaS layer and,The first GaS layer;At least someCovering firstGaNWith an insulating film including a layerIt is characterized by that.
[0021]
  Like this,III- Made of Group V compound semiconductorBy covering the surface of the compound semiconductor layer 2 with a layer 3 containing at least GaSTerminate surface dangling bonds with S (sulfur)Reduce interface state densityIt is possible,In addition, by making the film thickness more than two atomic layers, the thermal stability can be improved and the contact resistance can be reduced as is apparent from FIG. 8B.In In difficult to reduce interface state density _x Al _y Ga _1-xy As _w P _1-W And nitride compound semiconductors III- Suitable for Group V compound semiconductors.
  Especially in the case of GaAsCancel pinningcan do.
  The “layer 3 containing at least GaS” means a GaS layer itself, a III-VI compound semiconductor layer such as an AlGaS layer or a GaSSe layer, or a layer mixed with other metal elements.
[0022]
Further, by covering the layer 3 containing at least GaS with the GaN layer 4 instead of the SiN layer, the manufacturing apparatus can be made common, thereby simplifying the manufacturing process and improving the throughput.
In particular, when the compound semiconductor layer 2 is grown on the semi-insulating compound semiconductor substrate 1, the compound semiconductor layer 2, the layer 3 containing at least GaS, and the GaN layer 4 can be manufactured using the same manufacturing apparatus.
[0023]
Further, by covering the layer 3 containing at least GaS with the GaN layer 4, it is possible to prevent peeling of the layer 3 containing at least GaS in a plasma ashing process or the like, and at least include GaS when an ohmic electrode is provided. It becomes easy to control the film thickness of the layer 3 within the optimum range.
[0024]
  (2) Further, the present invention provides the above (1),The insulating film further includes a second GaS layer covering the first GaN layer.It is characterized by that.
[0025]
In general, since it is not easy to deposit the GaN layer 4 thickly on the layer 3 containing at least GaS, it is possible to increase the overall thickness by further providing a layer containing at least GaS on the GaN layer 4. This can increase the withstand voltage.
[0026]
  (3) Further, the present invention provides the above (1),The insulating film further includes a second GaS layer that covers the first GaN layer and a second GaN layer that covers the surface of the second GaS layer.It is characterized by that.
[0027]
Thus, by making the uppermost layer a GaN layer, process instability of a layer containing at least GaS, such as peeling in a plasma ashing process or the like, can be improved.
[0030]
  (4) Moreover, the present invention provides any of the above (1) to (3),At least one ohmic electrode in ohmic contact with the compound semiconductor layer is formed on the first GaS layer.It is provided so that it may touch.
[0031]
In this manner, by providing ohmic electrodes such as the source electrode 7 and the drain electrode 8 on the surface of the layer 3 containing at least GaS exposed by removing the GaN layer 4 covering the surface, the film of the layer 3 containing at least GaS. Since the thickness can be accurately controlled according to the deposition conditions, the contact resistance can be reduced with good reproducibility. When applied to HBT or the like, for example, only the base electrode may be provided on the surface of the layer 3 containing at least GaS, and the emitter electrode or the collector electrode may be provided directly on the surface of the compound semiconductor layer 2.
[0032]
  (5) Moreover, the present invention provides any of the above (1) to (3),At least one ohmic electrode in ohmic contact with the compound semiconductor layer is formed on the first GaN layer.It is provided so that it may touch.
[0033]
As described above, since the thickness of the GaN layer 4 is generally thin, even if an electrode is provided on the surface of the GaN layer 4, the electrode and the compound semiconductor layer 2 are ohmically connected via a tunnel current, whereby contact holes are formed. Therefore, the number of manufacturing steps can be reduced.
[0034]
  (6) Moreover, the present invention provides the above (4) or (5),A gate electrode formed on the insulating layer;It is characterized by that.
  (7) Further, in the present invention according to any one of (1) to (6), the compound semiconductor layer includes GaAs.
[0035]
Thus, by using a laminated structure of the layer 3 containing at least GaS and the GaN layer 4, ohmic electrodes such as the low-resistance source electrode 7 and the drain electrode 8 have a low interface state density and an excellent withstand voltage. Since a metal-insulator-semiconductor structure (MIS structure) can be formed at the same time, an MIS type compound semiconductor device can be realized.
In this case, the gate insulating film 5 is a laminated structure film of the layer 3 containing at least GaS and the GaN layer 4.
[0036]
DETAILED DESCRIPTION OF THE INVENTION
Here, with reference to FIG. 2, the manufacturing process of the MISFET according to the first embodiment of the present invention will be described.
See Fig. 2 (a)
First, on the semi-insulating GaAs substrate 11, using the MOVPE method, the thickness is, for example, 300 nm, and the carbon concentration is, for example, 3 × 10.¹⁵cm^-3P to be the channel layer of^-After the type GaAs layer 12 is grown, the thickness is increased by sublimating tertiary butyl gallium sulfacuben, which is a solid material housed in the chamber, at a substrate temperature of 350 to 500 ° C., for example, 350 ° C. An amorphous GaS layer 13 having a thickness of 2 atomic layers to 20 nm, for example, 10 nm is grown.
[0037]
Subsequently, in a state where the substrate temperature is 400 to 450 ° C., for example, 400 ° C. in the same chamber, 1 sccm of nitrogen radicals excited by 0.25 sccm of TEGa (triethyl gallium) and high frequency power of 350 W is flowed. Thus, the GaN layer 14 having a thickness of 0.5 to 5 nm, for example, 5 nm is grown on the GaS layer 13.
In this case, the growth rate of the GaN layer 14 is about 20 to 40 nm / hour.
[0038]
Refer to FIG.
Next, hot H is used using the resist pattern 15 provided with the openings 16 corresponding to the source / drain regions as a mask._ThreePO_FourThe GaS layer 13 is exposed by selectively removing the GaN layer 14 by performing wet etching using.
[0039]
Refer to FIG.
Next, after removing the resist pattern 15, a new resist pattern 17 having openings corresponding to the gate electrode and the source / drain electrode is provided, and a Ti film having a thickness of, for example, 10 nm is formed on the entire surface. For example, the Ti / Pt / Au layer 18 is deposited by sequentially depositing a Pt film having a thickness of 30 nm and an Au film having a thickness of, for example, 300 nm.
[0040]
Refer to FIG.
Next, the resist pattern 17 is removed, and the Ti / Pt / Au layer 18 deposited on the resist pattern 17 is lifted off, thereby forming the gate electrode 20, the source electrode 21, and the drain electrode 22.
In this case, the gate insulating film 19 has a laminated structure of the GaS layer 13 and the GaN layer 14.
[0041]
In the MISFET of the first embodiment, p^-Since the GaS layer 13 is provided so as to be in contact with the type GaAs layer 12, the interface state density is 10 by the termination effect by the GaS layer 13.¹¹eV^-1cm^-2Can be reduced to p^-An inversion layer, that is, an n-type channel layer is formed on the surface of the type GaAs layer 12.
[0042]
Further, since the gate insulating film 19 has a two-layer structure of the GaS layer 13 and the GaN layer 14, the low dielectric breakdown voltage of the GaS layer 13 can be compensated for by the wide gap GaN layer 14. Withstand voltage can be increased and leakage current can be reduced.
[0043]
The operation of the GaN layer 14 in this case is the same as that of the SiN layer 64 shown in FIG. 8A described above, but the GaN layer 14 is different from the SiN layer 64 in the same chamber as the GaS layer 13. Therefore, the manufacturing apparatus is simplified, and the throughput is improved because a cleaning process or the like when moving between the manufacturing apparatuses becomes unnecessary.
[0044]
Further, since the source electrode 21 and the drain electrode 22 are provided via the GaS layer 13 having a thickness of, for example, 10 nm, the pinning effect is canceled and the ohmic electrodes having a low contact resistivity can be formed.
In addition, since the film thickness of the GaS layer 13 in this case is determined by the film thickness at the time of film formation, the contact resistivity can be accurately controlled within the optimum range shown in FIG. A semiconductor MISFET can be manufactured with good reproducibility.
[0045]
Next, a MISFET according to a second embodiment of the present invention will be described with reference to FIG.
3A is a cross-sectional view when the ohmic electrode is provided on the GaS layer, and FIG. 3B is a cross-sectional view when the ohmic electrode is provided via the GaN layer. .
See Fig. 3 (a)
First, in exactly the same manner as in the first embodiment, the thickness is, for example, 300 nm and the carbon concentration is, for example, 3 × 10 on the semi-insulating GaAs substrate 11 by using the MOVPE method.¹⁵cm^-3P to be the channel layer of^-After the growth of the type GaAs layer 12, the tertiary butyl gallium sulfacuben housed in the chamber is sublimated at a substrate temperature of 350 to 500 ° C., for example, 350 ° C. A GaS layer 13 in an amorphous state of 20 nm, for example, 10 nm is grown.
[0046]
Subsequently, in the same chamber, with the substrate temperature set at 400 to 450 ° C., for example, 400 ° C., 1 Gacm of nitrogen radicals excited by 0.25 sccm of TEGa and high frequency power of 350 W are allowed to flow, thereby causing GaS layers to flow. A GaN layer 23 having a thickness of 0.5 to 5 nm, for example, 2 nm, is grown on 13.
[0047]
Subsequently, by sublimating tertiary butyl gallium sulfacuben in the same chamber at a substrate temperature of 350 to 500 ° C., for example, 350 ° C., an amorphous film having a thickness of 2 to 20 nm, for example, 10 nm. The GaS layer 24 in the state is grown.
[0048]
Next, a resist pattern (not shown) provided with openings corresponding to the source / drain regions is used as a mask._ThreePO_FourThe GaS layer 24 is selectively removed to expose the GaN layer 23 by wet etching using a mixed solution of + HCl, and then hot H_ThreePO_FourThe GaS layer 13 is exposed by selectively removing the GaN layer 23 by performing wet etching using.
[0049]
Thereafter, in exactly the same manner as in the first embodiment, after removing the resist pattern, a new resist pattern having openings corresponding to the gate electrode and the source / drain electrodes is provided. For example, a Ti / Pt / Au layer is deposited by sequentially depositing a 10 nm Ti film, a Pt film having a thickness of, for example, 30 nm, and an Au film having a thickness of, for example, 300 nm, and then a resist pattern. Then, the Ti / Pt / Au layer deposited on the resist pattern is lifted off to form the gate electrode 20, the source electrode 21, and the drain electrode 22.
In this case, the gate insulating film 25 has a laminated structure of GaS layer 13 / GaN layer 23 / GaS layer 24.
[0050]
The device characteristics of the MISFET of the second embodiment are basically the same as those of the first embodiment. However, in the GaN layer deposition process at a relatively low temperature, the device characteristics of the first embodiment are the same. In general, it is not easy to deposit the GaN layer 13 thickly. Instead of thinning the GaN layer 23, the gate insulation breakdown voltage is increased by increasing the total thickness of the GaS layer.
[0051]
In this case, the GaS layer 13 may be 20 nm and the GaS layer 24 may be omitted. In this case, the GaS layer 24 in the source / drain region is too thick, and the contact resistivity is too high. Since the thin GaN layer 23 is used as an etching stopper in the second embodiment, the contact resistivity can be accurately controlled within the optimum range shown in FIG. A MISFET can be manufactured with good reproducibility.
[0052]
Refer to FIG.
The MISFET shown in FIG. 3B is a modification of FIG. 3A, and the film forming process is the same as that in FIG. In forming the portion, only the GaS layer 24 is removed, and the thin GaN layer 23 is left as it is, and the source electrode 21 and the drain electrode 22 are provided on the surface of the GaN layer 23.
[0053]
In this case, since the GaN layer 23 is very thin, about 2 nm, the source electrode 21 and the drain electrode 22 are connected to the p-type via the tunnel current.^-The type GaAs layer 12 is ohmicly connected.
By adopting such a configuration, the etching process of the GaN layer 23 becomes unnecessary, so that the number of manufacturing processes can be reduced and the throughput is improved.
[0054]
Next, a MISFET according to a third embodiment of the present invention will be described with reference to FIG.
4A is a cross-sectional view when the ohmic electrode is provided on the GaS layer, and FIG. 4B is a cross-sectional view when the ohmic electrode is provided via the GaN layer. .
See Fig. 4 (a)
First, in exactly the same manner as in the first embodiment, the thickness is, for example, 300 nm and the carbon concentration is, for example, 3 × 10 6 on the semi-insulating GaAs substrate 11 by using the MOVPE method.¹⁵cm^-3P to be the channel layer of^-After the growth of the type GaAs layer 12, the tertiary butyl gallium sulfacuben housed in the chamber is sublimated at a substrate temperature of 350 to 500 ° C., for example, 350 ° C. A GaS layer 13 in an amorphous state of 20 nm, for example, 10 nm is grown.
[0055]
Subsequently, in the same chamber, with the substrate temperature set at 400 to 450 ° C., for example, 400 ° C., 1 Gacm of nitrogen radicals excited by 0.25 sccm of TEGa and high frequency power of 350 W are allowed to flow, thereby causing GaS layers to flow. A GaN layer 23 having a thickness of 0.5 to 5 nm, for example, 2 nm, is grown on 13.
[0056]
Subsequently, by sublimating tertiary butyl gallium sulfacuben in the same chamber at a substrate temperature of 350 to 500 ° C., for example, 350 ° C., an amorphous film having a thickness of 2 to 20 nm, for example, 10 nm. After the growth of the GaS layer 24 in the state, the TEGa was subsequently excited by high-frequency power of 0.25 sccm and 350 W in a state where the substrate temperature was 400 to 450 ° C., for example, 400 ° C., in the same chamber. By flowing 1 sccm of nitrogen radicals, a GaN layer 26 having a thickness of 0.5 to 5 nm, for example, 2 nm is grown on the GaS layer 24.
[0057]
Next, hot H is used using a resist pattern (not shown) provided with openings corresponding to the source / drain regions as a mask._ThreePO_FourAfter selectively removing the GaN layer 26 and exposing the GaS layer 24 by performing wet etching using_ThreePO_FourThe GaS layer 24 is selectively removed to expose the GaN layer 23 by wet etching using a mixed solution of + HCl, and then again hot H_ThreePO_FourThe GaS layer 13 is exposed by selectively removing the GaN layer 23 by performing wet etching using.
[0058]
Thereafter, in exactly the same manner as in the first embodiment, after removing the resist pattern, a new resist pattern having openings corresponding to the gate electrode and the source / drain electrodes is provided. For example, a Ti / Pt / Au layer is deposited by sequentially depositing a 10 nm Ti film, a Pt film having a thickness of, for example, 30 nm, and an Au film having a thickness of, for example, 300 nm, and then a resist pattern. Then, the Ti / Pt / Au layer deposited on the resist pattern is lifted off to form the gate electrode 20, the source electrode 21, and the drain electrode 22.
In this case, the gate insulating film 27 has a laminated structure of GaS layer 13 / GaN layer 23 / GaS layer 24 / GaN layer 26.
[0059]
The element characteristics of the MISFET of the third embodiment are basically the same as those of the second embodiment, but the GaS layer 24 is easily peeled off in the plasma ashing process for removing the resist pattern. Since there is process instability, the process stability is improved by providing the GaN layer 26 as the uppermost layer.
Further, by providing the GaN layer 26, the dielectric strength of the gate is further improved.
[0060]
Also in this third embodiment, since the lower GaN layer 23 is used as an etching stopper, the contact resistivity can be accurately controlled within the optimum range shown in FIG. Thereby, the compound semiconductor MISFET can be manufactured with good reproducibility.
[0061]
Refer to FIG.
The MISFET shown in FIG. 4B is a modification of FIG. 4A and corresponds to the MISFET of FIG. 3B, and the film forming process is the same as in FIG. 4A. Although the description is omitted, when forming the opening corresponding to the source / drain region, the GaN layer 26 and the GaS layer 24 are simply removed, leaving the thin GaN layer 23 as it is, and on the surface of the GaN layer 23. A source electrode 21 and a drain electrode 22 are provided.
[0062]
Also in this case, since the GaN layer 23 is very thin, about 2 nm, the source electrode 21 and the drain electrode 22 are connected to the p-type via the tunnel current.^-The type GaAs layer 12 is ohmicly connected.
By adopting such a configuration, the etching process of the GaN layer 23 becomes unnecessary, so that the number of manufacturing processes can be reduced and the throughput is improved.
[0063]
Next, a HEMT according to a fourth embodiment of the present invention will be described with reference to FIG.
5A is a cross-sectional view of the HEMT when the ohmic electrode is provided on the GaS layer, and FIG. 5B is a HEMT when the ohmic electrode is provided via the GaN layer. It is sectional drawing.
Refer to FIG.
First, TEGa (triethyl gallium), AsH on the semi-insulating GaAs substrate 31 using the MOVPE method._ThreeAnd H as a carrier gas₂After flowing an undoped i-type GaAs buffer layer 32 having a thickness of, for example, 500 nm, TMIn (trimethylindium) is added to form a thickness of, for example, 14 nm and an In composition ratio of 0.2. A non-doped i-type InGaAs channel layer 32 and then AsH_ThreePH_ThreeSiH as an impurity source_FourFor example, the thickness is 25 nm and the Si concentration is 2 × 10¹⁸cm^-3Then, an n-type InGaP carrier supply layer 33 having an In composition ratio of 0.49 is grown, and then the supply of TMIn is stopped and PH_ThreeAgain AsH_ThreeThe thickness is, for example, 70 nm, and the Si concentration is, for example, 5 × 10¹⁸cm^-3N⁺A type GaAs contact layer 35 is deposited.
[0064]
Then n⁺Type GaAs contact layer 35 with H_ThreePO_Four+ H₂O₂+ H₂After forming a gate recess portion by patterning so as to correspond to the source / drain regions by wet etching using a mixed solution of O, it is accommodated in a GaS deposition chamber, and tertiary butyl gallium sulfacubene is contained in the chamber. , By sublimation at a substrate temperature of 350 to 500 ° C., for example 350 ° C., to grow an amorphous GaS layer 36 having a thickness of 2 to 20 nm, for example 10 nm, and subsequently in the same chamber, By flowing 1 sccm of nitrogen radicals excited by high frequency power of 0.25 sccm and 350 W of TEGa in a state where the substrate temperature is 400 to 450 ° C., for example, 400 ° C., the thickness is increased on the GaS layer 36. GaN layer 37 of 0.5-5 nm, for example 2 nm is grown That.
[0065]
Next, hot H is used using a resist pattern (not shown) provided with an opening for forming a gate as a mask._ThreePO_FourAfter selectively removing the GaN layer 37 by performing wet etching using_ThreePO_FourThe GaS layer 36 is selectively removed by wet etching using a mixed solution of HCl and HCl.
[0066]
Next, after removing the resist pattern, a new resist pattern (not shown) having openings corresponding to the source / drain regions is used as a mask to form hot H_ThreePO_FourAfter selectively removing the GaN layer 37 by performing wet etching using, an Al film having a thickness of, for example, 500 nm is deposited on the entire surface, and lifted off together with the resist pattern to thereby form the source electrode 39 and the drain electrode 40. Form.
[0067]
Next, after removing the resist pattern, a new resist pattern (not shown) having an opening for forming a gate electrode is provided, and an Al film having a thickness of, for example, 500 nm is deposited on the entire surface, together with the resist pattern. The basic structure of the HEMT is completed by forming the gate electrode 38 by lifting off.
[0068]
In the HEMT according to the fourth embodiment of the present invention, the channel region excluding the portion in contact with the gate electrode 38 in the surface of the n-type InGaP carrier supply layer 34 is covered with the GaS layer 36. The dangling bonds on the surface of the type InGaP carrier supply layer 34 can be stabilized by termination with S, and thereby the interface state density is reduced, so that the operation of the HEMT can be stabilized.
[0069]
Also in this case, since the source electrode 39 and the drain electrode 40 are provided via the GaS layer 36 having a film thickness of about 10 nm, the source electrode 39 and the drain electrode 40 can be low-resistance ohmic electrodes.
[0070]
In the fourth embodiment, since the surface of the GaS layer 36 is covered with the GaN layer 37, the GaS layer 36 does not peel off when performing plasma ashing to remove the resist pattern. , Process stability is improved.
[0071]
Refer to FIG.
The HEMT shown in FIG. 5 (b) is a modification of FIG. 5 (a), and the film forming process is the same as that in FIG. Since the electrode 39 and the drain electrode 40 are provided and it is only necessary to provide an opening for forming a gate, the number of etching steps can be reduced and the throughput is improved.
[0072]
In this case, since the gate electrode 38, the source electrode 39, and the drain electrode 40 can be formed by a single film formation process and a lift-off process, the number of manufacturing processes can be further reduced.
Since the GaN layer 37 is very thin, about 2 nm, the source electrode 39, the drain electrode 40, and the n⁺The type GaAs contact layer 35 is connected to the ohmic contact.
[0073]
Next, an HBT according to a fifth embodiment of the present invention will be described with reference to FIG.
6A is a cross-sectional view of the HBT when the ohmic electrode is provided on the GaS layer, and FIG. 6B is a cross-sectional view of the HBT when the ohmic electrode is provided via the GaN layer. It is sectional drawing.
See Fig. 6 (a)
First, TEGa, AsH is formed on a semi-insulating GaAs substrate 41 by using the MOVPE method._ThreeSiH as impurity source_FourAnd H as a carrier gas₂For example, the thickness is 500 nm and the Si concentration is 3 × 10¹⁸cm^-3N⁺Type GaAs subcollector layer 42 and, for example, a thickness of 450 nm and a Si concentration of 3 × 10¹⁶cm^-3The n-type GaAs collector layer 43 is sequentially deposited.
[0074]
Next, SiH_FourCBr_FourFor example, the thickness is 70 nm and the C concentration is 4 × 10.¹⁹cm^-3P⁺After depositing the type GaAs base layer 44, CBr_FourAgain SiH_FourAnd switch to AsH_ThreePH_ThreeFor example, the thickness is 50 nm and the Si concentration is 3 × 10.¹⁷cm^-3Then, an n-type InGaP emitter layer 45 having an In composition ratio of 0.49 is deposited, and then the supply of TMIn is stopped and PH_ThreeAsH_ThreeFor example, n having a thickness of 200 nm⁺A type GaAs emitter cap layer 46 is deposited.
N⁺The type GaAs emitter cap layer 46 has a Si concentration of 3 × 10 5 at a thickness of 150 nm on the n-type InGaP emitter layer 45 side.¹⁷cm^-3And the Si concentration in the remaining 50 nm thick portion on the upper side is 3 × 10¹⁸cm^-3It is.
[0075]
Then, by applying mesa etching, n⁺By forming an emitter mesa composed of the n-type GaAs emitter cap layer 46 and the n-type InGaP emitter layer 45, and then performing mesa etching again, p⁺A base mesa composed of the n-type GaAs base layer 44 and the n-type GaAs collector layer 43 is formed.
In this mesa etching process, the GaAs layer is etched by H_ThreePO_Four+ H₂O₂+ H₂For etching InGaP using a mixed solution of O, H_ThreePO_FourUse a mixture of HCl and HCl
When this HBT is integrated, mesa etching reaching the semi-insulating GaAs substrate 41 is performed to form a collector mesa in order to perform element isolation.
[0076]
The substrate is then housed in a GaS deposition chamber and the tert-butyl gallium sulfacuben is sublimated in the chamber at a substrate temperature of 350-500 ° C., eg, 350 ° C., to achieve a thickness of 2 atomic layers. A GaS layer 47 having an amorphous state of ˜20 nm, for example, 10 nm is grown, and subsequently, TEGa is 0.25 sccm and 350 W in a state where the substrate temperature is 400 to 450 ° C., for example, 400 ° C., in the same chamber. By flowing 1 sccm of nitrogen radicals excited by the high-frequency power, a GaN layer 48 having a thickness of 0.5 to 5 nm, for example, 2 nm is grown on the GaS layer 47.
[0077]
Next, hot H is used using a resist pattern (not shown) provided with an opening for forming a base electrode as a mask._ThreePO_FourAfter selectively removing the GaN layer 48 by performing wet etching using a Pt film, a Pt film having a thickness of 20 nm and an Au film having a thickness of 150 nm are sequentially deposited on the entire surface, and then removed together with the resist pattern, thereby removing the base electrode. 50 is formed.
[0078]
Next, after removing the resist pattern, a new resist pattern (not shown) having openings for forming an emitter electrode and a collector electrode is provided._ThreePO_FourAfter selectively removing the GaN layer 48 by performing wet etching using, for example, a 10 nm Ti film, a 30 nm Pt film, and a 300 nm Au film are formed on the entire surface. The basic structure of the HBT is completed by sequentially depositing and lifting off together with the resist pattern to form the emitter electrode 49 and the drain electrode 51.
[0079]
In the HBT according to the fifth embodiment of the present invention, p⁺Since the exposed surface of the n-type GaAs base layer 44 and the side surface of the n-type InGaP emitter layer 45 are covered with the GaS layer 47, the region in the vicinity of the pn junction between the base and emitter is terminated by S, and the interface state density is reduced. As a result, the surface recombination in the pn junction region is suppressed, so that the current gain can be increased.
[0080]
Also in this case, since the emitter electrode 49, the base electrode 50, and the collector electrode 51 are provided via the GaS layer 36 having a thickness of about 10 nm, the emitter electrode 49, the base electrode 50, and the collector electrode 51 are provided. Can be a low-resistance ohmic electrode.
[0081]
Also in the fifth embodiment, since the surface of the GaS layer 47 is covered with the GaN layer 48, the GaS layer 47 does not peel off in the plasma ashing process for removing the resist pattern. Process stability is improved.
[0082]
Refer to FIG.
The HBT shown in FIG. 6B is a modified example of FIG. 6A, and the film forming process is the same as that in FIG. Since the electrode 49, the base electrode 50, and the collector electrode 51 are provided and it is not necessary to remove the GaN layer 48, the number of etching steps can be reduced and the throughput is improved.
Since the GaN layer 48 is very thin, about 2 nm, the emitter electrode 49, the base electrode 50, and the collector electrode 51 become ohmic electrodes due to the tunnel current.
[0083]
As mentioned above, although each embodiment of the present invention has been described, the present invention is not limited to the configuration described in each embodiment, and various modifications are possible.
For example, in the first to third embodiments described above, the semi-insulating GaAs substrate 11 is used as a starting material, and p is further formed thereon.^-The type GaAs layer 12, the GaS layer 13, the GaN layers 13 and 23, etc. are formed by a series of growth processes.^-An epitaxial wafer on which the type GaAs layer 12 is grown may be used as a starting material.
[0084]
When such an epitaxial wafer is used, the surface of the epitaxial wafer is naturally oxidized by performing a treatment for 10 minutes at a substrate temperature of 500 ° C., for example, using trisdimethylaminoarsine in a GaS deposition chamber. The film is removed and subsequently processed using HCl gas, for example, at a substrate temperature of 500 ° C., p^-After the surface of the type GaAs layer 12 is etched by several atomic layers to clean the surface, the GaS layer 13 and the like may be deposited.
[0085]
Further, such a cleaning process is desirably performed before the film forming process of the GaS layers 36 and 47 performed after the semiconductor layer etching process in the fourth and fifth embodiments. In the embodiment, several atomic layers of the surface of the n-type InGaP carrier supply layer 34 are also removed.
[0086]
In the first to third embodiments, the source electrode 21 and the drain electrode 22 are provided on the GaS layer 13 or via the GaN layer 23. However, the GaS layer 13 is also selectively formed. It is possible to remove and form an alloy ohmic electrode such as a three-layer structure film made of 20 nm Au / Ge film / 5 nm Ni film / 300 nm Au film in a separate process from the gate electrode 20. The same applies to the case of the emitter electrode 49 and the collector electrode 51 of the fifth embodiment.
[0087]
In the fourth embodiment, the HEMT is described. However, by replacing the i-type InGaAs channel layer 33 with an n-type InGaAs channel layer, it is possible to operate as a MESFET. Such MESFETs are also targeted.
[0088]
In each of the above-described embodiments, the GaS layer is formed using tertiary butyl gallium sulfacuben. However, the GaS layer is not limited to tert-butyl gallium sulfacuben, and 2 [(tBu)₂Ga (μ-SH)]₂May be used.
[0089]
In each of the above-described embodiments, the main purpose is to stabilize the surface of GaAs, which exhibits a remarkable pinning effect. However, as in the fourth and fifth embodiments, the surface stabilization of InGaP is also performed. Even if there is no direct relationship to the cancellation of the pinning effect, the interface state density can be reduced by terminating the surface dangling bonds with S, which contributes to the improvement of device characteristics. And therefore In_xAl_yGa_1-xyAs_wP_1-WAnd In_xAl_yGa_1-xyAs_wN_1-wIt can also be used for surface stabilization of other III-V compound semiconductors represented by
[0090]
In each of the above embodiments, the surface stabilization layer is described as a GaS layer. However, the layer is not limited to a pure GaS layer, and may be a III-VI group compound semiconductor such as AlGaS or GaSSe. Alternatively, a GaS layer or the like in which a metal component is doped or alloyed by a solid phase diffusion reaction with an ohmic electrode may be used.
[0091]
In each of the above embodiments, the GaS layer is regarded as an insulator and is effectively ohmicized by a tunnel current. However, it is not necessarily purely insulative, A metal component may be doped by a solid phase diffusion reaction to have some conductivity.
[0092]
In addition, the thickness of the GaS layer in each of the above embodiments is set to 2 to 20 nm, but in order to increase the thermal stability, it is more desirable that the film thickness is 5 nm or more. When the ohmic electrode is formed by removing the GaS layer, the GaS layer functions purely as an insulator, and thus may have a thickness of 20 nm or more.
[0093]
【The invention's effect】
According to the present invention, the surface of the compound semiconductor layer such as GaAs is covered with the two-layer structure film of the GaS layer and the GaN layer having a thickness of at least two atomic layers or more. In addition, the GaN layer can be used to stabilize the manufacturing apparatus, and the manufacturing apparatus can be shared, and the ohmic electrode is provided on the GaS layer or via the GaN layer. Since the contact resistance of the ohmic electrode can be reduced and the etching process can be reduced, it greatly contributes to high performance and low cost of the compound semiconductor device.
[0094]
In particular, when a GaAs layer is used as the compound semiconductor layer, the pinning effect can be canceled and a good inversion layer can be formed, which greatly contributes to the practical use of the compound semiconductor MISFET.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram of a basic configuration of the present invention.
FIG. 2 is an explanatory diagram of a manufacturing process of the MISFET according to the first embodiment of the invention.
FIG. 3 is a cross-sectional view of a MISFET according to a second embodiment of the present invention.
FIG. 4 is a cross-sectional view of a MISFET according to a third embodiment of the present invention.
FIG. 5 is a cross-sectional view of a HEMT according to a fourth embodiment of the present invention.
FIG. 6 is a cross-sectional view of an HBT according to a fifth embodiment of the present invention.
FIG. 7 is an explanatory diagram of a pinning effect and its prevention method in GaAs.
FIG. 8 is an explanatory diagram of the structure and contact resistivity of a conventional improved MISFET.
[Explanation of symbols]
1 Semi-insulating compound semiconductor substrate
2 Compound semiconductor layer
3 Layer containing at least GaS
4 GaN layer
5 Gate insulation film
6 Gate electrode
7 Source electrode
8 Drain electrode
11 Semi-insulating GaAs substrate
12 p^-Type GaAs layer
13 GaS layer
14 GaN layer
15 resist pattern
16 opening
17 resist pattern
18 Ti / Pt / Au layer
19 Gate insulation film
20 Gate electrode
21 Source electrode
22 Drain electrode
23 GaN layer
24 GaS layer
25 Gate insulation film
26 GaN layer
27 Gate insulation film
31 Semi-insulating GaAs substrate
32 i-type GaAs buffer layer
33 i-type InGaAs channel layer
34 n-type InGaP carrier supply layer
35 n⁺Type GaAs contact layer
36 GaS layer
37 GaN layer
38 Gate electrode
39 Source electrode
40 Drain electrode
41 Semi-insulating GaAs substrate
42 n⁺Type GaAs subcollector layer
43 n-type GaAs collector layer
44 p⁺Type GaAs base layer
45 n-type InGaP emitter layer
46 n⁺Type GaAs emitter cap layer
47 GaS layer
48 GaN layer
49 Emitter electrode
50 Base electrode
51 Collector electrode
61 Semi-insulating GaAs substrate
62 p^-Type GaAs channel layer
63 GaS layer
64 SiN layer
65 Gate insulation film
66 Gate electrode
67 Source electrode
68 Drain electrode

Claims (7)

Covering the surface of the III-V compound formed of a semiconductor compound semiconductor layer, a first GaS layer of two or more atomic layers thick, and a first GaN layer covering at least a portion of said first GaS layer A compound semiconductor device comprising an insulating film . 2. The compound semiconductor device according to claim 1 , wherein the insulating film further includes a second GaS layer covering the first GaN layer. The insulating layer, the first covering the GaN layer, and the second GaS layer, the compound of claim 1, wherein the further comprising a second second GaN layer covering the surface of the GaS layer Semiconductor device. 4. The compound semiconductor device according to claim 1 , wherein at least one ohmic electrode that is in ohmic contact with the compound semiconductor layer is provided so as to be in contact with the first GaS layer. 5. 4. The compound semiconductor device according to claim 1 , wherein at least one ohmic electrode that is in ohmic contact with the compound semiconductor layer is provided so as to be in contact with the first GaN layer. 5. The compound semiconductor device according to claim 4, further comprising a gate electrode formed on the insulating film .   The compound semiconductor device according to claim 1, wherein the compound semiconductor layer contains GaAs.

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