CN110120346B - LDMOS transistor and manufacturing method thereof - Google Patents
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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Abstract
The invention provides an LDMOS transistor and a manufacturing method thereof, wherein a shielding groove with a wide upper part and a narrow lower part is formed in a shielding insulating layer between a grid structure and a drain region, the average thickness of the shielding insulating layer at one side far away from the grid structure can be increased through the shielding groove, the electric field intensity below a metal layer is reduced, the electric field below the metal layer is more uniformly distributed, and the hot carrier injection effect at the edge of the grid structure is favorably inhibited, so that higher breakdown voltage and lower on-resistance can be realized, and the performance of a device is finally improved.
Description
Technical Field
The invention relates to the technical field of integrated circuit manufacturing, in particular to an LDMOS transistor and a manufacturing method thereof.
Background
The LDMOS (laterally diffused metal oxide semiconductor) has the advantages of good linearity, high gain, high withstand voltage, large output power, good thermal stability, high efficiency, good broadband matching performance, easy integration with MOS (metal oxide semiconductor) process and the like, has the price far lower than that of a gallium arsenide device, is a power device with high competitiveness, and is widely applied to power amplifiers of GSM (global system for mobile communications), PCS (personal communications), W-CDMA (W-code division multiple access) base stations, wireless broadcasting, nuclear magnetic resonance and other aspects. The breakdown voltage BV and the on-resistance Rdson of an LDMOS device are two important parameters for measuring the device performance. The higher breakdown voltage helps to ensure the stability of the device in actual operation, for example, the breakdown voltage of an LDMOS device with an operating voltage of 50V needs to reach more than 110V. The on-resistance Rdson directly affects the characteristics of the device, such as output power and gain.
Therefore, there is a need for a new LDMOS transistor and method of manufacturing the same that is capable of higher breakdown voltage and lower on-resistance.
Disclosure of Invention
The invention aims to provide an LDMOS transistor and a manufacturing method thereof, which can have higher breakdown voltage and lower on-resistance.
In order to achieve the above object, the present invention provides an LDMOS transistor comprising:
a semiconductor substrate;
the semiconductor device comprises a well region and a drift region which are different in doping type, wherein the well region and the drift region are transversely distributed in a semiconductor substrate and are separated by a first transverse distance, an active region is formed in the well region, and a drain region is formed in the drift region;
the gate structure is positioned on the surface of the semiconductor substrate and crosses the edge of the well region and the edge of the drift region, and the source region and the drain region are positioned on two sides of the gate structure;
the shielding insulating layer covers the top of the gate structure and extends to a part of the surface of the drift region, the shielding insulating layer exposes the drain region, a shielding groove which is wide at the top and narrow at the bottom is formed in the shielding insulating layer between the drain region and the gate structure and covers the surface of the drift region, and the shielding groove does not penetrate through the shielding insulating layer;
and the metal layer covers the surfaces of the source region and the shielding insulating layer.
Optionally, the LDMOS transistor further includes a body connection region having a doping type different from that of the source region, and the body connection region and the source region are laterally distributed in the well region and separated by a second lateral distance.
Optionally, a field oxide isolation structure is disposed between the body connection region and the source region, so that the body connection region and the source region are separated by another lateral distance.
Optionally, a field-free oxygen isolation structure is arranged between the drain region and the gate structure.
Optionally, the metal layer covers one end of the surface of the shielding insulating layer, covers an edge of the shielding trench close to the drain region, or covers an edge of the shielding insulating layer close to the drain region.
Optionally, the material of the shielding insulating layer includes at least one of silicon oxide, silicon nitride, and silicon oxynitride.
Optionally, the gate structure includes a gate dielectric layer and a gate electrode layer stacked on the surface of the semiconductor substrate in sequence, and a sidewall covering the sidewalls of the gate dielectric layer and the gate electrode layer, and the thickness of the shielding insulating layer at the bottom of the shielding trench is greater than or equal to the thickness of the gate dielectric layer.
Optionally, the shielding trench is shaped like a right trapezoid with a wide top and a narrow bottom in the film layer stacking direction, and a right angle of the right trapezoid is located at one side close to the gate structure; or the shielding groove is fan-shaped in the film layer overlapping direction; or, the shape of the shielding groove in the film layer superposition direction is a polygon with a right angle, one side of the polygon close to the gate structure is a right-angle side, and one side of the polygon far away from the gate structure is a continuous arc line segment or a multi-angle side formed by sequentially connecting a plurality of line segments with gradually increased slope.
Optionally, the acute angle of the right trapezoid is 45 ° to 70 °.
The invention also provides a manufacturing method of the LDMOS transistor, which comprises the following steps:
providing a semiconductor substrate, wherein a well region and a drift region which are different in doping type are formed in the semiconductor substrate, the well region and the drift region are laterally distributed in the semiconductor substrate and are separated by a first lateral distance, and a gate structure crossing the edge of the well region and the edge of the drift region is formed on the surface of the semiconductor substrate;
forming a shielding insulating layer with a shielding groove which is wide at the top and narrow at the bottom on the surfaces of the semiconductor substrate and the grid structure, wherein the shielding groove does not penetrate through the shielding insulating layer;
etching the shielding insulating layer to form a source contact hole at least exposing partial surface of the well region;
and forming a metal layer on the surfaces of the source contact hole and the rest of the shielding insulating layer.
Optionally, the process of forming a shielding insulating layer having a shielding trench with a wide top and a narrow bottom on the surface of the semiconductor substrate and the gate structure includes:
forming a shielding insulating layer with a first groove on the surfaces of the semiconductor substrate and the grid structure, wherein the shielding insulating layer with a certain thickness is reserved at the bottom of the first groove;
covering a sacrificial layer on the surface of the shielding insulating layer with the first groove, wherein the sacrificial layer is filled in the first groove;
etching the sacrificial layer and the shielding insulating layer in an upper area of one side of the first groove far away from the gate structure to form a second groove with a wide upper part and a narrow lower part, wherein the side wall of the second groove close to the gate structure is the sacrificial layer, the side wall far away from the gate structure is the shielding insulating layer, and the bottom of the second groove is lower than or equal to the bottom of the first groove;
and removing the sacrificial layer to form a shielding groove with a wide upper part and a narrow lower part on the shielding insulating layer.
Optionally, the process of forming the shielding insulating layer with the first trench on the surface of the semiconductor substrate and the gate structure includes:
forming a first insulating layer on a partial surface of a drift region of the semiconductor substrate;
sequentially forming a second insulating layer with a flattened top and a patterned mask layer with an opening positioned above the first insulating layer on the surfaces of the semiconductor substrate, the gate structure and the first insulating layer;
and etching the second insulating layer by using the patterned mask layer as a mask through a vertical etching process or an approximately vertical etching process to form a first groove exposing the surface of the first insulating layer.
Optionally, the material of the patterned mask layer includes a photoresist, the first insulating layer is a silicon oxide layer, and the second insulating layer is a silicon nitride layer and a silicon oxide layer stacked on the surface of the first insulating layer in sequence.
Optionally, the etching gas of the vertical etching process or the approximately vertical etching process includes a fluorocarbon-containing gas.
Optionally, after the first insulating layer is formed and before the second insulating layer is formed, performing source-drain ion implantation on the semiconductor substrate on both sides of the gate structure by using the gate structure and the first insulating layer as masks to form a source region in the well region, and forming a drain region in a drift region on a side of the first insulating layer away from the gate structure; or etching the shielding insulating layer to form a source contact hole exposing part of the surface of the well region, and simultaneously forming a drain contact hole exposing part of the surface of the drift region, wherein the drain contact hole is positioned in the shielding insulating layer at one side of the shielding groove far away from the gate structure, and after the source contact hole and the drain contact hole are formed, performing source-drain ion injection on the semiconductor substrate at the bottoms of the source contact hole and the drain contact hole by taking the gate structure and the shielding insulating layer as masks to form a source region in the well region and form a drain region in the drift region.
Optionally, after forming the source region, a body connection region having a doping type different from that of the source region and being further away from the gate structure relative to the source region is formed in the well region, and the body connection region and the source region are laterally distributed in the well region and separated by a second lateral distance.
Optionally, a field oxide isolation structure is disposed between the body connection region and the source region, so that the body connection region and the source region are separated by a second lateral distance; and/or a field-free oxygen isolation structure is arranged between the drain region and the grid structure.
Optionally, in the process of providing the semiconductor substrate, before or after forming the drift region, multiple ion implantations are performed on the semiconductor substrate on the side of the gate structure away from the drift region by using a multi-step ion implantation process to form the well region.
Optionally, the step of etching the sacrificial layer and the shielding insulating layer in an upper region of the first trench on a side away from the gate structure to form a second trench having a wide upper portion and a narrow lower portion includes:
firstly, forming a patterned photoresist layer on the surface of the sacrificial layer, wherein the patterned photoresist layer is provided with an opening which is offset from the first groove, and the opening is farther away from the grid structure relative to the first groove;
and then, etching the sacrificial layer and the shielding insulating layer by taking the patterned photoresist layer as a mask to form a second groove with a wide upper part and a narrow lower part.
Optionally, the sacrificial layer comprises an anti-reflective layer having a planar top surface.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
1. according to the LDMOS transistor, the average thickness of the shielding insulating layer at one side far away from the grid structure can be increased through the shielding groove, the electric field intensity below the metal layer is reduced, the electric field below the metal layer is more uniformly distributed, and the Hot Carrier Injection (HCI) effect at the edge of the grid structure is favorably inhibited, so that higher breakdown voltage and lower on-resistance can be realized, and finally the performance of the device is improved。
2. The manufacturing method of the LDMOS transistor only needs to change the rectangular groove formed in the shielding insulating layer into the shielding groove with the wide upper part and the narrow lower part, and the manufacturing process is simple.
Drawings
FIG. 1 is a schematic cross-sectional view of an LDMOS device;
fig. 2A to 2F are schematic cross-sectional views of LDMOS devices according to embodiments of the invention;
FIG. 3 is a flow chart of a method for fabricating an LDMOS device in accordance with an embodiment of the present invention;
fig. 4A to 4F are schematic cross-sectional views of devices in the method for manufacturing the LDMOS device according to the embodiment of the invention;
fig. 5A to 5B are schematic diagrams illustrating the results of performance tests performed on the LDMOS shown in fig. 1 and the LDMOS of the present invention, respectively.
Detailed Description
As described in the background, higher performance LDMOS transistors are required to have higher breakdown voltages and lower on-resistances. In order to obtain a higher breakdown voltage and a lower on-resistance, one current method is to form a high-performance LDMOS transistor by forming a shield insulating layer (shield plate) with a rectangular groove above a gate structure and a drain region, and covering a metal layer such as aluminum on the shield insulating layer, and the specific structure of this LDMOS transistor is shown in fig. 1 and includes: the semiconductor device includes a semiconductor substrate 100, an N-type drift region (N-drift)103 and a P-WELL (P-WELL)105 which are laterally distributed in the semiconductor substrate 100 and have a certain lateral spacing, a gate structure 101 formed on the surface of the semiconductor substrate 100, a sidewall 102 located on a sidewall of the gate structure 101, a drain region (N +, drain) 104 formed in the N-type drift region (N-drift)103, a source region (N +, source)107, a body connection region (P-body)108 and a field oxide isolation structure 106 isolating the source region 107 and the body connection region 108 formed in the P-WELL (P-WELL)105, a shielding insulating layer 109 covering the sidewall 102, the gate structure 101 and the surface of the N-type drift region 103 between the drain region 104 and the gate structure 101, and a metal layer 110 covering the source region 107 and the surface of the shielding insulating layer 109. A rectangular groove is formed in the shielding insulating layer 109 between the gate structure 101 and the drain region 104, and the metal layer 110 on the surface of the shielding insulating layer 109 can be used for homogenizing the field intensity distribution of the N-type drift region 104, reducing the gate-drain edge electric field, improving the breakdown voltage and reducing the on-resistance.
However, the breakdown voltage of the LDMOS transistor of this structure is difficult to increase again because the electric field at the edges of the gate structure is still high due to the accumulation of charges in the shield insulating layer 109 at the bottom of the rectangular trench due to the hot carrier injection effect.
Based on the LDMOS transistor and the manufacturing method thereof, the invention can improve the hot carrier injection effect at the bottom of the trench of the shielding insulating layer, homogenize the field intensity distribution of the drift region, reduce the grid-drain edge electric field, improve the breakdown voltage and reduce the on-resistance.
The present invention will be described in more detail with reference to the accompanying drawings, which are included to illustrate embodiments of the present invention.
Referring to fig. 2A to 2E, the present invention provides an LDMOS transistor, including: the semiconductor device comprises a semiconductor substrate 200, a gate structure 201, side walls 202, a drift region 203, a drain region 204, a well region 205, a field oxide isolation structure 206, a source region 207, a body connection region 208, a shielding insulating layer 209 and a metal layer 210.
The semiconductor substrate 100 may be any semiconductor material known to those skilled in the art, such as a bulk silicon substrate, a silicon-on-insulator substrate, a substrate with a silicon-germanium epitaxial layer on silicon, etc.; the well region 205 and the drift region 203 have different doping types, for example, when the LDMOS transistor is an N-type transistor, the doping type of the well region 205 is a P-type, that is, the well region 205 is a P-well (P-well), the doping type of the drift region 203 is an N-type, when the LDMOS transistor is a P-type transistor, the doping type of the well region 205 is an N-type, that is, the well region 205 is an N-well, the doping type of the drift region 204 is a P-type, and the well region 205 and the drift region 203 are laterally distributed in the semiconductor substrate 200 and separated by a lateral distance.
The gate structure 201 is located on the surface of the semiconductor substrate 200 and crosses the edge of the well region 205 and the edge of the drift region 203, i.e., the gate structure 201 covers not only the surface of the semiconductor substrate between the well region 205 and the drift region 204, but also partially covers the surface of the well region 205 and partially covers the surface of the drift region 203. The gate structure 201 may include a gate dielectric layer (not shown), such as silicon dioxide or a high-K dielectric having a dielectric constant K of 4 or more, and a gate electrode layer (such as polysilicon or metal) stacked on a surface of the gate dielectric layer. The sidewall spacers 202 are located on the surface of the semiconductor substrate 200 and cover the sidewalls of the gate structure 201.
The drain region 204 is located in the drift region 203, and the doping type is the same as that of the drift region 203, but the doping concentration is different, and there is no field oxide isolation structure between the drain region 204 and the gate structure 201. The body connection region 208 and the source region 207 are laterally distributed in the well region 205 and are separated from each other by another lateral distance through the field oxide isolation structure 206, the source region 207 is closer to the gate structure 201 than the body connection region 208, so that the source region 207 and the drain region 204 are located on both sides of the gate structure 201, the source region 207 is closer to the gate structure 201 than the drain region 204, the body connection region 208 and the source region 207 have different doping types, wherein the doping type of the body connection region 206 is the same as that of the well region 205, but the doping concentration is different, and the doping type of the source region 207 is the same as that of the drift region 203, but the doping concentration is different. The field oxide isolation structure 206 may be a field oxide isolation structure formed by a shallow trench isolation process, or may be a field oxide isolation structure formed by a local field oxide isolation process.
The shielding insulating layer 209 covers the sidewall 202, the gate structure 201, and the surface of the drift region 203 between the gate structure 201 and the drain region 204, and a shielding trench with a narrow top and a wide bottom is arranged in the region between the gate structure 201 and the drain region 204, the shielding trench extends from the surface of the shielding insulating layer 209 into the shielding insulating layer 209 without penetrating through the shielding insulating layer 209, and the thickness of the shielding insulating layer 209 reserved at the bottom of the shielding trench may be greater than or equal to the thickness of the gate dielectric layer in the gate structure 201. At this time, a portion of the shielding insulating layer 209 above the drift region 203 exposes only the drain region 204. Referring to fig. 2A, the shielding trench may have a shape of a right trapezoid 209a with a wide top and a narrow bottom in a film stacking direction (i.e., a direction from the bottom to the top), a right angle of the right trapezoid 209a is located at a side close to the gate structure 201, and an acute angle in the right trapezoid is 45 ° to 70 °; alternatively, referring to fig. 2C, the shape of the shielding trench in the film layer stacking direction is a polygon 209b with a right angle and an arc edge, the upper portion of the polygon 209b is wide, the lower portion of the polygon is narrow, a bottom angle Q of one side of the polygon 209b close to the gate structure 201 is a right angle, the bottom of the polygon is a horizontal line segment, and an edge of one side far away from the gate structure 201 is an arc segment; alternatively, referring to fig. 2D, the shielding trench is shaped as a sector 209c in the film layer overlapping direction, a side of the sector 209c close to the gate structure 201 is a vertical side, and a side of the sector 209c far away from the gate structure 201 is an arc segment, where the arc segment makes the shielding insulating layer 209 at the bottom of the shielding trench become thicker and thicker along the direction far away from the gate structure 201; alternatively, referring to fig. 2E, the shape of the shielding trench in the film layer stacking direction is a polygon 209d with a wide top and a narrow bottom and a right angle, one side of the polygon 209d with a wide top and a narrow bottom and a right angle, which is close to the gate structure 201, is a right angle, one side of the polygon 209d away from the gate structure 201 is a polygonal side formed by sequentially connecting a plurality of line segments with gradually increasing slopes, and the slope of the side with the largest slope among the polygonal sides is less than or equal to tg 70. The material of the shielding insulating layer 209 may be silicon oxide, silicon nitride, or silicon oxynitride, as shown in fig. 2A to 2E, or may include two or more of silicon oxide, silicon nitride, and silicon oxynitride, as shown in 2091, 2092, and 2093 in fig. 2F, that is, the material of the layer 2091 and the layer 2093 in fig. 2F may be the same or different; in fig. 2F, the material of layer 2092 is different from the material of layer 2091.
The metal layer 210 covers the source region 207, the sidewall of the gate structure 201, and the surface of the shielding insulating layer 209, and one end of the metal layer 210 covering the surface of the shielding insulating layer 209 may cover an edge of the shielding trench close to the drain region 204, as shown in fig. 2A and fig. 2C to fig. 2F, or may cover an edge of the shielding insulating layer 209 close to the drain region 204, as shown in fig. 2B, that is, the metal layer 210 may cover the shielding insulating layer 209 completely or partially. The material of the metal layer 210 includes at least one of Ti, Al, W, TiN, or TiW.
Referring to fig. 5A and 5B, the LDMOS transistor of the present invention and the LDMOS transistor shown in fig. 1 are tested and analyzed for saturation current Idsat (i.e. the maximum current flowing between the source and the drain at a certain gate voltage) and quality factor FOM2 (design of unit) at the same breakdown voltage BV, the LDMOS transistor of the present invention and the LDMOS transistor shown in fig. 1 were selected such that only the shape of the trench of the shield insulating layer in the region between the gate structure and the drain region was different, the shape of the shield trench of the shield insulating layer of the LDMOS transistor of the present invention in the region between the gate structure and the drain region was a right trapezoid, the shape of the trench of the shield insulating layer of the LDMOS transistor shown in fig. 1 was rectangular, and the width of the top opening of the shield trench of the LDMOS transistor of the present invention is the same as the width of the top opening of the trench of the shield insulating layer of the LDMOS transistor shown in fig. 1. As can be seen from FIGS. 5A and 5B, the saturation current Idsat and quality of the LDMOS transistor of the present invention are comparable to the LDMOS transistor of FIG. 1 having the same breakdown voltageFOM2 is relatively good, wherein FOM2, or device figure of merit, is related to the on-resistance, and the lower the value, the lower the on-resistance, and the better the device performance. That is, with the same Idsat and FOM2, the breakdown voltage of the LDMOS transistor of the present invention is higher and the on-resistance is lower. The LDMOS transistor is characterized in that the shielding insulating layer of the LDMOS transistor is provided with the shielding groove with the wide upper part and the narrow lower part above the drift region, when the width of the top opening of the shielding groove is the same as that of the top opening of the rectangular groove of the existing LDMOS transistor, the shielding groove can increase the average thickness of the shielding insulating layer at one side far away from the gate structure, reduce the electric field intensity below the metal layer, simultaneously enable the electric field below the metal layer to be more uniformly distributed, and is beneficial to inhibiting the Hot Carrier Injection (HCI) effect at the edge of the gate structure, thereby realizing higher breakdown voltage and lower on-resistance, and finally improving the performance of the device。
Referring to fig. 3, the present invention further provides a method for manufacturing an LDMOS transistor, which includes the following steps:
s1, providing a semiconductor substrate, wherein a well region and a drift region with different doping types are formed in the semiconductor substrate, the well region and the drift region are laterally distributed in the semiconductor substrate and are separated by a first lateral distance, and a gate structure crossing the edge of the well region and the edge of the drift region is formed on the surface of the semiconductor substrate;
s2, forming a shielding insulating layer with a shielding groove which is wide at the top and narrow at the bottom on the surfaces of the semiconductor substrate and the gate structure, wherein the shielding groove does not penetrate through the shielding insulating layer;
s3, etching the shielding insulating layer to form at least a source contact hole exposing partial surface of the well region;
and S4, forming a metal layer on the surfaces of the source contact hole and the rest shielding insulating layer.
Referring to fig. 4A, in step S1, the semiconductor substrate 400 provided may be any semiconductor material known to those skilled in the art, such as a bulk silicon substrate, a silicon germanium substrate, a silicon-on-insulator substrate, or a semiconductor substrate with doped semiconductor on a substrateA conductive epitaxial layer structure. When the semiconductor substrate 400 is used for forming an N-type LDMOS transistor subsequently, the semiconductor substrate 400 is doped in a P-type manner; when the semiconductor substrate 400 is used for forming a P-type LDMOS transistor subsequently, the semiconductor substrate 400 is doped in an N type, the ions of the P type doping are one or more of boron ions, indium ions and gallium ions, and the ions of the N type doping are one or more of phosphorus ions, arsenic ions and antimony ions. In step S1, a field oxygen isolation structure 401 located in the well region 405 to be formed may be formed in the semiconductor substrate 400 through a device isolation process (including photolithography, etching, dielectric filling, and other steps) such as a shallow trench isolation process or a local field oxygen isolation process; then, on the surface of the semiconductor substrate 400, a gate dielectric layer 402a is formed through a deposition process or a thermal growth process, and a gate electrode layer 402b is deposited on the surface of the gate dielectric layer 402 a; then, the gate electrode layer 402b and the gate dielectric layer 402a are sequentially etched through gate lithography and etching processes to form a gate structure 402, wherein the gate dielectric layer 402a may be silicon nitride, silicon oxynitride, silicon oxide or a high-K dielectric material, and the high-K dielectric material is HfO, ZrO, WN, Al2O3HfSiO, or any combination thereof, the gate electrode 402b may be polysilicon or metal. Thereafter, a sidewall forming process (including sidewall material deposition, etching, etc.) may be employed to form a sidewall 403 on the sidewall of the gate structure 402.
In step S1, before forming the gate structure 402, after forming the gate structure 402, or after forming the sidewalls 403, a drift region 404 and a well region 405 are formed by a corresponding photo mask process and an ion implantation process, specifically, a surface of the semiconductor substrate 400 at a side of forming the source region is protected by a layer of photoresist mask to expose a surface of the semiconductor substrate 400 at a side of forming the drain region, and then a lightly doped LDD ion implantation with higher energy is performed on the exposed surface of the semiconductor substrate 400 to form the lightly doped drift region 404, wherein the ions such as phosphorus and arsenic are implanted with an energy of 50keV to 300keV and a dose of 5e11cm-2-4e12cm-2And then removing the photoresist mask. The drift region 404 may be formedWithout any field oxygen isolation structures.
In step S1, before or after forming the drift region 404, a new photoresist mask is formed to expose the surface of the semiconductor substrate 400 where the well region is to be formed and protect other surfaces of the semiconductor substrate 400 including the surface of the drift region 404, and then a multi-step ion implantation process is performed to implant ions into the exposed surface of the semiconductor substrate 400 to form the well region 405. The specific process of forming the well region 405 by the multi-step ion implantation process includes: first, a first ion implantation is performed on the exposed surface of the semiconductor substrate 400 by a one-step high-dose, high-energy vertical ion implantation process, wherein the type of the implanted ions is opposite to the type of the doped ions of the drift region 404, so as to neutralize the inversion ions in the semiconductor substrate 400, wherein the implantation dose is, for example, 5e13 cm-2The implantation energy is, for example, 300keV, and when the well region 405 is a P-well, the ions of the first ion implantation are, for example, boron ions; next, a second ion implantation is performed on the exposed surface of the semiconductor substrate 400 by a one-step low-dose low-energy vertical ion implantation process, wherein the type of the implanted ions is opposite to the type of the doped ions of the drift region 404, and the implanted ions are used for adjusting the threshold voltage and forming a channel, wherein the implantation dose is, for example, 1e13 cm-2The implantation energy is, for example, 80keV, and when the well region 405 is a P-well, the ions of the second ion implantation are, for example, boron ions; then, a third ion implantation is performed on the exposed surface of the semiconductor substrate 400 by a low-energy, high-dose tilted ion implantation process, wherein the ion type of the implantation is opposite to the doping ion type of the drift region 404 for preventing punch-through, and the implantation dose is, for example, 2.5e13 cm-2The implantation energy is, for example, 30keV, and the angle (i.e., the inclination angle) between the implantation energy and the perpendicular line on the surface of the semiconductor substrate 300 is 30 degrees to 45 degrees, and when the well region 405 is a P-well, the ions implanted for the third time are, for example, boron ions. Finally, annealing treatment is carried out to enable doped ions in the drift region 404 and the well region 405 to be diffused in place, and at the moment, edges of the well region 405 and the drift region 404 are diffused for a certain distance towards the bottom of the gate structure 402, so that the formed well region 405And a drift region 404 laterally distributed in the semiconductor substrate 404 at a lateral distance, the gate structure 402 straddling the edges of said well region 405 and the edges of said drift region 404.
Referring to fig. 4B to 4E, in step S2 of the present embodiment, a specific process of forming a shielding insulating layer having a shielding trench with a wide top and a narrow bottom on the surfaces of the semiconductor substrate 400 and the gate structure 402 may include:
first, referring to fig. 4B, a deposition process or a thermal growth (thermal oxidation, thermal nitridation or thermal oxynitridation) process is employed to cover a first insulating layer 406 with a certain thickness at least on the surfaces of the drift region 404 and the well region 405, the thickness of the first insulating layer 406 depends on the performance requirement of the device, the thickness of the first insulating layer 406 is usually greater than or equal to the thickness of the gate dielectric layer 402a, and the material of the first insulating layer 406 is silicon oxide, silicon nitride or silicon oxynitride; the first insulating layer 406 is then etched, the well region 405 and the first insulating layer 406 on the surface of the drift region 404 for forming the drain region are removed, the first insulating layer 406 is used for protecting the surface of the drift region 404 when a shielding trench is formed subsequently, and is used as an etching stop layer to ensure the thickness of the shielding insulating layer at the bottom of the subsequent shielding trench. In an embodiment of the present invention, after the first insulating layer 406 is etched, source and drain ions are implanted into the semiconductor substrate 400 on both sides of the gate structure 402 by using the gate structure 402, the sidewall 403 and the first insulating layer 406 as masks, and the implanted ions are of the same type as the doped ions of the drift region 404, so as to form a source region 407 in the well region 405, form a drain region 408 in the drift region 404 on a side of the first insulating layer 406 away from the gate structure 402, and further form a body connecting region 409 in the well region 405, which is of a different doping type from the source region 407 and is farther away from the gate structure 402 than the source region 407 after the source region 407 is formed, where the body connecting region 409 and the source region 407 are laterally distributed in the well region 404 and separated by a second lateral distance. In another embodiment of the present invention, the source region 407, the drain region 408 and the body connection region 409 may also be formed by etching the shielding insulating layer to form a source contact hole and a drain contact hole, and then using the shielding insulating layer as a mask to the well region 405 at the bottom of the source contact holeAnd performing source and drain ion implantation on the surface and the surface of the drift region at the bottom of the drain contact hole to form the source region 407 and the drain region 408. In addition, in other embodiments of the present invention, before forming the source region 407 and the drain region 408, a patterned photomask may be formed to expose the surface of the well region 405 where the body region 409 is to be formed and protect the surface of the well region 405 where the source region 407 is formed and the surface of the drift region 404 where the drain region 408 is formed, and then the body connection region 409 may be formed in the well region 405 by implanting ions of the same doping type as that of the well region 405 into the surface of the well region 405 where the body region 409 is to be formed, which is exposed by the patterned photomask. In addition, when the LDMOS transistor to be formed is an N-type LDMOS transistor, the source-drain ions implanted in the source region 407 and the drain region 408 are N + ions, such as phosphorus or arsenic or antimony, with a dose larger than the dose of the ions doped in the well region 405 and the drift region 404, such as 1e14cm-2～1e16cm-2The implanted ions in the body region 409 are P + ions, such as boron or boron difluoride or indium or gallium, at a dose greater than the dose of the ions doped in the well region 405, such as 1e14 cm-2-1e16cm-2。
Next, with continued reference to fig. 4B, a top-planarized second insulating layer is formed on the surfaces of the well region 405 (including the body connection region 409 and the source region 407), the field oxide isolation structure 401, the sidewall 403, the gate structure 402, the first insulating layer 406, and the drift region 404 (including the drain region 408) by a deposition process and a chemical mechanical polishing process, where the second insulating layer is used to form a first trench on one hand, and also provides a planar process window for the formation of subsequent layers on the other hand. The second insulating layer may be a single-layer structure or a stacked-layer structure, and the stacked-layer structure includes, for example, a thinner dielectric insulating layer 410 and a thicker dielectric insulating layer 411 that are sequentially adjacent to the first insulating layer 406, wherein the thicker dielectric insulating layer 411 is deposited to a thickness sufficient to have a flat upper surface after being processed by a chemical mechanical planarization process, and the thinner dielectric insulating layer 410 has a higher etching selectivity with respect to both the first insulating layer 406 and the thicker dielectric insulating layer 411, and is made of, for example, silicon nitride or silicon oxynitride, or a combination thereofThe material of the insulating layer 406 and the thicker dielectric insulating layer 411 may be the same or different, and the material of the first insulating layer 406 and the thicker dielectric insulating layer 411 may be selected from silicon oxide, silicon nitride or silicon oxynitride, in an embodiment of the present invention, the first insulating layer 406 is, for example, a silicon oxide layer, and the second insulating layer is, for example, a silicon nitride layer (i.e., the thinner dielectric insulating layer 410) and a silicon oxide layer (i.e., the thicker dielectric insulating layer 411) sequentially stacked on the surface of the first insulating layer 406. Then, a patterned mask layer 414 with an opening is formed on the surface of the second insulating layer, where the patterned mask layer 414 may be a single-layer structure or a stacked-layer structure, and the material of the patterned mask layer 414 includes photoresist, the opening of the patterned mask layer 414 is located above the drift region 404 between the gate structure 402 and the drain region 408, the patterned mask layer 414 is used as a mask, the second insulating layer is etched by using a vertical etching process or an approximately vertical etching process, the etching is stopped at forming a first trench 413 exposing the surface of the first insulating layer 406, and the first trench 413 is a linear trench, that is, a sidewall of the first trench 413 is vertical or approximately vertical (that is, a bottom angle is close to 90 °, for example, 75 ° to 89 °). The vertical etching process or the approximately vertical etching process is a dry etching process, such as a plasma etching process. In one embodiment of the present invention, the etching gas used in the plasma etching process includes a fluorocarbon-containing gas (e.g., CF)4、CHF3、C2F6、C3F8Etc.), the accuracy of the formed first trench 413 is improved upon etching, and damage to the surface of the first insulating layer 406 exposed at the bottom of the first trench is reduced.
Then, referring to fig. 4C, an appropriate process (e.g., an ashing process, a chemical mechanical polishing process, or an etching process) may be selected according to a material of the patterned mask layer 414 to remove the patterned mask layer 414, and a sacrificial layer 414 is formed on the second insulating layer and the surface of the first trench 413 by a deposition process, a coating process, or the like, where the sacrificial layer 414 has a thickness required to fill the first trench 413, and the sacrificial layer 414 may be a single-layer structure or a stacked-layer structure, and the material thereof may include a silicon-containing anti-reflection layer (Si-ARC), Polyimide (PMMA), or organic glass (PI); then, a patterned photoresist layer 415 may be formed on the surface of the sacrificial layer 414 by a photolithography process, where the patterned photoresist layer 415 has an opening 416 misaligned with the first trench 413, the opening 416 is farther away from the gate structure 402 relative to the first trench 413, and a misalignment distance between the opening 416 and the gate structure 402 is D, that is, the patterns in the patterned photoresist layer 415 and the patterned mask layer 414 may be the same, but may be misaligned relatively, so that the patterned photoresist layer 415 and the patterned mask layer 414 may use the same mask, and the mask may be misaligned when the patterned photoresist layer 415 is formed.
Next, referring to fig. 4D, using the patterned photoresist layer 415 as a mask, etching the sacrificial layer 414 and the second insulating layer (including the dielectric insulating layer 410 and the dielectric insulating layer 411) by using an etching gas (heavy polymer gas) that is favorable for generating more polymers, that is, etching the sacrificial layer 414 and the shielding insulating layer in an upper region of a side of the first trench away from the gate structure to form an inverted cone-shaped trench, that is, a second trench 417 that is wide at the top and narrow at the bottom, where a sidewall of the second trench 417 close to the gate structure 402 is the sacrificial layer 414, a sidewall away from the gate structure 402 is the shielding insulating layer (that is, the first insulating layer 406, the dielectric insulating layer 410, and the dielectric insulating layer 411 are stacked in sequence), a bottom of the second trench 417 is lower than or equal to a bottom of the first trench 413, that is, a bottom of the second trench 417 exposes a surface of the first insulating layer 406, the etching gas may include C4F6And may also include O2。
Then, referring to fig. 4E, an oxygen ashing process may be used to remove the patterned photoresist layer 415, and a suitable process (e.g., wet etching, etc.) is used to remove the remaining sacrificial layer, thereby forming a shielding trench 418 with a wide top and a narrow bottom, where the shielding trench 418 is substantially formed by overlapping a first trench 413 and a second trench 417 and has a right trapezoid shape, a right angle of the right trapezoid shape is located at a side close to the gate structure 402, and an acute angle of the right trapezoid shape is 45 ° to 70 °.
It should be noted that the shape of the shielding trench 418 formed in step S2 according to another embodiment of the present invention is not limited to the right trapezoid with a wide top and a narrow bottom, but may also be a polygon with a wide top and a narrow bottom (see 209d in fig. 2E), for example, the shielding trench 418 formed in step S2 according to an embodiment of the present invention may be a polygon with a wide top and a narrow bottom and having right angles (see 209d in fig. 2E), a side of the polygon with a wide top and a narrow bottom and having right angles, which is close to the gate structure, is a right-angled side, a side far from the gate structure is a polygon side formed by sequentially connecting a plurality of line segments with gradually increasing slopes, a slope of a side with a largest slope among the polygons is less than or equal to tg70 °, and referring to fig. 4B to 4E, the process of forming the polygon with a wide top and a narrow bottom and having right angles includes: first, the first trench 413 is formed first, and then a plurality of tapered trenches with sequentially raised bottoms are formed, the forming process of each tapered trench includes sacrificial layer deposition, patterned photoresist dislocation mask, tapered etching of the sacrificial layer and the shielding insulating layer, and photoresist and sacrificial layer removal, and the specific forming process of each tapered trench may refer to the forming process of the tapered trench (i.e., the second trench 417), which is not described herein again. For another example, in step S2 of another embodiment of the present invention, the shielding trench 418 formed is a right-angled curved surface (as shown in 209B in fig. 2C) with a wide top and a narrow bottom, a bottom corner of a side of the right-angled curved surface close to the gate structure is a right angle, a bottom is a horizontal line segment, and an edge of a side far away from the gate structure is an arc line segment, please refer to fig. 4B to 4E and fig. 2C, and the forming process of the right-angled curved surface with the wide top and the narrow bottom includes: first trench 413 is formed, then a trench with an arc-shaped side wall is formed through steps of sacrificial layer deposition, patterning of a photoresist dislocation mask, circular etching or arc etching (to form an arc-shaped trench) of a sacrificial layer and a shielding insulating layer, the side wall of one side, close to a gate structure, of the trench is an arc-shaped sacrificial layer, the side wall of one side, far away from the gate structure, of the trench is an arc-shaped shielding insulating layer, then the photoresist and the sacrificial layer are removed, and a right-angled polygon with a wide upper part and a narrow lower part is obtained. For another example, the shielding trench formed in step S2 of the further embodiment of the present invention is shaped as a sector (e.g. 209c in fig. 2D), a side of the sector close to the gate structure is a vertical side, and a side formed from a bottom of the vertical side to a side of the trench top far from the gate structure is an arc segment, where the arc segment makes the shielding insulating layer at the bottom of the shielding trench thicker in a direction far from the gate structure.
Referring to fig. 4E, in step S3, the shielding insulating layer is etched by photolithography and etching processes, i.e., the dielectric insulating layer 410 and the dielectric insulating layer 411 above the source region 407, the drain region 408 and the body connecting region 409 are etched until the surfaces of the source region 407, the drain region 408 and the body connecting region 409 are exposed, so as to form source contact holes 420, drain contact holes 419 and body connecting region 421 contact holes, and the source contact holes 420 may expose the sidewall surfaces of the sidewalls 403. Note that, in other embodiments of the present invention, when the source region 407, the drain region 408, and the body connection region 409 have not been formed before step S3, the shielding insulating layer of the respective regions is etched in step S3 until the surfaces of the well region 405 for forming the body connection region 409 and the source region 408 and the surfaces of the drift region 404 for forming the drain region 408 are exposed to form the source contact hole 420, the drain contact hole 419, and the body connection region contact hole 421; furthermore, in some embodiments of the present invention, only the shielding dielectric layer above the source region 408 (or the well region used to form the source region 408) may be etched, and the etching stops at the surface of the source region 408 (or the well region 405), thereby forming the source contact hole 420.
In addition, when the source region 407, the drain region 408 and the body connection region 409 have not been formed before step S3, a patterned source/drain photoresist layer may be formed on the shielding insulating layer, the patterned source/drain photoresist layer protects the body connection region contact hole 421 and the well region 405 thereunder to expose the source contact hole 420 and the drain contact hole 419, source/drain ion implantation is performed on the semiconductor substrate 400 below the source contact hole 420 and the drain contact hole 419 using the patterned source/drain photoresist layer and the shielding insulating layer as masks to form the source region 407 in the well region 405 below the source contact hole 420, the drain region 408 is formed in the drift region 404 below the drain contact hole 419, the patterned source/drain photoresist layer is removed, and a patterned body photoresist layer is formed to protect the source contact hole 420 and the source region 407 therebelow, Drain contact hole 419 and drain region 408 thereunder exposing body contact region 421 and well region 405 thereunder; then, the well region 405 under the body connection region contact hole 421 is ion-implanted with the patterned body region photoresist layer and the shielding insulating layer as masks, thereby forming the body connection region 409 in the well region 405 under the body connection region contact hole 421.
Referring to fig. 4F, in step S4, first, a metal layer 422 is formed by covering at least one metal selected from Ti, Al, W, TiN, or TiW on the entire device surface including the source contact hole 420 by a sputtering deposition process, etc., i.e., the metal layer 422 is covered on the surface of the shielding insulating layer and the exposed semiconductor substrate 400 (including the exposed well region 405, the drift region 404, the drain region 407, the source region 408, and the body connection region 409); then, the excess metal layer may be etched away, and only the metal layer on the region from the source region 408 (the side away from the gate structure 402) to the shielding trench 418 (the side away from the gate structure 402) remains, or only the metal layer on the region from the source region 408 to the drain region 419 near one side edge of the gate structure 402 remains, that is, the remaining metal layer 422 covers the surfaces of the source region 407, the sidewall 403, and the shielding insulating layer, and the covering of the remaining metal layer 422 on the shielding insulating layer may be complete or partial, specifically, the end of the remaining metal layer 422 covering the surface of the shielding insulating layer may cover the side edge of the shielding trench 418 near the drain region 408, and may also cover the edge of the shielding insulating layer near the drain region 408. The remaining metal layer 422 crosses over the gate structure 402, and one end of the metal layer is in contact with the source region 407, and the other end of the metal layer is spaced from the drain region 408 by a certain distance, the thickness of the shielding insulating layer between the metal layer 422 and the gate structure 402 is different, the size of the coupling capacitance of the device is also different, the distance between the other end of the metal layer 422 and the drain region 408 is also different, and the electric field strength between the source region 407 and the drain region 408 of the device is also different, so that the thickness of the shielding insulating layer and the position of the shielding trench 418 therein can be adaptively changed according to different device performance requirements.
The manufacturing method of the semiconductor device can be compatible with the existing standard CMOS process, only needs to change the original rectangular groove into the shielding groove with narrow top and wide bottom, can reduce the electric field in the region between the grid and the drain region, enables the electric field to be more uniformly distributed, is beneficial to inhibiting the Hot Carrier Injection (HCI) effect at the edge of the grid structure, and can greatly improve the output resistance of the device, thereby realizing higher breakdown voltage and lower on resistance.
It will be apparent to those skilled in the art that various changes and modifications may be made in the invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (22)
1. An LDMOS transistor, comprising:
a semiconductor substrate;
the semiconductor device comprises a well region and a drift region which are different in doping type, wherein the well region and the drift region are transversely distributed in a semiconductor substrate and are separated by a first transverse distance, a source region is formed in the well region, and a drain region is formed in the drift region;
the gate structure is positioned on the surface of the semiconductor substrate and crosses the edge of the well region and the edge of the drift region, and the source region and the drain region are positioned on two sides of the gate structure;
the shielding insulation layer covers the top of the gate structure and extends to the partial surface of the drift region, the shielding insulation layer is exposed out of the drain region, a shielding groove with a wide upper part and a narrow lower part is formed in the shielding insulation layer between the drain region and the gate structure and covering the surface of the drift region, the shielding groove does not penetrate through the shielding insulation layer, one side, close to the gate structure, of the shielding groove is a vertical side wall, and the shape of the side wall, far away from the gate structure, of the shielding groove enables the opening size of the shielding groove to be gradually widened from bottom to top so as to increase the average thickness of the shielding insulation layer on the periphery of one side, far away from the gate structure, of the shielding groove;
and the metal layer covers the surfaces of the source region and the shielding insulating layer.
2. The LDMOS transistor set forth in claim 1 further including a body connection region of a different doping type than said source region, said body connection region and said source region being laterally distributed within said well region and separated by a second lateral distance.
3. The LDMOS transistor set forth in claim 2 wherein a field oxygen isolation structure is provided between said body connection region and said source region to separate said body connection region and said source region by a second lateral distance; and/or a field-free oxygen isolation structure is arranged between the drain region and the grid structure.
4. The LDMOS transistor set forth in claim 1 wherein said metal layer overlies one of an end of said shield insulator layer on a surface, an edge of said shield trench adjacent said drain region, and an edge of said shield insulator layer adjacent said drain region.
5. The LDMOS transistor set forth in claim 1 wherein said shield insulator layer is made of a material including at least one of silicon oxide, silicon nitride and silicon oxynitride.
6. The LDMOS transistor of claim 1, wherein the gate structure comprises a gate dielectric layer and a gate electrode layer stacked on the surface of the semiconductor substrate in sequence and a sidewall covering sidewalls of the gate dielectric layer and the gate electrode layer, and a thickness of the shielding insulating layer at the bottom of the shielding trench is greater than or equal to a thickness of the gate dielectric layer.
7. The LDMOS transistor of any one of claims 1-6, wherein the shielding trench has a shape of a right-angled trapezoid wide at the top and narrow at the bottom in a film layer stacking direction, and a right angle of the right-angled trapezoid is positioned at a side close to the gate structure; or the shielding groove is fan-shaped in the film layer overlapping direction; or, the shape of the shielding groove in the film layer superposition direction is a polygon with a right angle, one side of the polygon close to the gate structure is a right-angle side, and one side of the polygon far away from the gate structure is a continuous arc line segment or a multi-angle side formed by sequentially connecting a plurality of line segments with gradually increased slope.
8. The LDMOS transistor set forth in claim 7 wherein the acute angle of said right trapezoid is between 45 ° and 70 °.
9. A method of fabricating an LDMOS transistor, comprising the steps of:
providing a semiconductor substrate, wherein a well region and a drift region which are different in doping type are formed in the semiconductor substrate, the well region and the drift region are laterally distributed in the semiconductor substrate and are separated by a first lateral distance, and a gate structure crossing the edge of the well region and the edge of the drift region is formed on the surface of the semiconductor substrate;
forming a shielding insulating layer with a shielding groove which is wide at the top and narrow at the bottom on the surfaces of the semiconductor substrate and the gate structure, wherein the shielding groove does not penetrate through the shielding insulating layer, one side of the shielding groove close to the gate structure is a vertical side wall, and the side wall of the shielding groove far away from the gate structure enables the opening size of the shielding groove to be gradually widened from bottom to top so as to increase the average thickness of the shielding insulating layer at the periphery of one side of the shielding groove far away from the gate structure;
etching the shielding insulating layer to form a source contact hole at least exposing partial surface of the well region;
and forming a metal layer on the surfaces of the source contact hole and the rest of the shielding insulating layer.
10. The method of fabricating the LDMOS transistor set forth in claim 9 wherein the process of forming the shield insulator layer having the shield trench wide at the top and narrow at the bottom on the surface of said semiconductor substrate and gate structure comprises:
forming a shielding insulating layer with a first groove on the surfaces of the semiconductor substrate and the grid structure, wherein the shielding insulating layer with a certain thickness is reserved at the bottom of the first groove;
covering a sacrificial layer on the surface of the shielding insulating layer with the first groove, wherein the sacrificial layer is filled in the first groove;
etching the sacrificial layer and the shielding insulating layer in an upper area of one side of the first groove far away from the gate structure to form a second groove with a wide upper part and a narrow lower part, wherein the side wall of the second groove close to the gate structure is the sacrificial layer, the side wall far away from the gate structure is the shielding insulating layer, and the bottom of the second groove is lower than or equal to the bottom of the first groove;
and removing the sacrificial layer to form a shielding groove with a wide upper part and a narrow lower part on the shielding insulating layer.
11. The method of fabricating the LDMOS transistor set forth in claim 10 wherein the process of forming the shield insulator layer having the first trench on the surface of the semiconductor substrate and the gate structure comprises:
forming a first insulating layer on a partial surface of a drift region of the semiconductor substrate;
sequentially forming a second insulating layer with a flattened top and a patterned mask layer with an opening positioned above the first insulating layer on the surfaces of the semiconductor substrate, the gate structure and the first insulating layer;
and etching the second insulating layer by using the patterned mask layer as a mask through a vertical etching process or an approximately vertical etching process to form a first groove exposing the surface of the first insulating layer.
12. The method of manufacturing the LDMOS transistor set forth in claim 11, wherein the material of the patterned mask layer comprises a photoresist, the first insulating layer is a silicon oxide layer, and the second insulating layer is a silicon nitride layer and a silicon oxide layer sequentially stacked on a surface of the first insulating layer.
13. The method of fabricating an LDMOS transistor set forth in claim 11 wherein the etching gas of said vertical etching process or of an approximately vertical etching process comprises a fluorocarbon containing gas.
14. The method for manufacturing the LDMOS transistor set forth in claim 11, wherein after the first insulating layer is formed and before the second insulating layer is formed, source-drain ion implantation is performed on the semiconductor substrate on both sides of the gate structure with the gate structure and the first insulating layer as masks to form a source region in the well region and a drain region in the drift region on a side of the first insulating layer away from the gate structure; or etching the shielding insulating layer to form a source contact hole exposing part of the surface of the well region, and simultaneously forming a drain contact hole exposing part of the surface of the drift region, wherein the drain contact hole is positioned in the shielding insulating layer at one side of the shielding groove far away from the gate structure, and after the source contact hole and the drain contact hole are formed, performing source-drain ion injection on the semiconductor substrate at the bottoms of the source contact hole and the drain contact hole by taking the gate structure and the shielding insulating layer as masks to form a source region in the well region and form a drain region in the drift region.
15. The method of fabricating the LDMOS transistor set forth in claim 14 further comprising: after forming the source region, forming a body connection region in the well region, the body connection region being of a different doping type than the source region and being further away from the gate structure relative to the source region, the body connection region and the source region being laterally distributed within the well region and separated by a second lateral distance.
16. The method of fabricating an LDMOS transistor set forth in claim 15 wherein a field oxide isolation structure is provided between said body connection region and said source region to space said body connection region and said source region a second lateral distance; and/or a field-free oxygen isolation structure is arranged between the drain region and the grid structure.
17. The method for manufacturing the LDMOS transistor set forth in claim 9 wherein during the providing of the semiconductor substrate, a plurality of ion implantations are performed on the semiconductor substrate on a side of the gate structure away from the drift region to form the well region using a multi-step ion implantation process before or after the forming of the drift region.
18. The method of fabricating the LDMOS transistor set forth in claim 10 wherein etching the sacrificial layer and the shield insulator layer in the region above the side of the first trench remote from the gate structure to form a second trench that is wide at the top and narrow at the bottom comprises:
firstly, forming a patterned photoresist layer on the surface of the sacrificial layer, wherein the patterned photoresist layer is provided with an opening which is offset from the first groove, and the opening is farther away from the grid structure relative to the first groove;
and then, etching the sacrificial layer and the shielding insulating layer by taking the patterned photoresist layer as a mask to form a second groove with a wide upper part and a narrow lower part.
19. The method of fabricating the LDMOS transistor set forth in claim 18, wherein said sacrificial layer comprises an anti-reflection layer having a flat top surface.
20. The method for manufacturing an LDMOS transistor set forth in any one of claims 9 to 19, wherein said shield trench is shaped in a right trapezoid wide at the top and narrow at the bottom in the film layer stacking direction, the right angle of said right trapezoid being located at a side close to said gate structure; or the shielding groove is fan-shaped in the film layer overlapping direction; or, the shape of the shielding groove in the film layer superposition direction is a polygon with a right angle, one side of the polygon close to the gate structure is a right-angle side, and one side of the polygon far away from the gate structure is a continuous arc line segment or a multi-angle side formed by sequentially connecting a plurality of line segments with gradually increased slope.
21. The method of fabricating an LDMOS transistor set forth in claim 20 wherein said acute angle of said right trapezoid is between 45 ° and 70 °.
22. The method for manufacturing an LDMOS transistor set forth in any one of claims 14 to 16 wherein said metal layer covers one end of said shield insulating layer on the surface, on the edge of said shield trench near said drain region or on the edge of said shield insulating layer near said drain region.
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| CN101326643A (en) * | 2005-12-14 | 2008-12-17 | Nxp股份有限公司 | MOS transistor and a method of manufacturing an MOS transistor |
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| US20170207177A1 (en) * | 2016-01-18 | 2017-07-20 | Silanna Asia Pte Ltd. | Quasi-Lateral Diffusion Transistor with Diagonal Current Flow Direction |
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| CN101326643A (en) * | 2005-12-14 | 2008-12-17 | Nxp股份有限公司 | MOS transistor and a method of manufacturing an MOS transistor |
| CN101529589A (en) * | 2006-07-28 | 2009-09-09 | 万国半导体股份有限公司 | Bottom source ldmosfet structure and method |
| CN101414634A (en) * | 2008-12-01 | 2009-04-22 | 西安电子科技大学 | Heterojunction field effect transistor for groove insulated gate type multiple source field plate |
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