CN113903802A - Array strip-based enhancement type switch transistor and manufacturing method thereof - Google Patents
Array strip-based enhancement type switch transistor and manufacturing method thereof Download PDFInfo
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Abstract
The invention discloses an enhancement type switch transistor based on array strips and a manufacturing method thereof, which mainly solve the current collapse problem of the existing gallium nitride-based enhancement type switch transistor and comprise the following components from bottom to top: the light-emitting diode comprises a substrate (1), a transition layer (2) and a barrier layer (3), wherein a source electrode (6), a P-GaN gate (4), a modulation electrode (5) and a drain electrode (7) are sequentially arranged on the barrier layer (3) from left to right, and gate metal (8) is deposited on the upper part of the P-GaN gate (4); the modulation electrode (5) is composed of an array strip (51) at the lower part and a strip metal (52) at the upper part, the array strip (51) is composed of m isolation strips which are arranged in parallel at equal intervals, and the thickness of each isolation strip is smaller than or equal to that of the P-GaN gate (4); the strip of metal (52) is electrically connected to the drain electrode (7). The invention can effectively inhibit current collapse, has simple manufacturing process and can be used as a power switch device.
Description
Technical Field
The invention belongs to the technical field of microelectronics, and particularly relates to an enhancement type switch transistor based on an array strip, which can be used as a basic device of a power electronic system.
Technical Field
Currently, a power switch device with high performance and high reliability is vigorously researched and developed to remarkably improve the efficiency and the overall performance of a power electronic system, and the power switch device is one of effective ways for assisting in energy conservation and emission reduction and implementing green development strategies. Because the traditional silicon-based power switch device is limited by the silicon material, the performance of the traditional silicon-based power switch device approaches the theoretical limit, and the requirements of the next generation of power electronic systems on high temperature, high voltage, high frequency, high efficiency and high power density cannot be met. The GaN-based power switch device, in particular to a high electron mobility transistor based on a P-type cap layer GaN-based heterojunction structure, namely a GaN-based enhanced switch transistor, can realize the characteristics of lower on resistance, faster switching speed, higher breakdown voltage and the like by virtue of the characteristics of large forbidden bandwidth, high saturated electron drift speed, strong breakdown electric field, stable chemical property and the like of a GaN material, thereby remarkably improving the performance and reliability of a power electronic system. Therefore, the high-performance and high-reliability GaN-based enhanced switch transistor has very wide and special application prospect in the fields of national economy and military.
Conventional GaN-based enhancement mode switching transistors are based on GaN-based heterojunction structures, which include: the structure comprises a substrate 1, a transition layer 2, a barrier layer 3, a P-GaN gate 4, a source electrode 5, a drain electrode 6 and gate metal 7; a source electrode 5 is deposited on the left side of the upper portion of the barrier layer 3, a drain electrode 6 is deposited on the right side of the upper portion of the barrier layer 3, a P-GaN gate 4 is deposited on the middle portion of the upper portion of the barrier layer 3, and a gate metal 7 is deposited on the upper portion of the P-GaN gate 4, as shown in FIG. 1.
However, in the conventional GaN-based enhancement mode switching transistor, there are a lot of defects on the surface and in the body of the device, which easily cause the device to have a serious current collapse during the switching operation, and thus cause the device to have degraded reliability and output power characteristics, see Effects of hole tracks on the temperature dependence of current laminate in a normal-OFF gate-emission transistor, japan Journal of Applied Physics,55(5), 2016. In a conventional GaN-based enhancement mode switching transistor, a field plate technique is used to suppress current collapse during the switching operation of the device, as shown in Reducing dynamic on-resistance of p-GaN gate electromagnetic field plate configurations,2020 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), pp.1-4,2020. However, the manufacturing process of the GaN-based enhancement type switch transistor adopting the field plate technology is complicated, the manufacturing yield of the device is low, and the manufacturing cost is high. In addition, the adoption of the field plate technology can increase the parasitic capacitance of the device, thereby attenuating the frequency characteristic of the device. Therefore, it is very necessary and urgent to develop a high-performance GaN-based enhancement mode switching transistor with a simple process and a strong ability to suppress current collapse.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide an enhancement-mode switch transistor based on array strips and a method for fabricating the same, so as to effectively suppress the current collapse phenomenon and significantly improve the reliability and power characteristics of the device.
In order to achieve the purpose, the technical scheme of the invention is realized as follows:
1. an array stripe based enhancement mode switching transistor comprising from bottom to top: substrate 1, transition layer 2 and barrier layer 3, barrier layer 3 upper portion is equipped with P-GaN gate 4, and the upper portion deposit of P-GaN gate 4 has grid metal 8, and the upper portion left and right side edge of barrier layer 3 is equipped with source electrode 6 and drain electrode 7 respectively, its characterized in that:
a modulation electrode 5 is arranged on the barrier layer 3 between the P-GaN gate 4 and the drain electrode 7, and the modulation electrode 5 consists of an array strip 51 at the lower part and a strip metal 52 at the upper part;
the array strip 51 is composed of m spacer strips with equal spacing, the m spacer strips are horizontally arranged on the barrier layer 3 and are arranged in parallel, and the m spacer strips are adjacent to each otherThe distance w between the two isolating bars is 0.5-1000 μm, and the doping concentration of each isolating bar is 5 multiplied by 1015～1×1022cm-3The thickness c of each isolating strip is equal and less than or equal to the thickness b of the P-GaN gate 4, when c is less than or equal to 5nm, each isolating strip has almost no depletion effect on two-dimensional electron gas in a channel formed between the lower barrier layer 3 and the transition layer 2 of the device in a balanced state, and when c is less than or equal to 5nm>When the thickness of the isolating bars is 5nm, the depletion effect of each isolating bar on two-dimensional electron gas in a channel formed between the lower barrier layer 3 and the transition layer 2 of the device in a balanced state can be gradually increased along with the increase of the thickness c of the isolating bar, and the distance between the 1 st isolating bar and the upper boundary of the device and the distance between the mth isolating bar and the lower boundary of the device are both u; wherein m is a positive integer, and u is a number when m is 1>0μm，m>U is more than or equal to 0 mu m at 1.
The strip metal 52 is electrically connected to the drain 7.
Further, the substrate 1 may be made of sapphire, silicon carbide, silicon, graphene, or other materials.
Further, the thickness a of the barrier layer 3 is 1 to 25 nm.
Further, the thickness b of the P-GaN gate 4 is 5-400 nm, and the doping concentration is 5 multiplied by 1015～1×1022cm-3。
Further, the horizontal distance d between the right end of the array strip 51 and the left end of the drain 7 is more than or equal to 0 μm.
Furthermore, the metal at the bottom layer of the drain electrode 7 is a metal close to the work function of the barrier layer 3, so that good ohmic contact between the drain electrode 7 and the barrier layer 3 is ensured.
2. The method for manufacturing the enhanced switch transistor based on the array strip gives the following two preparation schemes:
preparation scheme 1: a method of fabricating an array stripe based enhancement mode switch transistor, comprising:
A) extending a GaN-based wide bandgap semiconductor material on a substrate 1 to form a transition layer 2 with the thickness of 0.5-50 mu m;
B) extending a GaN-based wide bandgap semiconductor material on the transition layer 2to form a barrier layer 3 with the thickness a of 1-25 nm;
C) a P-type GaN semiconductor material is epitaxially formed on the barrier layer 3 to have a thickness b of 5to 400nm and a doping concentration of 5 × 1015～1×1022cm-3The P-type GaN layer of (1);
D) manufacturing a mask on the P-type GaN layer for the first time, etching the P-type GaN layer by using the mask until the upper surface of the barrier layer 3 is etched to form 1P-GaN gate 4 with the thickness of b on the left side and m P-GaN blocks which are arranged in parallel and have equal intervals and the thickness of b on the right side, wherein the interval w between every two adjacent P-GaN blocks is 0.5-1000 microns;
E) manufacturing a mask on the barrier layer 3, the P-GaN gate 4 and the m P-GaN blocks for the second time, etching the P-GaN blocks by using the mask, wherein the etching depth f is greater than or equal to 0 mu m and less than the thickness of the P-GaN gate 4, forming m equally-spaced isolation bars with the right side thickness of c, namely f + c-b, and when c is less than or equal to 5nm, the device has almost no depletion effect on the two-dimensional electron gas in the channel formed between the lower barrier layer 3 and the transition layer 2 under the balanced state, and when c is greater than 5nm, the depletion effect of the device on the two-dimensional electron gas in the channel formed between the lower barrier layer 3 and the transition layer 2 under the balanced state can gradually increase along with the increase of the thickness c of the isolation bars; the distance between the 1 st isolating bar and the upper boundary of the device is equal to the distance between the mth isolating bar and the lower boundary of the device, namely u, and the m isolating bars form an array bar 51, wherein m is a positive integer and u is greater than 0 μm when m is 1 and is greater than or equal to 0 μm when m is 1;
F) manufacturing masks on the barrier layer 3, the P-GaN gate 4 and the array strip 51 for the third time, depositing metal on the upper parts of the barrier layer 3 on the left side and the right side by using the masks, and performing rapid thermal annealing to finish the manufacture of the source electrode 6 and the drain electrode 7, wherein the horizontal distance d between the left end of the drain electrode 7 and the right end of the array strip 51 is more than or equal to 0 mu m;
G) making a mask on the barrier layer 3, the P-GaN gate 4, the array strip 51, the source electrode 6 and the drain electrode 7 for the fourth time, and depositing metal on the upper part of the P-GaN gate 4 by using the mask to finish the making of gate metal 8;
H) and manufacturing a mask on the barrier layer 3, the P-GaN gate 4, the array strips 51, the source electrode 6, the drain electrode 7 and the gate metal 8 for the fifth time, depositing metal on the upper part of each isolation strip in the array strips 51 by using the mask to form strip metal 52, and electrically connecting the strip metal 52 with the drain electrode 7 to finish the manufacturing of the whole device.
Preparation scheme 2: a method of fabricating an array stripe based enhancement mode switch transistor, comprising:
1) extending a GaN-based wide bandgap semiconductor material on a substrate 1 to form a transition layer 2 with the thickness of 0.5-50 mu m;
2) extending a GaN-based wide bandgap semiconductor material on the transition layer 2to form a barrier layer 3 with the thickness a of 1-25 nm;
3) a P-type GaN semiconductor material is epitaxially formed on the barrier layer 3 to have a thickness b of 5to 400nm and a doping concentration of 5 × 1015～1×1022cm-3The P-type GaN layer of (1);
4) manufacturing a mask on the P-type GaN layer for the first time, etching the P-type GaN layer by using the mask, wherein the etching depth f is greater than or equal to 0 mu m and smaller than the thickness b of the P-type GaN layer, and forming a P-GaN block on the left side;
5) making a mask on the P-GaN block and the P-type GaN layer for the second time, etching the etched P-type GaN layer in the step 4) again by using the mask until the upper surface of the barrier layer 3 is etched, forming 1P-GaN gate 4 with the thickness of b on the left side and m equally spaced isolating bars with the thickness of c on the right side, namely f + c-b, wherein when c is less than or equal to 5nm, each isolating bar of the device has almost no depletion effect on the two-dimensional electron gas in the channel formed between the lower barrier layer 3 and the transition layer 2 of the device in a balanced state, and when c is greater than 5nm, the depletion effect of each isolating bar on the two-dimensional electron gas in the channel formed between the lower barrier layer 3 and the transition layer 2 of the device in the balanced state gradually increases along with the increase of the thickness c of the isolating bar; the distance w between two adjacent isolating bars is 0.5-1000 μm, the distance between the 1 st isolating bar and the upper boundary of the device is equal to the distance between the mth isolating bar and the lower boundary of the device, namely u, the m isolating bars jointly form an array bar 51, wherein m is a positive integer, u is greater than 0 μm when m is 1, and u is greater than or equal to 0 μm when m is 1;
6) manufacturing masks on the barrier layer 3, the P-GaN gate 4 and the array strip 51 for the third time, depositing metal on the upper parts of the barrier layer 3 on the left side and the right side by using the masks, and performing rapid thermal annealing to finish the manufacture of the source electrode 6 and the drain electrode 7, wherein the horizontal distance d between the left end of the drain electrode 7 and the right end of the array strip 51 is more than or equal to 0 mu m;
7) making a mask on the barrier layer 3, the P-GaN gate 4, the array strip 51, the source electrode 6 and the drain electrode 7 for the fourth time, and depositing metal on the upper part of the P-GaN gate 4 by using the mask to finish the making of gate metal 8;
8) and manufacturing a mask on the barrier layer 3, the P-GaN gate 4, the array strips 51, the source electrode 6, the drain electrode 7 and the gate metal 8 for the fifth time, depositing metal on the upper part of each isolation strip in the array strips 51 by using the mask to form strip metal 52, and electrically connecting the strip metal 52 with the drain electrode 7 to finish the manufacture of the whole device.
Compared with the traditional GaN-based enhanced switch transistor, the device has the following advantages:
firstly, the device adopts the modulation electrode 5 electrically connected with the drain electrode, so that the charge and discharge of defects on the surface and in the body of the device can be effectively inhibited by modulating the p-n junction formed by the modulation electrode and the barrier layer when the device switch works, and the current collapse phenomenon is inhibited; meanwhile, the array strips 51 and the P-GaN gate 4 are made of the same layer of P-type GaN layer material, so that the manufacturing process is simplified.
Second, the modulation electrode 5 used in the device of the present invention is formed of m spacer bars and the upper bar metal thereof, and has a good frequency characteristic because parasitic capacitance of the device is hardly increased while ensuring good output characteristics of the device, as compared with other methods such as a field plate structure.
Simulation results show that the device has good reliability and output power characteristics, the manufacturing yield of the device can be improved, and the manufacturing cost of the device can be reduced.
Drawings
FIG. 1 is a block diagram of a conventional GaN-based enhancement mode switching transistor;
FIG. 2 is a block diagram of an array stripe based enhancement mode switching transistor of the present invention;
FIG. 3 is a three-dimensional perspective view of an array bar based enhancement mode switching transistor of the present invention;
FIG. 4 is a top view of an array stripe based enhancement mode switching transistor of the present invention;
FIG. 5 is a flow chart of an implementation of scheme 1 of the present invention for fabricating an array stripe based enhancement mode switch transistor;
FIG. 6 is a flow chart of an implementation of the present invention for making array stripe based enhancement mode switch transistor scheme 2;
fig. 7 is a graph showing current collapse characteristics obtained by simulation of a conventional device and a device according to the present invention.
Detailed Description
The embodiments and effects will be described in further detail below with reference to the accompanying drawings.
Referring to fig. 2, 3 and 4, the array stripe-based enhancement type switching transistor of the present example includes: the structure comprises a substrate 1, a transition layer 2, a barrier layer 3, a P-GaN gate 4, a modulation electrode 5, a source electrode 6, a drain electrode 7 and gate metal 8. Wherein:
the substrate 1 is made of sapphire, silicon carbide, silicon, graphene or other materials;
the transition layer 2 is positioned on the upper part of the substrate 1 and is composed of a plurality of layers of same or different GaN-based wide bandgap semiconductor materials, and the thickness of the transition layer is 0.5-50 mu m;
the barrier layer 3 is positioned on the upper part of the transition layer 2 and is composed of a plurality of layers of same or different GaN-based wide bandgap semiconductor materials, and the thickness of the barrier layer is 1-25 nm;
the P-GaN gate 4 is arranged on the barrier layer 3, has a thickness b of 5-400 nm and a doping concentration of 5 × 1015～1×1022cm-3；
The modulation electrode 5 is composed of an array strip 51 and a strip metal 52, the array strip 51 is positioned at the right side of the P-GaN gate 4 and at the upper part of the barrier layer 3 and is composed of m isolation strips with equal intervals, the m isolation strips are horizontally arranged on the barrier layer 3 and are arranged in parallel, the interval w between every two adjacent isolation strips is 0.5-1000 mu m, and the doping concentration of each isolation strip is 5 multiplied by 1015～1×1022cm-3The thickness c of each isolating strip is equal and less than or equal to the thickness b of the P-GaN gate 4, when c is less than or equal to 5nm, each isolating strip has almost no depletion effect on two-dimensional electron gas in a channel formed between the lower barrier layer 3 and the transition layer 2 of the device in a balanced state, and when c is less than or equal to 5nm>Device at 5nm is in equilibriumIn the state, the depletion effect of each isolating strip on the two-dimensional electron gas in a channel formed between the lower barrier layer 3 and the transition layer 2 of each isolating strip is gradually increased along with the increase of the thickness c of the isolating strip, and the distance between the 1 st isolating strip and the upper boundary of the device is equal to the distance between the mth isolating strip and the lower boundary of the device and is equal to u; wherein m is a positive integer, and u is a number when m is 1>0μm，m>U is more than or equal to 0 mu m at 1 hour; the strip metal 52 is located on top of the array strip 51;
the source electrode 6 and the drain electrode 7 are respectively positioned on the left side of the P-GaN gate 4 and the right side of the array strip 51, and are both positioned on the upper part of the barrier layer 3, the metal at the bottommost layer adopts Al, Ti, Ta or other metals capable of forming ohmic contact with the barrier layer 3, and the drain electrode 7 is electrically connected with the strip metal 52.
The gate metal 8 is positioned on the upper part of the P-GaN gate 4, and the width of the gate metal is smaller than that of the P-GaN gate 4.
Referring to fig. 5, scheme 1 of the present invention for preparing an array stripe-based enhancement type switching transistor gives the following three examples.
The first embodiment is as follows: the barrier layer 3 is made on the sapphire substrate with the thickness of 1nm, the array strip 51 contains 2 isolating strips, the thickness of each isolating strip is 1nm, the doping concentration is 5 multiplied by 1015cm-3The distance w between two adjacent spacers is 0.5 μm, the distance u between the 1 st spacer and the upper boundary of the device and the distance u between the 2 nd spacer and the lower boundary of the device are both 0 μm, and the horizontal distance d between the right end of the array bar 51 and the left end of the drain 7 is 0 μm.
A GaN material with the thickness of 30nm is epitaxially grown on a sapphire substrate 1 by using a metal organic chemical vapor deposition technology, and the process conditions of the metal organic chemical vapor deposition are as follows: the temperature is 500 ℃, the pressure is 46Torr, the hydrogen flow is 4300sccm, the ammonia flow is 4300sccm, and the gallium source flow is 21 mu mol/min;
1b) GaN material with the thickness of 0.47 mu m is epitaxially grown on the GaN material by using the metal organic chemical vapor deposition technology to form the undoped transition layer 2, wherein the process conditions of the metal organic chemical vapor deposition are as follows: the temperature was 960 deg.C, the pressure was 45Torr, the hydrogen flow was 4400sccm, the ammonia flow was 4400sccm, and the gallium source flow was 120. mu. mol/min.
Depositing undoped Al with a thickness of 1nm and an aluminum composition of 0.3 on the GaN transition layer 2 by using a metal organic chemical vapor deposition technique0.3Ga0.7The N barrier layer 3 has the following metal organic chemical vapor deposition process conditions: the temperature is 990 ℃, the pressure is 44Torr, the hydrogen flow is 4400sccm, the ammonia flow is 4400sccm, the gallium source flow is 35 mu mol/min, and the aluminum source flow is 7 mu mol/min.
And 3, manufacturing a P-GaN gate 4 on the barrier layer 3.
3a) Epitaxial thickness of 5nm and doping concentration of 5 × 10 on the barrier layer 3 by using metal organic chemical vapor deposition15cm-3Forming a P-type GaN layer.
The process conditions for epitaxy by adopting metal organic chemical vapor deposition are as follows: the temperature is 950 ℃, the pressure is 40Torr, the hydrogen flow is 4000sccm, a high-purity Mg source is used as a doping agent, the ammonia flow is 4000sccm, and the gallium source flow is 100 mu mol/min;
3b) manufacturing a mask on the P-type GaN layer for the first time, etching the P-type GaN layer by using a reactive ion etching technology by using the mask until the upper surface of the barrier layer 3 is etched to form 1 left P- GaN gate 4 and 2 right P-GaN blocks, wherein the distance w between the 2P-GaN blocks is 0.5 mu m, and the thicknesses of the P-GaN gate 4 and the 2P-GaN blocks are both 5 nm;
the etching adopts the following process conditions: cl2The flow rate is 15sccm, the pressure is 10mTorr, and the power is 100W.
And 4, manufacturing an array strip 51 on the barrier layer 3.
Making a mask on the barrier layer 3, the P-GaN gate 4 and the 2P-GaN blocks for the second time, etching the 2P-GaN blocks by using the mask and using a reactive ion etching technology, wherein the etching depth f is 4nm, forming 2 isolating strips with the thickness c of 1nm, the distance between the 1 st isolating strip and the upper boundary of the device is equal to the distance between the 2 nd isolating strip and the lower boundary of the device is equal to 0 mu m, and the 2 isolating strips form an array strip 51;
the etching adopts the following process conditions: cl2The flow rate is 18sccm, the pressure is 14mTorr, and the power is 120W.
And 5, manufacturing a source electrode 6 and a drain electrode 7 on the barrier layer 3.
Making a mask on the barrier layer 3, the P-GaN gate 4 and the array strips 51 for the third time, depositing a plurality of layers of metals on the upper parts of the barrier layers 3 at the left and right sides by using an electron beam evaporation technology, wherein the plurality of layers of metals are respectively Ti/Al/Au from bottom to top, the thicknesses of the metals are respectively 0.018 mu m/0.045 mu m/0.052 mu m, and the N is arranged on the array strips2Performing rapid thermal annealing in the atmosphere to complete the manufacture of the source electrode 6 and the drain electrode 7, wherein the horizontal distance d between the left end of the drain electrode 7 and the right end of the array strip 51 is 0 μm;
the technological conditions of the electron beam evaporation technology are as follows: vacuum degree less than 1.8X 10-3Pa, power of 500W, evaporation rate of less than
The process conditions adopted by the rapid thermal annealing are as follows: the temperature was 870 ℃ for 35 s.
And 6, manufacturing gate metal 8 on the P-GaN gate 4.
Making a mask on the barrier layer 3, the P-GaN gate 4, the array strip 51, the source electrode 6 and the drain electrode 7 for the fourth time, and depositing a W/Au metal combination on the upper part of the P-GaN gate 4 by utilizing the mask by adopting an electron beam evaporation technology, namely, the lower layer is W, the upper layer is Au, the thicknesses of the W/Au metal combination and the Au metal combination are respectively 0.045 mu m/0.20 mu m, so as to finish the making of the gate metal 8;
the process conditions adopted for depositing the metal are as follows: vacuum degree less than 1.8X 10-3Pa, power of 200W, evaporation rate of less than
Setting the vacuum degree to be less than 1.8 multiplied by 10-3Pa, power of 500W, evaporation rate of less than
The process conditions of (1) manufacturing a mask on the barrier layer 3, the P-GaN gate 4, the array strip 51, the source electrode 6, the drain electrode 7 and the gate metal 8 for the fifth time, depositing a plurality of layers of metals on the upper parts of 2 isolating strips in the array strip 51 by using the mask and adopting an electron beam evaporation technology, wherein the plurality of layers of metals are the combination of Ni, Pt and Au, namely the Ni, Pt and Au respectively from bottom to top, the thicknesses of the Ni, Pt and Au are 0.012 mu m/0.053 mu m/0.035 mu m, forming strip metal 52, and electrically connecting the strip metal 52 with the drain electrode 7 to finish the manufacture of the whole device.
Example two: the barrier layer 3 is made on the silicon substrate with the thickness of 25nm, the array strip 51 contains 1 isolating strip with the thickness of 5nm and the doping concentration of 1 multiplied by 1022cm-3The distance u between the spacer and the upper boundary of the device and the distance u between the spacer and the lower boundary of the device are both 1 μm, and the horizontal distance d between the right end of the array bar 51 and the left end of the drain 7 is 2 μm.
Step one, a transition layer 2 is made by extending AlN and GaN materials on a silicon substrate 1 from bottom to top.
1.1) carrying out epitaxy on an AlN material with the thickness of 300nm on a silicon substrate 1 by using a metal organic chemical vapor deposition technology under the process conditions that the temperature is 820 ℃, the pressure is 42Torr, the hydrogen flow is 4300sccm, the ammonia flow is 4300sccm and the aluminum source flow is 21 mu mol/min;
1.2) using metal organic chemical vapor deposition technology to epitaxially grow a GaN material with the thickness of 19.7 μm on the AlN material under the process conditions that the temperature is 970 ℃, the pressure is 44Torr, the hydrogen flow is 4400sccm, the ammonia flow is 4400sccm and the gallium source flow is 110 μmol/min, so as to form the transition layer 2.
Depositing undoped Al on the undoped GaN transition layer 20.2Ga0.8N forms the barrier layer 3.
Depositing a GaN transition layer 2 with a thickness of 25nm by using a metal organic chemical vapor deposition technology under the process conditions of 990 ℃ of temperature, 44Torr of pressure, 4400sccm of hydrogen flow, 4400sccm of ammonia flow, 35 mu mol/min of gallium source flow and 7 mu mol/min of aluminum source flowUndoped Al having an aluminum component of 0.20.2Ga0.8An N barrier layer 3.
And step three, manufacturing a P-GaN gate 4 on the barrier layer 3.
3.1) Using molecular Beam epitaxy technique at 1.0X 10-10mbar, radio frequency power of 440W, and N as reactant2Under the process condition of high-purity Ga source, the epitaxial thickness on the barrier layer 3 is 400nm, and the doping concentration is 1 multiplied by 1022cm-3Forming a P-type GaN layer;
3.2) making a mask on the P-type GaN layer for the first time, and using the mask to perform reactive ion etching on Cl2And etching the P-type GaN layer until the upper surface of the barrier layer 3 under the process conditions of 15sccm of flow, 10mTorr of pressure and 100W of power to form 1 left P- GaN gate 4 and 1 right P-GaN block, wherein the thicknesses of the P-GaN gate 4 and the P-GaN block are both 400 nm.
And step four, manufacturing the array strips 51 on the barrier layer 3.
Making a mask on the barrier layer 3, the P-GaN gate 4 and the right P-GaN block for the second time, and using the mask to perform reactive ion etching on Cl2Etching the P-GaN block under the process conditions of the flow of 18sccm, the pressure of 14mTorr and the power of 120W, wherein the etching depth f is 395nm, forming a barrier rib with the thickness c of 5nm, and the distance between the barrier rib and the upper boundary of the device and the distance between the barrier rib and the lower boundary of the device are equal to 1 μm, and the barrier rib is the array rib 51.
And step five, manufacturing a source electrode 6 and a drain electrode 7 on the barrier layer 3.
Making mask on the barrier layer 3, P-GaN gate 4 and array strip 51 for the third time, and using the mask to evaporate electron beam on the upper parts of the barrier layers 3 at the left and right sides under vacuum degree of less than 1.8 × 10-3Pa, power of 500W, evaporation rate of less than
Under the process conditions of (1), depositing a plurality of layers of metals, from bottom to top, of Ta, Pt and Au, respectively, having a thickness of 0.122 μm/0.317 μm/0.161 μm, and N at a temperature of 870 ℃2In the atmosphereAnd performing rapid thermal annealing for 35s to complete the manufacture of the source electrode 6 and the drain electrode 7, wherein the horizontal distance d between the left end of the drain electrode 7 and the right end of the array strip 51 is 2 μm.
And step six, manufacturing gate metal 8 on the P-GaN gate 4.
Making a mask on the barrier layer 3, the P-GaN gate 4, the array strip 51, the source electrode 6 and the drain electrode 7 for the fourth time, and using the mask to adopt the electron beam evaporation technology to ensure that the vacuum degree is 1.7 multiplied by 10-3Pa, power 900W, evaporation rate
Under the process conditions of (1), a Ti/Au metal combination is deposited on the upper part of the P-GaN gate 4, namely the lower layer is Ti and the upper layer is Au, the thicknesses of the Ti/Au metal combination and the Au metal combination are respectively 0.25 mu m/0.30 mu m, and the manufacturing of the gate metal 8 is completed.
And step seven, manufacturing strip metal 52 on the array strip 51.
Making a mask on the barrier layer 3, the P-GaN gate 4, the array strips 51, the source electrode 6, the drain electrode 7 and the gate metal 8 for the fifth time, and using the mask to adopt the electron beam evaporation technology to ensure that the vacuum degree is less than 1.8 multiplied by 10-3Pa, power of 530W, evaporation rate of less than
Under the process conditions of (1), depositing a plurality of layers of metals on the upper part of the array strip 51, wherein the plurality of layers of metals are Al/Ti/Au metal combinations, namely Al, Ti and Au from bottom to top respectively, and the thicknesses of the metals are 0.211 mu m/0.528 mu m/0.261 mu m to form strip metal 52; and electrically connecting the strip of metal 52 to the drain 7, completing the fabrication of the entire device.
Example three: the barrier layer 3 is made on the silicon carbide substrate with the thickness of 20nm, the array strip 51 comprises four isolating strips, the thickness of each isolating strip is 100nm, the doping concentration is 1 multiplied by 1018cm-3The distance w between two adjacent spacers is 1000 μm, the distance between the 1 st spacer and the upper boundary of the device and the distance u between the fourth spacer and the lower boundary of the device are both 150 μm, and the horizontal distance d between the right end of the array bar 51 and the left end of the drain 7 is 3 μm.
And step A, epitaxially growing AlN and GaN materials on the silicon carbide substrate 1 from bottom to top to form a transition layer 2.
A1) Setting the process conditions of 1050 ℃ of temperature, 46Torr of pressure, 4600sccm of hydrogen flow, 4600sccm of ammonia flow and 6 mu mol/min of aluminum source flow, and extending an AlN material with the thickness of 90nm on the silicon carbide substrate 1 by using a metal organic chemical vapor deposition technology;
A2) setting the process conditions of 1050 ℃ of temperature, 46Torr of pressure, 4600sccm of hydrogen flow, 4600sccm of ammonia flow and 100 mu mol/min of gallium source flow, and forming the transition layer 2 by using a metal organic chemical vapor deposition technology to epitaxially grow a GaN material with the thickness of 29.01 mu m on the AlN material.
Step B-depositing undoped Al on the undoped GaN transition layer 20.1Ga0.9N forms the barrier layer 3.
Setting the technological conditions of 970 deg.C, 46Torr of pressure, 4500sccm of hydrogen flow, 4500sccm of ammonia flow, 37 mu mol/min of gallium source flow and 7 mu mol/min of aluminum source flow, and depositing undoped Al with the thickness of 20nm and the aluminum component of 0.1 on the GaN transition layer 2 by metal organic chemical vapor deposition0.1Ga0.9An N barrier layer 3.
And C, manufacturing the P-GaN gate 4 and the array strips 51 on the barrier layer 3.
C1) Setting the epitaxial process conditions of 950 ℃, 40Torr of pressure, 4000sccm of hydrogen flow, 4000sccm of high-purity Mg source as dopant, 4000sccm of ammonia flow and 100 micromol/min of gallium source flow, and using the metal organic chemical vapor deposition technology to epitaxially form a barrier layer 3 with the thickness of 100nm and the doping concentration of 1 × 1018cm-3Forming a P-type GaN layer;
C2) setting up Cl2Manufacturing a mask on the P-type GaN layer for the first time under the etching process conditions of 15sccm flow, 11mTorr pressure and 120W power, etching the P-type GaN layer by utilizing the mask and using a reactive ion etching technology until the upper surface of the barrier layer 3 to form a left P-GaN gate 4 and four right isospaced isolation strips, wherein the thicknesses of the P-GaN gate 4 and the four isolation strips are both 100nm, and the distance W between every two adjacent isolation strips is1000 μm, the first spacer is spaced from the upper boundary of the device by a distance equal to 150 μm from the lower boundary of the device by a fourth spacer, the four spacers forming the array stripe 51.
And D, manufacturing a source electrode 6 and a drain electrode 7 on the barrier layer 3.
Making mask on the barrier layer 3, P-GaN gate 4 and array strip 51 for the second time, and setting vacuum degree less than 1.8 × 10- 3Pa, power of 400W, evaporation rate of less than
Using electron beam evaporation technique to deposit multiple layers of metals on the left and right sides of barrier layer 3, wherein the multiple layers of metals are Al/Ni/Au from bottom to top, the thicknesses of the metals are 0.132 μm/0.061 μm/0.058 μm, and the metal is in N2And performing rapid thermal annealing at 840 ℃ for 35s in an atmosphere to form the source electrode 6 and the drain electrode 7, wherein the horizontal distance d between the left end of the drain electrode 7 and the right end of the array strip 51 is 3 mu m.
And E, manufacturing gate metal 8 on the P-GaN gate 4.
Making mask on the barrier layer 3, P-GaN gate 4, array strip 51, source electrode 6 and drain electrode 7 for the third time, and setting vacuum degree less than 1.8 × 10-3Pa, power 570W, evaporation rate
The process conditions of (1) and (2) are that the mask is utilized to deposit a Pt/Au metal combination on the upper part of the P-GaN gate 4 by adopting an electron beam evaporation technology, namely the lower layer is Pt, the upper layer is Au, and the thicknesses of the Pt/Au metal combination are respectively 0.021 mu m/0.35 mu m, so that the gate metal 8 is manufactured.
Step f. a strip metal 52 is fabricated on the array strip 51.
Making a mask on the barrier layer 3, the P-GaN gate 4, the array strip 51, the source electrode 6, the drain electrode 7 and the gate metal 8 for the fourth time, and setting the vacuum degree to be 1.7 multiplied by 10-3Pa, power 530W, evaporation rate
Using the mask on four spacers in the array stripe 51Partially depositing Ti/Mo/Au multilayer metal, namely Ti, Mo and Au from bottom to top, wherein the thickness of the Ti/Mo/Au multilayer metal is 0.136 mu m/0.198 mu m/0.126 mu m, and forming strip metal 52; and electrically connecting the bar metal 52 with the drain electrode 7, completing the fabrication of the entire device.
Referring to fig. 6, scheme 2 of the present invention for preparing an array stripe-based enhancement type switching transistor gives the following three examples.
Example four: the barrier layer 3 is made on the sapphire substrate with the thickness of 20nm, the array strip 51 contains 5 isolating strips, the thickness of each isolating strip is 50nm, the doping concentration is 1 multiplied by 1019cm-3The distance w between two adjacent spacers is 1000 μm, the distance u between the 1 st spacer and the upper boundary of the device and the distance u between the 5 th spacer and the lower boundary of the device are both 100 μm, and the horizontal distance d between the right end of the array bar 51 and the left end of the drain 7 is 2 μm.
The specific implementation of this step is the same as step 1 of the first embodiment.
Depositing undoped Al with a thickness of 20nm and an aluminum composition of 0.3 on the GaN transition layer 2 by using a MOCVD technique0.3Ga0.7The N barrier layer 3 has the following metal organic chemical vapor deposition process conditions: the temperature was 970 deg.C, the pressure was 46Torr, the hydrogen flow was 4500sccm, the ammonia flow was 4500sccm, the gallium source flow was 37. mu. mol/min, and the aluminum source flow was 8. mu. mol/min.
And 3, manufacturing a P-type GaN layer on the barrier layer 3.
Epitaxial process conditions of high-purity Mg source as dopant, ammonia gas flow of 4200sccm, gallium source flow of 120 mu mol/min, temperature of 960 deg.C, pressure of 42Torr and hydrogen flow of 4200sccm are set, and a metal organic chemical vapor deposition technique is used to epitaxially form a barrier layer 3 with a thickness of 50nm and a doping concentration of 1 × 1019cm-3Forming a P-type GaN layer.
And 4, manufacturing a P-GaN gate 4 and an array strip 51 on the barrier layer 3.
Making a mask on the P-type GaN layer for the first time, and setting Cl2The flow is 15sccm, the pressure is 12mTorr, the power is 90W, the mask is utilized to etch the P-type GaN layer by using the reactive ion etching technology until the upper surface of the barrier layer is etched, 1P-GaN gate 4 with the thickness b of 50nm on the left side and 5 isolation bars with the thickness c of 50nm on the right side are formed, the distance W between the two adjacent isolation bars is 1000 microns, the distance between the 1 st isolation bar and the upper boundary of the device is equal to the distance between the 5 th isolation bar and the lower boundary of the device is equal to 100 microns, and the 5 isolation bars form an array bar 51.
And 5, manufacturing a source electrode 6 and a drain electrode 7 on the barrier layer 3.
Making mask on the barrier layer 3, P-GaN gate 4 and array strip 51 for the second time, and setting vacuum degree less than 1.8 × 10- 3Pa, power of 500W, evaporation rate of less than
The technological conditions are that the mask is utilized to deposit a plurality of layers of metals on the upper parts of the barrier layers 3 at the left and the right sides by using an electron beam evaporation technology, the plurality of layers of metals are respectively Al, Ti and Au from bottom to top, the thicknesses of the metals are respectively 0.132 mu m/0.016 mu m/0.051 mu m, and N is at the temperature of 860 DEG C2And performing rapid thermal annealing for 35s in the atmosphere to finish the manufacture of the source electrode 6 and the drain electrode 7, wherein the horizontal distance d between the left end of the drain electrode 7 and the right end of the array strip 5 is 2 microns.
And 6, manufacturing a gate metal 8 on the P-GaN gate 4.
The specific implementation of this step is the same as step 6 of the first embodiment.
The specific implementation of this step is the same as step 7 of the first embodiment.
Example five: the barrier layer 3 is made on the silicon substrate with the thickness of 1nm, the array strip 51 contains 3 isolating strips, the thickness of each isolating strip is 1nm, the doping concentration is 5 multiplied by 1015cm-3The distance w between two adjacent spacers is 0.5 μm, and the 1 st spacerThe distance between the spacer and the upper boundary of the device and the distance u between the 3 rd spacer and the lower boundary of the device are both 2.2 μm, and the horizontal distance d between the right end of the array strip 51 and the left end of the drain 7 is 1 μm.
Firstly, AlN and GaN materials are epitaxially grown on a silicon substrate 1 from bottom to top to form a transition layer 2.
The specific implementation of this step is the same as the step one in the second embodiment.
Second, undoped Al is deposited on the undoped GaN transition layer 20.2Ga0.8N forms the barrier layer 3.
Depositing undoped Al with a thickness of 1nm and an aluminum composition of 0.2 on the GaN transition layer 2 by using a metal organic chemical vapor deposition technique0.2Ga0.8The N barrier layer 3 has the following metal organic chemical vapor deposition process conditions: the temperature was 960 deg.C, the pressure was 48Torr, the hydrogen flow was 4500sccm, the ammonia flow was 4500sccm, the gallium source flow was 34. mu. mol/min, and the aluminum source flow was 6. mu. mol/min.
And thirdly, manufacturing a P-type GaN layer on the barrier layer 3.
Using molecular beam epitaxy technique at 1.0X 10-10mbar, radio frequency power of 440W, and N as reactant25nm of epitaxial thickness and 1 multiplied by 10 of doping concentration on the barrier layer 3 under the process condition of the high-purity Ga source17cm-3Forming a P-type GaN layer.
And fourthly, manufacturing the P-GaN gate 4 and the array strips 51 on the barrier layer 3.
4a) Making a mask on the P-type GaN layer for the first time, and using the mask to perform reactive ion etching on Cl2And etching the P-type GaN layer under the process conditions of 15sccm of flow, 12mTorr of pressure and 90W of power, wherein the etching depth f is 4nm, and 1P-GaN block on the left side is formed.
4b) Making a mask on the P-GaN block and the P-type GaN layer for the second time, and using the mask to perform reactive ion etching on Cl2Etching the etched P-type GaN layer in the step 4a) again under the process conditions of the flow of 20sccm, the pressure of 13mTorr and the power of 130W until the upper surface of the barrier layer 3 is etchedAnd 1P-GaN gate 4 with the thickness b of 5nm on the left side and 3 equally-spaced isolation bars with the thickness c of 1nm on the right side are formed, the distance w between every two adjacent isolation bars is 0.5 mu m, the distance between the 1 st isolation bar and the upper boundary of the device is equal to the distance between the 3 rd isolation bar and the lower boundary of the device is equal to 2.2 mu m, and the 3 isolation bars form an array bar 51.
And fifthly, manufacturing a source electrode 6 and a drain electrode 7 on the barrier layer 3.
A mask is formed for the third time on the barrier layer 3, the P-GaN gate 4 and the array bar 51, and the electron beam evaporation technique is used to form the mask under the vacuum degree of 1.6 × 10-3Pa, power 540W, evaporation rate
Under the process conditions of (1), depositing a plurality of layers of metals on the left and right sides of the upper part of the barrier layer 3, wherein the plurality of layers of metals are respectively Ti, Ni and Au from bottom to top, the thicknesses of the metals are respectively 0.016 mu m/0.175 mu m/0.051 mu m, and N is at the temperature of 850 DEG C2And performing rapid thermal annealing in the atmosphere for 35s to form the source electrode 6 and the drain electrode 7, wherein the distance d between the left end of the drain electrode 7 and the right end of the array strip 51 is 1 μm.
And sixthly, manufacturing gate metal 8 on the P-GaN gate 4.
The specific implementation of this step is the same as step six of the second embodiment.
Seventh step, a bar metal 52 is fabricated on the array bar 51.
The specific implementation of this step is the same as step seven of the second embodiment.
Example six: the barrier layer 3 is made on the silicon carbide substrate with the thickness of 25nm, the array strip 51 contains 4 isolating strips, the thickness of each isolating strip is 5nm, the doping concentration is 1 multiplied by 1022cm-3The distance w between two adjacent spacers is 20 μm, the distance between the 1 st spacer and the upper boundary of the device and the distance between the 4 th spacer and the lower boundary of the device are both 4.2 μm, and the horizontal distance d between the right end of the array bar 51 and the left end of the drain 7 is 0 μm.
And 1, epitaxial growth of AlN and GaN materials on the silicon carbide substrate 1 from bottom to top to form a transition layer 2.
The specific implementation of this step is the same as step a of the third embodiment.
Deposition of undoped Al on the undoped GaN transition layer 20.1Ga0.9N forms the barrier layer 3.
Undoped Al with a thickness of 25nm and an Al component of 0.1 was deposited on the GaN transition layer 2 by MOCVD0.1Ga0.9The N barrier layer 3 has the following metal organic chemical vapor deposition process conditions: the temperature is 970 ℃, the pressure is 45Torr, the hydrogen flow is 4400sccm, the ammonia flow is 4400sccm, the gallium source flow is 36 mu mol/min, and the aluminum source flow is 6 mu mol/min.
And 3. manufacturing a P type GaN layer on the barrier layer 3.
Setting the epitaxial process conditions as 940 deg.C, 44Torr pressure, 4800sccm hydrogen flow, high purity Ga source as dopant, 4800sccm ammonia flow, 100 mu mol/min gallium source flow, and using metal organic chemical vapor deposition technique to epitaxially form 400nm thickness and 1 × 10 doping concentration on the barrier layer 322cm-3Forming a P-type GaN layer.
And 4. manufacturing the P-GaN gate 4 and the array strips 51 on the barrier layer 3.
4-1) setting the process conditions adopted by etching as follows: cl2A flow rate of 15sccm, a pressure of 12mTorr, a power of 90W,
and manufacturing a mask on the P-type GaN layer for the first time, and etching the P-type GaN layer by using the mask and a reactive ion etching technology, wherein the etching depth is 395nm, and 1P-GaN block on the left side is formed.
4-2) setting the process conditions adopted by etching as follows: cl2Making a mask on the P-GaN block and the P-type GaN layer for the second time with the flow of 23sccm, the pressure of 29mTorr and the power of 175W, etching the P-type GaN layer etched in the step 4-1) again by using the mask and a reactive ion etching technology until the upper surface of the barrier layer 3 to form 1P-GaN gate 4 with the thickness of 400nm at the left side and 4 isolation bars with the thickness of 5nm at the right side, wherein the distance W between the two adjacent isolation bars is 20 micrometers, and the distance between the 1 st isolation bar and the upper boundary of the device is equal to the distance between the 4 th isolation bar and the deviceThe distance of the lower border of the strip is equal to 4.2 μm, and the 4 spacer bars constitute the array bar 51.
And 5, manufacturing a source electrode 6 and a drain electrode 7 on the barrier layer 3.
The technological conditions for setting the electron beam evaporation technology are as follows: vacuum degree less than 1.8X 10-3Pa, power of 400W, evaporation rate of less than
A mask is made on the barrier layer 3, the P-GaN gate 4 and the array strip 51 for the third time, a plurality of layers of metal are deposited on the upper parts of the barrier layer 3 at the left side and the right side by using an electron beam evaporation technology, the plurality of layers of metal are respectively Ta/Ni/Au from bottom to top, the thickness of the plurality of layers of metal is respectively 0.016 mu m/0.177 mu m/0.058 mu m, and the N is heated to 840 DEG C2Performing rapid thermal annealing for 35s in the atmosphere to form a source electrode 6 and a drain electrode 7, wherein the horizontal distance d between the left end of the drain electrode 7 and the right end of the array strip 51 is 0 μm;
and 6, manufacturing a gate metal 8 on the P-GaN gate 4.
The specific implementation of this step is the same as step E of the third embodiment.
7. strip metal 52 is fabricated on array strip 51.
The specific implementation of this step is the same as step F of the third embodiment.
The effects of the present invention can be further illustrated by the following simulations.
Simulation: current collapse characteristic simulation is performed on the conventional device and the device according to the second embodiment of the present invention, and the results are shown in fig. 7, where fig. 7(a) is the current collapse characteristic simulation result of the conventional device, and fig. 7(b) is the current collapse characteristic simulation result of the device according to the second embodiment of the present invention.
As can be seen from the comparison between fig. 7(a) and fig. 7(b), the conventional device has a significant current collapse phenomenon, and compared with the conventional device, the pulse output current of the enhancement type switching transistor based on the array strip manufactured by the invention is closer to the direct current test result, which shows that the enhancement type switching transistor based on the array strip manufactured by the invention can effectively inhibit the current collapse effect and has good characteristics.
The foregoing description is only illustrative of six specific embodiments of the present invention and is not to be construed as limiting the invention, it will be apparent to those skilled in the art that various modifications and variations in form and detail can be made in the method according to the present invention without departing from the principle and scope of the invention, but such modifications and variations are still within the scope of the invention as defined in the appended claims.
Claims (10)
1. An array stripe based enhancement mode switching transistor comprising from bottom to top: substrate (1), transition layer (2) and barrier layer (3), barrier layer (3) upper portion is equipped with P-GaN bars (4), and the deposit of P-GaN bars (4) upper portion has gate metal (8), and the upper portion left and right side edge of barrier layer (3) is equipped with source electrode (6) and drain electrode (7) respectively, its characterized in that:
a modulation electrode (5) is arranged on the barrier layer (3) between the P-GaN gate (4) and the drain electrode (7), and the modulation electrode (5) is composed of an array strip (51) at the lower part and a strip metal (52) at the upper part;
the array strips (51) are composed of m spacer strips with equal spacing, the m spacer strips are horizontally arranged on the barrier layer (3) and are arranged in parallel, the spacing between two adjacent spacer strips is w, and the doping concentration of each spacer strip is 5 multiplied by 1015～1×1022cm-3The distance between the 1 st isolating bar and the upper boundary of the device and the distance between the mth isolating bar and the lower boundary of the device are both u; wherein m is a positive integer, and u is a number when m is 1>0μm，m>U is more than or equal to 0 mu m at 1.
2. Device according to claim 1, characterized in that the substrate (1) is made of sapphire or silicon carbide or silicon or graphene or other materials.
3. The device according to claim 1, wherein the thickness of each spacer in the array strips (51) is equal and less than or equal to the thickness of the P-GaN gate (4).
4. The device according to claim 1, wherein the horizontal distance d between the right end of the array stripe (51) and the left end of the drain (7) is greater than or equal to 0 μm.
5. A device according to claim 1, characterized in that the strip metal (52) is electrically connected to the drain (7).
6. The device according to claim 1, characterized in that the metal of the lowest layer of the drain (7) is selected to be close to the work function of the barrier layer (3) to ensure good ohmic contact between the drain (7) and the barrier layer (3).
7. A manufacturing method of an enhancement type switch transistor based on an array strip is characterized by comprising the following steps:
A) a GaN-based wide bandgap semiconductor material is epitaxially grown on a substrate (1) to form a transition layer (2);
B) extending a GaN-based wide bandgap semiconductor material on the transition layer (2) to form a barrier layer (3) with the thickness of a;
C) a P-type GaN semiconductor material is epitaxially formed on the barrier layer (3) to a thickness of b and a doping concentration of 5 × 1015～1×1022cm-3The P-type GaN layer of (1);
D) manufacturing a mask on the P-type GaN layer for the first time, etching the P-type GaN layer by using the mask until the upper surface of the barrier layer (3) is etched to form 1P-GaN gate (4) with the thickness of b on the left side and m P-GaN blocks which are arranged in parallel and are equidistant and with the thickness of b on the right side, wherein the distance between every two adjacent P-GaN blocks is w;
E) manufacturing a mask on the barrier layer (3), the P-GaN gate (4) and the m P-GaN blocks for the second time, etching the P-GaN blocks by using the mask, wherein the etching depth f is greater than or equal to 0 mu m and smaller than the thickness of the P-GaN gate (4), and forming m equally-spaced isolating strips with the thickness of c on the right side, namely f + c-b; when c is less than or equal to 5nm, almost no depletion effect of each isolating strip on two-dimensional electron gas in a channel formed between the lower barrier layer (3) and the transition layer (2) of the device is realized in a balanced state, and when c is greater than 5nm, the depletion effect of each isolating strip on the two-dimensional electron gas in the channel formed between the lower barrier layer (3) and the transition layer (2) of the device is gradually increased along with the increase of the thickness c of each isolating strip; the distance between the 1 st isolating bar and the upper boundary of the device is equal to the distance between the mth isolating bar and the lower boundary of the device, namely u, and the m isolating bars form an array bar (51), wherein m is a positive integer and u is greater than 0 μm when m is 1 and is greater than or equal to 0 μm when m is 1;
F) manufacturing a mask on the barrier layer (3), the P-GaN gate (4) and the array strip (51) for the third time, depositing metal on the upper parts of the barrier layer (3) on the left side and the right side by using the mask, and performing rapid thermal annealing to finish the manufacture of the source electrode (6) and the drain electrode (7), wherein the horizontal distance d between the left end of the drain electrode (7) and the right end of the array strip (51) is more than or equal to 0 mu m;
G) making a mask on the barrier layer (3), the P-GaN gate (4), the array strip (51), the source electrode (6) and the drain electrode (7) for the fourth time, and depositing metal on the upper part of the P-GaN gate (4) by using the mask to finish the making of gate metal (8);
H) and (3) making a mask on the barrier layer (3), the P-GaN gate (4), the array strips (51), the source electrode (6), the drain electrode (7) and the gate metal (8) for the fifth time, depositing metal on the upper part of each isolation strip in the array strips (51) by using the mask to form strip metal (52), and electrically connecting the strip metal (52) with the drain electrode (7) to finish the manufacture of the whole device.
8. A manufacturing method of an enhancement type switch transistor based on an array strip is characterized by comprising the following steps:
1) a GaN-based wide bandgap semiconductor material is epitaxially grown on a substrate (1) to form a transition layer (2);
2) extending a GaN-based wide bandgap semiconductor material on the transition layer (2) to form a barrier layer (3) with the thickness of a;
3) a P-type GaN semiconductor material is epitaxially formed on the barrier layer (3) to a thickness of b and a doping concentration of 5 × 1015～1×1022cm-3The P-type GaN layer of (1);
4) manufacturing a mask on the P-type GaN layer for the first time, etching the P-type GaN layer by using the mask, wherein the etching depth f is greater than or equal to 0 mu m and smaller than the thickness b of the P-type GaN layer, and forming a P-GaN block on the left side;
5) manufacturing a mask on the P-GaN block and the P-type GaN layer for the second time, etching the etched P-type GaN layer in the step 4) again by using the mask until the upper surface of the barrier layer (3) is etched, and forming a P-GaN gate (4) with the thickness of b on the left side and m equally-spaced isolating strips with the thickness of c on the right side, namely f + c b; when c is less than or equal to 5nm, almost no depletion effect of each isolating strip on two-dimensional electron gas in a channel formed between the lower barrier layer (3) and the transition layer (2) of the device is realized in a balanced state, and when c is greater than 5nm, the depletion effect of each isolating strip on the two-dimensional electron gas in the channel formed between the lower barrier layer (3) and the transition layer (2) of the device is gradually increased along with the increase of the thickness c of each isolating strip; the distance between two adjacent isolating bars is w, the distance between the 1 st isolating bar and the upper boundary of the device is equal to the distance between the m th isolating bar and the lower boundary of the device, namely u, the m isolating bars jointly form an array bar (51), wherein m is a positive integer, and u is greater than 0 μm when m is 1, and u is greater than or equal to 0 μm when m is greater than 1;
6) manufacturing a mask on the barrier layer (3), the P-GaN gate (4) and the array strip (51) for the third time, depositing metal on the upper parts of the barrier layer (3) on the left side and the right side by using the mask, and performing rapid thermal annealing to finish the manufacture of the source electrode (6) and the drain electrode (7), wherein the horizontal distance d between the left end of the drain electrode (7) and the right end of the array strip (51) is more than or equal to 0 mu m;
7) making a mask on the barrier layer (3), the P-GaN gate (4), the array strip (51), the source electrode (6) and the drain electrode (7) for the fourth time, and depositing metal on the upper part of the P-GaN gate (4) by using the mask to finish the making of gate metal (8);
8) and (3) making a mask on the barrier layer (3), the P-GaN gate (4), the array strips (51), the source electrode (6), the drain electrode (7) and the gate metal (8) for the fifth time, depositing metal on the upper part of each isolation strip in the array strips (51) by using the mask to form strip metal (52), and electrically connecting the strip metal (52) and the drain electrode (7) to finish the manufacture of the whole device.
9. The method of claim 7, wherein: the epitaxial technique used in steps A), B), C) comprises: metal organic chemical vapor deposition, hydride vapor phase epitaxy, and molecular beam epitaxy.
10. The method of claim 7, wherein: the metal deposition process used in steps F), G), H) comprises: electron beam evaporation process, sputtering process.
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