CN111863950B - Junction gate-drain power device - Google Patents
Junction gate-drain power device Download PDFInfo
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
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Abstract
The invention discloses a junction type gate-drain power device, which mainly solves the problems of low threshold voltage and complex process for realizing high breakdown voltage of the conventional power switch device and comprises the following steps: the transistor comprises a substrate (1), a transition layer (2), a barrier layer (3), a gate groove (4), a drain groove (5), a P-type layer (6), a gate column (7), an N-type drain column (8), a source electrode (11), an ohmic contact (12), a table top (14), a grid electrode (15) and a passivation layer (16). A P-type row column (81) is arranged in the N-type leakage column; an N-type row column (9) is arranged in the grid column, and array holes (10) are formed in the barrier layer on the left side of the grid column and the barrier layer on the right side of the N-type drain column; a drain electrode (13) is arranged above the N-type drain column and the ohmic contact; the upper part of the passivation layer is provided with a composite plate (17); the passivation layer and the periphery of the composite plate are provided with a protective layer (18). The invention has simple process, good forward blocking and reverse blocking, high threshold voltage, and can be used as a switch device.
Description
Technical Field
The invention belongs to the technical field of microelectronics, and particularly relates to a power switch device which can be used as a basic device of a power electronic system.
Technical Field
The power electronic system is widely applied to the fields of aerospace, industrial equipment, electric automobiles, household appliances and the like, and the power switch device is an important element of the power electronic system and is an important tool for realizing energy conversion and control. Therefore, the performance and reliability of the power switch device have a decisive influence on various technical indexes and performances of the whole power electronic system. At present, the performance of Si-based power switching devices has approached their theoretical limit and cannot meet the requirements of next generation of power electronic systems for high temperature, high voltage, high frequency, high efficiency and high power density. The third generation wide bandgap semiconductor material represented by GaN has the characteristics of large forbidden band width, high saturated electron drift velocity, large critical breakdown electric field and stable chemical property, and has unique advantages in the aspect of preparing power switching devices with lower on resistance, higher switching speed and higher breakdown voltage. Particularly, a high electron mobility device transistor based on a GaN-based heterojunction structure, namely a GaN-based high electron mobility transistor HEMT power switch device, has wide and special application prospects in the fields of national economy and military due to the excellent power characteristics of the high electron mobility device transistor.
The traditional GaN-based HEMT power switch device is based on a GaN-based heterojunction structure, and comprises: the device comprises a substrate, a transition layer, a barrier layer, a P-type layer, a gate column, a source electrode, a drain electrode, a grid electrode, a table board and a protective layer; a source electrode is deposited on the left side above the barrier layer, a drain electrode is deposited on the right side above the barrier layer, a P-type layer is epitaxially deposited on the barrier layer between the source electrode and the drain electrode, a gate electrode is deposited on the P-type layer, and the protective layer completely covers the barrier layer, the P-type layer, the source electrode, the drain electrode and the region above the gate electrode, as shown in FIG. 1.
However, in the conventional GaN-based HEMT power switching device, the activation rate of the P-type impurity magnesium in the P-type layer is low, and it is difficult to realize a highly doped P-type layer, so that the threshold voltage of the device tends to be lower than 2V. And studies have shown that a P-type layer with too high a doping concentration can in turn lead to a reduction in the threshold voltage of the device, see On the physical operation and optimization of the P-GaN gate in normal-off GaN HEMT devices, Applied Physics Letters, Vol.110, No.12, pp.1-5,2017. In addition, in the conventional GaN-based HEMT power switch device, an extremely high electric field peak is usually formed near the drain electrode of the device, so that when a positive drain voltage is applied to the device, namely, when the device is in a forward off state, the forward breakdown voltage of the device is far lower than a theoretically expected value, and the reliability problems of current collapse, inverse piezoelectric effect and the like exist, so that the practical application of the device is severely restricted. In order to solve the above practical problems, researchers have proposed many methods, and the multilayer field plate structure is one of the most significant ones, see A130-W Boost Converter Operation Using a High-Voltage GaN-HEMT, IEEE Electron devices Letters, Vol.29, No.1, pp.8-10,2008.
In many technical fields of current electric vehicles, power management systems, class-S power amplifiers and the like, a power switching device is often required to have a strong reverse blocking capability, i.e., a reverse off-state capability, that is, it is desirable that the device has a high negative drain breakdown voltage, i.e., a reverse breakdown voltage, in an off-state. Since the drain of the conventional GaN-based HEMT power switching device is ohmic contact, a reverse voltage cannot be applied. Researchers have proposed a power switching Device using a Schottky Drain, see AlGaN/GaN HEMT With Integrated processed Schottky-Drain detection Diode, IEEE Electron devices Letters, vol.30, No.9, pp.901-903,2009. However, the schottky drain has a very limited ability to improve the reverse blocking characteristic of the device, so in order to further improve the reverse blocking capability of the power switching device, researchers have proposed a power switching device based on a source field plate and a drain field plate to take account of the forward and reverse blocking capabilities of the device, see Design optimization of high breakdown voltage AlGaN-GaN power HEMT on an insulating substrate for RONA-VBTransdeoff characteristics, IEEE Transactions on Electron Devices, Vol.52, No.1, pp.106-111,2005. In addition, the double-layer field plate structure is combined with the power switch device based on the source field plate and the drain field plate, namely the source field plate with the double-layer field plate structure and the drain field plate with the double-layer field plate structure are adopted to form the source-drain composite double-layer field plate power switch device, so that the forward and reverse breakdown voltages of the device can be further improved. However, the source-drain composite double-layer field plate power switch device has complex process and higher manufacturing cost, and the manufacturing of each layer of field plate needs photoetching, metal deposition and passivation medium depositionAnd the like. And moreover, the thickness of the dielectric material under each layer of field plate needs to be optimized to realize the maximization of breakdown voltage, and complicated process debugging and optimization are needed, so that the difficulty of manufacturing the device is greatly increased, and the yield of the device is reduced.
Disclosure of Invention
The invention aims to provide a junction type gate-drain power device aiming at the defects of the prior art, so as to remarkably improve the threshold voltage and the bidirectional blocking voltage of the device, effectively reduce the on-resistance of the device, reduce the manufacturing difficulty of the device and improve the reliability of the device.
In order to achieve the purpose, the technical scheme of the invention is realized as follows:
first, device structure
A junction gate-drain power device comprising, from bottom to top: a substrate 1, a transition layer 2, a barrier layer 3 and a passivation layer 16; a gate groove 4 and a drain groove 5 are carved in the barrier layer 3, a table surface 14 is carved on the side surface of the barrier layer, and a gate column 7 is arranged at the upper part of the gate groove 4; the upper portion of grid post 7 deposits there is grid 15, and its left side deposits there is source 11, its characterized in that:
the gate column 7 consists of a P-type layer 6 in the gate groove 4 and a P-type layer 6 on the upper part of the gate groove 4, the lower end of the P-type layer 6 is completely filled in the gate groove 4, and an N-type row column 9 is injected into the gate column 7;
the upper part of the leakage groove 5 is provided with an N-shaped leakage column 8, and the right side of the leakage groove is deposited with an ohmic contact 12;
a P-type row column 10 is injected into the N-type leakage column 8, the P-type row column is composed of w rectangular P columns which are equally spaced and have the same size, and w is greater than 0;
a drain electrode 13 is deposited on the upper parts of the N-type drain column 8 and the ohmic contact 12 together, the N-type drain column 8, the ohmic contact 12 and the drain electrode 13 are electrically connected with each other, and the lower end of the N-type drain column 8 is completely filled in the drain groove 5;
the N-shaped row columns 9 comprise m rectangular N columns which are equally spaced and have the same size>0, each rectangular N column is composed of a lower rectangular N-Column 91 and upper rectangle N+A post 92;
array holes 19 are etched in the barrier layer 3 at the positions on the left side of the gate column 7 and the right side of the N-type drain column 8;
the gate 15, its lower edge and all N+The upper edges of the posts 92 are coincident;
2N +1 grooves with the same size are etched in the region between the grid column 7 and the N-type drain column 8 on the upper portion of the passivation layer 16; the groove is provided with a composite plate 17, and n is more than or equal to 1;
the composite plate 17 is composed of a left modulation plate, a right modulation plate and 2n-1 independent metal blocks with the same size, the lower ends of the metal blocks are completely filled in 2n +1 grooves, the left modulation plate is electrically connected with the source electrode 11, the right modulation plate is electrically connected with the drain electrode 13, the independent metal blocks are suspended in the air, the left modulation plate and the grid electrode 15 are overlapped in the horizontal direction, the right modulation plate and the drain electrode 13 are overlapped in the horizontal direction, and the left modulation plate and the right modulation plate are symmetrically distributed in the left-right direction by taking the nth independent metal block as the center; the composite plate 17 and the passivation layer 16 are provided with a protective layer 18 on their periphery.
Further, the length a of the gate groove 41Greater than or equal to 2nm, and depth z thereof1Is less than the thickness of the barrier layer 3, and z1>0。
Further, the length a of the leakage groove 52Greater than or equal to 2nm and a depth z2，z2>0。
Furthermore, the length of the gate post 7 is more than or equal to 4nm, and the distance between the left edge of the gate post and the left edge of the gate groove 4 is q1The distance between the right edge of the gate groove 4 and the right edge of the gate groove is q2And q is1＝q2The length of the gate 15 is equal to the length of the gate pillar 7.
Further, the doping concentration of the N-type drain column 8 is 1 × 1016～5×1020cm-3The lower end of the barrier layer is completely filled in the leak groove 5 and is positioned at the thickness h above the barrier layer 3110 to 1200 nm.
Further, the depth of the P-type bent 10 is u1The depth of the leak 5 is z2The thickness of the N-shaped leakage column 8 above the leakage groove 5 is h1，u1<z2+h1。
Further, each rectangle in the P-type bent 10The width of the P column is O1The distance between two adjacent rectangular P columns is O2The left edge of the first rectangular P column coincides with the left edge of the N-type leakage column 8, and the distance between the right edges of the w-th rectangular P column and the N-type leakage column 8 is O3The length of the leak groove 5 is a2，O1＝O2＝O3And satisfies (2w) × (O)1)＝a2。
Further, the doping concentration of the P-type row column 10 is 1 × 1016～5×1020cm-3And the doping concentration of the N-type drain column 8 is less than or equal to that of the N-type drain column.
Further, in the gate post 7, N-Column 91 and N+The posts 92 are of the same width, x1Two adjacent N+The posts 92 are spaced at a distance x2First N+The left edge of the pillar 92 coincides with the left edge of the gate pillar 7, the mth N+The right edge of pillar 92 is spaced from the right edge of gate pillar 7 by a distance x3The length of the gate groove 4 is a1The distance between the left edge of the grid column 7 and the left edge of the grid groove 4 is q1The distance between the right edge of the gate groove 4 and the right edge of the gate groove is q2，x1＝x2＝x3And satisfies (2m) × x1＝q1+a1+q2。
Further, said N-The depth of the column 91 is y1，N+The depth of the post 92 is y2The thickness of the P-type layer 6 is h 220 to 1000nm, y1>0，y2>0, and y1+y2<h2。
Further, the doping concentration of the P-type layer 6 is 5 × 1016～5×1020cm-3，N+The doping concentration of the pillars 92 is 1 × 1018～5×1020cm-3，N-The doping concentration of the pillar 91 is 1 × 1011～1×1018cm-3And N is-The doping concentrations of the pillars 91 are all less than N+The doping concentration of the pillars 92 and the doping concentration of the P-type layer 6.
Further, the array of holes 19 is composed of f × g holes having the same size, f>1，g>1, each hole is longer than the upper partA square hole column 191 and a lower rectangular pyramid 192, the distance k between two adjacent holes30.5 to 3 μm, and a boundary distance k between the outermost hole and the source electrode 11 or the ohmic contact 1211-4 μm; the upper and lower surfaces of the hole column 191 are square, and the side length k of the square20.5-2 μm, the depth r of the hole columns 101 is 2-20 nm, and the lower surfaces of the hole columns 191 are overlapped with the upper surfaces of the rectangular pyramids 192; the depth e of the rectangular pyramid 192 is 1 to 35nm, and the four sides are the same.
Further, the lengths of the source electrode 11 and the ohmic contact 12 are both LOAll width being WOThe length of the leak groove 5 is a2The length of the drain electrode 13 is a2+LOWidth of WO。
Further, the drain electrode 13 adopts a multi-layer metal combination, the work function of the lowest layer metal is larger than 5eV, and the barrier height formed by the lowest layer metal contacting with each rectangular P column in the P-type row column 10 is smaller than the barrier height formed by the lowest layer metal contacting with the N-type drain column 8.
Further, the gate 15 adopts a multi-layer metal combination, the work function of the lowest layer metal is less than 5eV, and the barrier height formed by the lowest layer metal contacting each rectangular N column in the N-type row columns 9 is less than the barrier height formed by the lowest layer metal contacting the P-type layer 6.
Further, the grooves on the passivation layer 16 have the same size, and the depth d of each groove is greater than 0 μm and smaller than the thickness and width a of the passivation layer 1630.1 to 4 μm.
Further, the composite board 17 takes the nth independent metal block as the symmetry axis, and on the left side of the symmetry axis, the distance between the left modulation board and the first independent metal block is S1The distance between the first independent metal block and the second independent metal block is S2In this way, the distance between the n-1 th independent metal block and the n-th independent metal block is Sn，S1<S2<...<Sn(ii) a On the right side of the symmetry axis, the distance between the right modulation plate and the 1 st independent metal block is U1The distance between the 1 st independent metal block and the 2 nd independent metal block is U2By analogy, the n-1 th independent metal block and the n-th independent metal blockThe distance between the independent metal blocks is Un，U1<U2<...<UnAnd S is1＝U1，S2＝U2，...，Sn＝Un，n≥1。
Further, the thickness of the left modulation board, the thickness of the right modulation board and the thickness of each independent metal block are the same, the length t of each independent metal block is 0.5-5 microns, the distance between the right edge of the left modulation board and the right edge of the grid column 7 is equal to the distance between the left edge of the right modulation board and the left edge of the N-type drain column 8, and the distance is L.
Furthermore, each groove takes the (n + 1) th groove as a symmetry axis, and the distance between the grid column 7 and the first groove is b on the left side of the symmetry axis1And 0 μm<b1<(L-a3) The distance between the first groove and the second groove is c1And so on, the distance between the nth groove and the (n + 1) th groove is cn，c1<c2<...<cn(ii) a On the right side of the symmetry axis, the distance between the N-type leakage column 8 and the 1 st groove is b2And 0 μm<b2<(L-a3) The distance between the 1 st groove and the 2 nd groove is i1By analogy, the distance between the nth groove and the (n + 1) th groove is in，i1<i2<...<inAnd b is1＝b2,c1＝i1,c2＝i2,…,cn＝in,n≥1。
Second, the manufacturing method
The invention discloses a method for manufacturing a junction type gate-drain power device, which is characterized by comprising the following steps of:
A) a GaN-based wide bandgap semiconductor material is epitaxially grown on a substrate 1 by adopting a metal organic chemical vapor deposition technology to form a transition layer 2 with the thickness of 1-10 mu m;
B) extending a GaN-based wide bandgap semiconductor material on the transition layer 2 by adopting a metal organic chemical vapor deposition technology to form a barrier layer 3 with the thickness of 4-60 nm;
C) manufacturing a gate groove 4 and a drain groove 5:
C1) manufacturing a mask on the barrier layer 3 for the first time, and etching in the barrier layer 3 by using the mask to form a gate groove 4, wherein the depth of the gate groove 4 is less than the thickness of the barrier layer 3;
C2) manufacturing a mask on the barrier layer 3 and the gate groove 4 for the second time, and etching in the barrier layer 3 by using the mask to form a drain groove 5;
D) a P-type GaN semiconductor material is epitaxially grown on the barrier layer 3 by molecular beam epitaxy, and the gate trench 4 and the drain trench 5 are filled to a thickness h220-1000 nm, and 5 × 10 of doping concentration16～5×1020cm-3P-type layer 6;
E) manufacturing a gate column 7 and an N-type drain column 8:
E1) making a mask on the P-type layer 6 for the third time, etching the two sides of the P-type layer 6 by using the mask, etching the outside of the leak groove 5 until the upper surface of the barrier layer 3, and etching the inside of the leak groove 5to the bottom thereof to form a gate post 7 with the length being more than or equal to 4 nm;
E2) making a mask on the barrier layer 3 and the gate post 7 for the fourth time, and using the mask to epitaxially grow N-type GaN semiconductor material in the drain trench 5 by using selective epitaxial growth technique to form a thickness h1An N-type drain column 8 with the length of 10-1200 nm and the length of more than or equal to 2 nm;
F) manufacturing an N-type row column 9 and a P-type row column 10:
F1) making a mask on the barrier layer 3, the gate column 7 and the N-type drain column 8 for the fifth time, and implanting N-type impurities into the P-type layer 6 by using the mask and using ion implantation technology to form m equally spaced N with the same size-A post 91;
F2) continuing to use the mask of F1), implanting N-type impurities again by using ion implantation technique to form m equally spaced N with the same size+Column 92, m of N+Column 92 and m N-The columns 91 together form an N-type bent 9;
F3) making a mask on the barrier layer 3, the gate column 7 and the N-type drain column 8 for the sixth time, and injecting P-type impurities into the N-type drain column 8 by using the mask through an ion injection technology to form w rectangular P columns which are equidistant and have the same size, wherein the w rectangular P columns form a P-type bent column 10;
G) manufacturing array holes 19:
G1) a mask is manufactured on the barrier layer 3, the gate column 7 and the upper part of the N-type drain column 8 for the seventh time, and the barrier layers on the left side and the right side are etched by using the mask to form f multiplied by g cuboid hole columns 191 with the same size;
G2) making a mask on the barrier layer 3, the gate column 7 and the upper part of the N-type drain column 8 for the eighth time, etching the inside of f × G cuboid hole columns 191 with the same size formed by G1) by using the mask to form rectangular pyramids 192 at the lower parts of the hole columns 191, wherein the f × G cuboid hole columns 191 with the same size and the rectangular pyramids 192 at the lower parts form array holes 19 together;
H) manufacturing a source electrode 11 and a drain electrode 13:
H1) making masks on the barrier layers 3, the gate columns 7 and the upper parts of the N-type drain columns 8 for the ninth time, depositing metal on the barrier layers 3 on the left side and the right side by using an electron beam evaporation technology by using the masks, and completely filling the array holes 19, wherein the metal adopts Gd, Zr or Ta;
H2) continuing with the mask in H1), depositing metal again by electron beam evaporation, and applying a voltage to the substrate2Performing rapid thermal annealing in the atmosphere, wherein the metal adopts one of Ti/Al/Ni/Au, Ti/Al/Mo/Au or Ti/Al/Ti/Au to form a source electrode 11 and an ohmic contact 12;
H3) making masks on the barrier layer 3, the gate column 7, the N-type drain column 8, the source electrode 11 and the ohmic contact 12 for the tenth time, depositing metal again by adopting an electron beam evaporation technology, wherein the metal is formed by combining multiple layers of metal, the work function of the metal at the lowest layer is more than 5eV, the barrier height formed by the contact of the metal at the lowest layer and each rectangular P column in the P-type row columns 10 is less than the barrier height formed by the contact of the metal at the lowest layer and the N-type drain column 8, so that a drain electrode 13 is formed, and the N-type drain column 8, the ohmic contact 12 and the drain electrode 13 are electrically connected with each other;
I) manufacturing masks on the barrier layer 3, the gate column 7, the source electrode 11 and the drain electrode 13 for the eleventh time, etching the barrier layer 3 on the left side of the source electrode 11 and the right side of the drain electrode 13 by using the masks, and forming a table-board 14, wherein the depth of an etching area is greater than the thickness of the barrier layer;
J) making a mask on the barrier layer 3, the gate column 7, the source electrode 11, the drain electrode 13 and the upper part of the table top 14 for the twelfth time, depositing a multi-layer metal combination on the upper part of the gate column 7 by using the mask through an electron beam evaporation technology, wherein the work function of the metal at the lowest layer is less than 5eV, the barrier height formed by the contact of the metal at the lowest layer and each rectangular N column in the N-type row column 9 is less than the barrier height formed by the contact of the metal at the lowest layer and the P-type layer 6, and making a gate electrode 15, wherein the length of the gate electrode 15 is equal to the length of the gate column 7;
K) depositing a passivation layer 16 with the thickness of more than or equal to 100nm on the upper parts of the gate column 7, the source electrode 11, the drain electrode 13 and the gate electrode 15 and the peripheral area thereof by adopting a plasma enhanced chemical vapor deposition technology;
l) manufacturing a mask on the passivation layer 16 for the thirteenth time, and etching 2N +1 grooves with the same size on the passivation layer 16 between the gate column 7 and the N-type drain column 8 by using the mask, wherein N is more than or equal to 1;
m) manufacturing masks on the passivation layer 16 and the upper part of the groove for the fourteenth time, depositing metal on the upper part of the passivation layer 16 and in the groove by using an electron beam evaporation technology by using the masks, wherein the lower end of the metal is completely filled in the groove, sequentially manufacturing a left modulation plate, 2n-1 independent metal blocks and a right modulation plate, wherein n is more than or equal to 1, the left modulation plate is electrically connected with the source electrode 11, the right modulation plate is electrically connected with the drain electrode 13, the independent metal blocks are suspended from each other, the left modulation plate is overlapped with the grid electrode 15 in the horizontal direction, the right modulation plate is overlapped with the drain electrode 13 in the horizontal direction, and the left modulation plate and the right modulation plate are symmetrically distributed left and right by taking the nth independent metal block as the center to form a composite plate 17;
n) in the peripheral area of the passivation layer 16 and the composite board 17, the protective layer 18 is deposited by using an insulating dielectric material and adopting a plasma enhanced chemical vapor deposition technology, and the manufacturing of the whole device is completed.
Compared with the traditional GaN-based HEMT power switch device, the device has the following advantages:
in the first device of the present invention, since the gate pillar embedded with the N-type row pillar is adopted below the gate 15, and the barrier height formed by the contact of the gate metal and each rectangular N-pillar in the N-type row pillar 9 is smaller than the barrier height formed by the contact of the gate metal and the P-type layer 6, when the gate is forward biased, the PN junction formed by each rectangular N-pillar in the N-type row pillar 9 and the adjacent P-type layer 6 on the right side thereof is in a reverse biased state, and the PIN junction formed by each rectangular N-pillar in the N-type row pillar 9 and the P-type layer 6 on the lower portion thereof is also in a reverse biased state, these N-pillars and P-type layers are in a reverse biased stateThe PN junction and the PIN junction which are reversely biased form a high-resistance space charge region, so that most of grid voltage can be shared, and N in the N-type bent posts 9 is adjusted+Doping concentration and depth of column 92, N-The doping concentration and depth of the pillars 91, the number of rectangular N pillars in the N-type row pillars 9, and the doping concentration and thickness of the P-type layer 6 can realize the continuous increase of the threshold voltage of the device. Therefore, the threshold voltage of the device can be obviously improved.
Secondly, the device of the invention adopts the structure of the array holes 19 under the drain ohmic contact and the source, and the electrical characteristics of the metal in each hole and the barrier layer contact can be effectively modulated by adjusting the shapes of the cuboid hole column 191 at the upper part and the rectangular pyramid 192 at the lower part of each hole in the array holes 19 and the relative position relationship of each hole, thereby effectively reducing the ohmic contact resistance of the source and the drain of the device.
Thirdly, the device adopts an N-type leakage column structure embedded with a P-type row column, the barrier height formed by the contact of metal adopted by a drain electrode 13 and each rectangular P column in the P-type row column 10 is smaller than the barrier height formed by the contact of the metal adopted by the drain electrode 13 and the N-type leakage column 8, when the device is reversely blocked, namely a grid electrode is biased at 0V, and when a low potential smaller than a source electrode potential is applied to a drain electrode, each rectangular P column in the P-type row column and an adjacent N-type semiconductor form a reverse biased PN junction, and high-resistance space charge regions of the PN junctions can share most drain electrode voltage, so that the device can realize high reverse breakdown voltage; when the device is conducted in the forward direction, namely the grid bias voltage is larger than the threshold voltage, and the drain electrode applies a high potential larger than the source electrode potential, the PN junction formed between each rectangular P column in the P-type row columns and the adjacent N-type semiconductor is in a forward bias state, so that a large number of holes are injected into the device from the N-type drain columns, and the output current of the device can be remarkably improved.
Fourthly, the composite plate 17 structure is adopted above the passivation layer 16, so that the potential distribution in the barrier layer between the gate column 7 and the N-type drain column 8 can be effectively modulated, when the device is blocked in the forward direction, namely the gate is biased at 0V, and the drain applies a high potential greater than the potential of the source, the potential in the barrier layer can be increased from the gate column 7 to the N-type drain column 8 in a gradual change mode, and when the device is blocked in the reverse direction, namely the gate is biased at 0V, and the drain applies a low potential less than the potential of the source, the potential in the barrier layer can be increased from the N-type drain column 8 to the gate column 7 in a gradual change mode. Therefore, when the device is blocked in the forward direction or the reverse direction, the composite plate structure can realize approximately uniform electric field distribution in the barrier layer between the grid column 7 and the N-type drain column 8, the voltage resistance of the barrier layer between the grid column 7 and the N-type drain column 8 is fully exerted, and the forward breakdown voltage and the reverse breakdown voltage of the device are remarkably improved.
Drawings
Fig. 1 is a structural view of a conventional GaN-based HEMT power switch device;
FIG. 2 is a block diagram of a junction gate-drain power device of the present invention;
FIG. 3 is a cross-sectional view of a gate pillar from left to right in a device of the present invention;
FIG. 4 is a cross-sectional view of an N-type drain pillar from left to right in a device of the present invention;
FIG. 5 is a top view of an array of holes in a device of the present invention;
FIG. 6 is a cross-sectional view of an array of holes from left to right in a device of the present invention;
FIG. 7 is a perspective view of an array of holes in a device of the present invention;
FIG. 8 is a schematic overall flow chart of the present invention for fabricating junction gate-drain power devices;
FIG. 9 is a graph of transfer characteristics simulated for a conventional device and a device of the present invention;
fig. 10 is a graph of simulated breakdown characteristics for a conventional device and a device of the present invention.
Detailed Description
Embodiments and effects of the present invention will be described in further detail below with reference to the accompanying drawings.
Referring to fig. 2, the junction-type gate-drain power device given in this example includes: the structure comprises a substrate 1, a transition layer 2, a barrier layer 3, a gate groove 4, a drain groove 5, a P-type layer 6, a gate column 7, an N-type drain column 8, an N-type row column 9, a P-type row column 10, a source electrode 11, an ohmic contact 12, a drain electrode 13, a table board 14, a gate electrode 15, a passivation layer 16, a composite board 17, a protective layer 18 and an array hole 19. Wherein:
the substrate 1 is made of sapphire, silicon carbide or silicon material;
the transition layer 2 is positioned at the upper part of the substrate 1 and is composed of a plurality of layers of same or different GaN-based wide bandgap semiconductor materials, and the thickness of the transition layer is 1-10 mu m;
the barrier layer 3 is positioned on the upper part of the transition layer 2 and is made of a plurality of layers of same or different GaN-based wide bandgap semiconductor materials, and the thickness of the barrier layer is 4-60 nm;
the gate groove 4 and the drain groove 5 are respectively positioned at two sides in the barrier layer 3, and the length a of the gate groove 41Greater than or equal to 2nm, and depth z thereof1Is less than the thickness of the barrier layer 3, and z1>0; length a of the discharge spout 52Greater than or equal to 2nm and a depth z2，z2>0；
The gate column 7 consists of a P-type layer 6 in the gate groove 4 and a P-type layer 6 on the upper part of the gate groove 4, and the lower end of the P-type layer 6 is completely filled in the gate groove 4; the length of the gate post 7 is more than or equal to 4nm, and the distance between the left edge of the gate post and the left edge of the gate slot 4 is q1The distance between the right edge of the gate groove 4 and the right edge of the gate groove is q2And q is1＝q2The inside of the column is injected with an N-type row column 9, as shown in figure 3;
the doping concentration of the N-type drain column 8 is 1 multiplied by 1016～5×1020cm-3The lower end of the barrier layer is completely filled in the leak groove 5 and is positioned at the thickness h above the barrier layer 3110-1200 nm; the N-type leakage column 8 is internally injected with a P-type row column 10, the P-type row column 10 consists of w rectangular P columns which are equally spaced and have the same size, and w is>0, as in FIG. 4;
the depth of the P-shaped row columns 10 is u1The depth of the leak 5 is z2The thickness of the N-shaped leakage column 8 above the leakage groove 5 is h1，u1<z2+h1(ii) a The P-shaped row columns 10 are composed of w rectangular P columns which are equally spaced and have the same size>0, the width of each rectangular P column is O1The distance between two adjacent rectangular P columns is O2The left edge of the first rectangular P column coincides with the left edge of the N-type leakage column 8, and the distance between the right edges of the w-th rectangular P column and the N-type leakage column 8 is O3The length of the leak groove 5 is a2，O1＝O2＝O3And satisfies (2w) × (O)1)＝a2(ii) a The doping concentration of the P-type row column 10 is 1 × 1016～5×1020cm-3The doping concentration of the N-type drain column 8 is less than or equal to that of the N-type drain column;
said N is-Column 91 and N+The posts 92 are of the same width, x1Two adjacent N+The posts 92 are spaced at a distance x2First N+The left edge of the pillar 92 coincides with the left edge of the gate pillar 7, the mth N+The right edge of pillar 92 is spaced from the right edge of gate pillar 7 by a distance x3The length of the gate groove 4 is a1The distance between the left edge of the grid column 7 and the left edge of the grid groove 4 is q1The distance between the right edge of the gate groove 4 and the right edge of the gate groove is q2，x1＝x2＝x3And satisfies (2m) × x1＝q1+a1+q2；N-The depth of the column 91 is y1，N+The depth of the post 92 is y2The P-type layer 6 is located above the barrier layer 3 and has a thickness h220 to 1000nm, y1>0，y2>0, and y1+y2<h2(ii) a The doping concentration of the P-type layer 6 is 5 x 1016～5×1020cm-3，N+The doping concentration of the pillars 92 is 1 × 1018～5×1020cm-3，N-The doping concentration of the pillar 91 is 1 × 1011～1×1018cm-3And N is-The doping concentrations of the pillars 91 are all less than N+The doping concentration of the pillars 92 and the doping concentration of the P-type layer 6;
array holes 19 are etched in the barrier layer 3 at positions on the left side of the gate column 7 and the right side of the N-type drain column 8, the array holes 19 are formed by f multiplied by g holes with the same size, f is greater than 1, and g is greater than 1;
each hole is composed of an upper rectangular hole column 191 and a lower rectangular pyramid 192, and the distance k between two adjacent holes30.5 to 3 μm, and a boundary distance k between the outermost hole and the source electrode 11 or the ohmic contact 1211-4 μm as shown in FIG. 5;
the upper and lower surfaces of the hole column 191 are square, and the side length k of the square20.5-2 μm, the depth r of the hole pillars 191 is 2-20 nm, and the lower surfaces of the hole pillars 191 are overlapped with the upper surfaces of the rectangular pyramids 192, as shown in FIG. 6;
the depth e of the rectangular pyramid 192 is 1-35 nm, and four sides are the same, as shown in FIG. 7;
the source electrode 11 is located on the left side of the gate column 7, the ohmic contact 12 is located on the right side of the N-type drain column 8, the source electrode 11 and the ohmic contact 12 completely fill the array hole 19, and the length of the array hole is LOAll width being WOA drain electrode 13 is deposited on the upper part of the N-type drain column 8 and the ohmic contact 12, and the length of the drain electrode 13 is a2+LOWidth of WOThe N-type drain pillar 8, the ohmic contact 12 and the drain electrode 13 are electrically connected to each other;
the drain electrode 13 is formed by combining multiple layers of metals, the work function of the metal at the lowest layer is larger than 5eV, and the barrier height formed by the contact of the metal at the lowest layer and each rectangular P column in the P-type row column 10 is smaller than the barrier height formed by the contact of the metal at the lowest layer and the N-type drain column 8;
the mesa 14 is positioned at two edges of the barrier layer 3, and the depth of the mesa is greater than the thickness of the barrier layer 3;
the grid electrode 15 is positioned on the grid column 7, the length of the grid electrode is equal to that of the grid column 7, the grid electrode is formed by combining multiple layers of metals, the work function of the metal at the lowest layer is less than 5eV, and the barrier height formed by the contact of the metal at the lowest layer and each rectangular N column in the N-type row columns 9 is less than the barrier height formed by the contact of the metal at the lowest layer and the P-type layer 6;
the passivation layer 16 is thicker than or equal to 100nm, completely covers the upper parts and the peripheral areas of the gate column 7, the N-type drain column 8, the source electrode 11, the drain electrode 13 and the grid electrode 15, and the passivation layer 16 is made of SiO2、SiN、Al2O3、Sc2O3、HfO2、TiO2Any one of or other insulating dielectric materials;
2N +1 grooves are arranged on the passivation layer 16 between the gate column 7 and the N-type drain column 8, N is larger than or equal to 1, the grooves are the same in size, the depth d of each groove is larger than 0 mu m and smaller than the thickness of the passivation layer 16, and the width a30.1 to 4 μm; the gate column 7 and the N-type drain column 8 use the (N + 1) th groove as a symmetry axis, and on the left side of the symmetry axis, the gate column 7 and the first grooveA distance of b1And 0 μm<b1<(L-a3) The distance between the first groove and the second groove is c1And so on, the distance between the nth groove and the (n + 1) th groove is cnAnd c is and c1<c2<...<cn(ii) a On the right side of the symmetry axis, the distance between the N-type leakage column 8 and the 1 st groove is b2And 0 μm<b2<(L-a3) The distance between the 1 st groove and the 2 nd groove is i1By analogy, the distance between the nth groove and the (n + 1) th groove is in，i1<i2<...<inAnd b is1＝b2,c1＝i1,c2＝i2,…,cn＝in,n≥1；
The composite plate 17 is positioned on the upper part of the passivation layer 16 and is composed of a left modulation plate, a right modulation plate and 2n-1 independent metal blocks with the same size, the lower end of the composite plate is completely filled in 2n +1 grooves, the left modulation plate is electrically connected with the source electrode 11, the right modulation plate is electrically connected with the drain electrode 13, and the independent metal blocks are suspended mutually; the left modulation plate is overlapped with the grid 15 in the horizontal direction, and the right modulation plate is overlapped with the drain 13 in the horizontal direction; the left modulation plate and the right modulation plate are symmetrically distributed in the left-right direction by taking the nth independent metal block as the center, and n is more than or equal to 1. Taking the nth independent metal block as a symmetry axis, and on the left side of the symmetry axis, the distance between the left modulation board and the first independent metal block is S1The distance between the first independent metal block and the second independent metal block is S2In this way, the distance between the n-1 th independent metal block and the n-th independent metal block is Sn，S1<S2<...<Sn(ii) a On the right side of the symmetry axis, the distance between the right modulation plate and the 1 st independent metal block is U1The distance between the 1 st independent metal block and the 2 nd independent metal block is U2In this way, the distance between the n-1 th independent metal block and the n-th independent metal block is Un，U1<U2<...<UnAnd S is1＝U1，S2＝U2，...，Sn＝UnN is more than or equal to 1; left and right modulation boards and each independent metalThe thickness of the blocks is the same, the length t of each independent metal block is 0.5-5 microns, the distance between the right edge of the left modulation plate and the right edge of the grid column 7 is equal to the distance between the left edge of the right modulation plate and the left edge of the N-type drain column 8, and the distance is L.
The protective layer 18 is located in the peripheral region of the passivation layer 16 and the composite plate 17 and is made of SiO2、SiN、Al2O3、Sc2O3、HfO2、TiO2Or other insulating dielectric material.
Referring to fig. 8, the junction-type gate-drain power device fabricated by the present invention is given in the following three examples.
The first embodiment is as follows: making a P-type layer 6 with a thickness h above the barrier layer 3220nm, and the doping concentration of the P-type layer 6 is 5X 1020cm-3The length of the gate column 7 is 4nm, and the doping concentration of the N-type drain column 8 is 5 × 1020cm-3A thickness h above the barrier layer 3110nm and the depth of the P-shaped row column 10 is u1Is 7nm, and has a doping concentration of 5 × 1020cm-3The number w of the rectangular P columns is 1, N-Depth y of the post 911Is 10nm and has a doping concentration of 1 × 1018cm-3，N+Depth y of the post 922Is 8nm and has a doping concentration of 5 × 1020cm-3The number m of the rectangular N columns is 1, the array holes 19 are formed by 2 multiplied by 2 holes with the same size, the number of the grooves is 3, and the number of the independent metal blocks is 1.
1a) A GaN material with the thickness of 30nm is epitaxially grown on a sapphire substrate 1 by using a metal organic chemical vapor deposition technology, and the process conditions are as follows: the temperature is 530 ℃, the pressure is 45Torr, the hydrogen flow is 4400sccm, the ammonia flow is 4400sccm, and the gallium source flow is 22 mu mol/min;
1b) GaN material with the thickness of 0.97 mu m is epitaxially grown on the GaN material by using a metal organic chemical vapor deposition technology to form an undoped transition layer 2, and the process conditions are as follows: the temperature was 960 deg.C, the pressure was 45Torr, the hydrogen flow was 4400sccm, the ammonia flow was 4400sccm, and the gallium source flow was 120. mu. mol/min.
Depositing undoped Al with a thickness of 4nm and an aluminum composition of 0.3 on the GaN transition layer 2 by using a metal organic chemical vapor deposition technique0.3Ga0.7The process conditions of the N barrier layer 3 are as follows: the temperature was 980 ℃, the pressure was 45Torr, the hydrogen flow was 4400sccm, the ammonia flow was 4400sccm, the gallium source flow was 35. mu. mol/min, and the aluminum source flow was 7. mu. mol/min.
And 3, manufacturing a gate groove 4 and a drain groove 5 on the barrier layer 3, as shown in fig. 8 c.
3a) In Al0.3Ga0.7A mask is firstly made on the N barrier layer 3, the mask is utilized to etch in the barrier layer 3 by using a reactive ion etching technology to form a gate groove 4, and the etching depth z of the gate groove 41Is 3nm and a length a1Is 2 nm;
the process conditions adopted for etching the gate groove 4 are as follows: cl2The flow rate is 15sccm, the pressure is 10mTorr, and the power is 50W.
3b) In Al0.3Ga0.7Making a mask on the N barrier layer 3 and the gate trench 4 for the second time, etching in the barrier layer 3 by using the mask and reactive ion etching technology to form a drain trench 5, wherein the etching depth z of the drain trench 52Is 3nm and a length a2Is 2 nm;
the process conditions adopted for etching the leakage groove 5 are as follows: cl2The flow rate is 15sccm, the pressure is 10mTorr, and the power is 50W.
And 4, extending a P-type layer 6 on the barrier layer 3, as shown in figure 8 d.
Epitaxy of a thickness h on the barrier layer 3 using molecular beam epitaxy220nm, and 5 × 10 doping concentration20cm-3And filling the gate trench 4 and the drain trench 5to form a P-type layer 6.
The process conditions adopted by molecular beam epitaxy are as follows: vacuum degree of 1.0X 10 or less-10mbar, radio frequency power of 400W, and N as reactant2High purity Ga source。
And 5, manufacturing a gate column 7 and an N-type drain column 8 as shown in fig. 8 e.
5a) Making a mask on the P-type layer 6 for the third time, etching the two sides of the P-type layer 6 by using a reactive ion etching technology by using the mask, etching the outside of the leak groove 5 until the upper surface of the barrier layer 3, etching the inside of the leak groove 5to the bottom thereof to form a gate post 7 with the length of 4nm, and forming a gap q between the left edge of the gate post 7 and the left edge of the gate groove 411nm, the distance q between the right edge of the gate trench and the right edge of the gate trench 42Is 1nm, and the etching adopts the following process conditions: cl2The flow rate is 15sccm, the pressure is 10mTorr, and the power is 100W.
5b) Making a mask on the barrier layer 3 and the gate post 7 for the fourth time, and using the mask to epitaxially grow N-type GaN semiconductor material in the drain trench 5 by selective epitaxial growth technique to form a thickness h above the barrier layer 3110nm, 2nm in length, and 5 × 10 in doping concentration20cm-3The process conditions adopted by the selective epitaxy are as follows: vacuum degree of 1.0X 10 or less-10mbar, radio frequency power of 400W, and N as reactant2And a high purity Ga source.
And 6, manufacturing the N-type row columns 9 and the P-type row columns 10, as shown in fig. 8 f.
6a) Making a mask on the barrier layer 3, the gate column 7 and the N-type drain column 8 for the fifth time, and doping the P-type layer 6 with a doping concentration of 1 × 10 by using the mask and using ion implantation technology18cm-3Is formed to a depth y1+y21N of 18nm and 2nm width-Column 91, the process conditions used for ion implantation were: the implanted N-type impurity is Si.
6b) Continuing to use the mask of 6a), doping the P-type layer 6 with a concentration of 5 × 10 by ion implantation20cm-3Is formed to a depth y21N of 8nm and 2nm width+Column 92, these 1N+Column 92 and 1N-The columns 91 together form an N-type rowed column 9, and the ion implantation adopts the following process conditions: the implanted N-type impurity is Si.
6c) A mask is formed on the barrier layer 3, the gate post 7 and the N-type drain post 8 for the sixth time, and ion implantation is performed using the maskThe doping concentration in the N-type drain column 8 is 5 multiplied by 1020cm-3P-type impurity of (d), formed to a depth u 11 rectangular P column with the width of 1nm and the width of 7nm, wherein the rectangular P column forms a P-type row column 10, and the ion implantation adopts the following process conditions: the implanted P-type impurity is Mg.
Step 7, making array holes 19, as shown in FIG. 8 g.
7a) Al at a thickness of 4nm0.3Ga0.7A mask is made on the N barrier layer 3, the gate column 7 and the N-type drain column 8 for the seventh time, and the pattern of the mask is formed by 2 multiplied by 2 side lengths k2Is an array of square holes of 0.5 μm, the spacing k of two adjacent holes30.5 μm, the boundary spacing k of the outermost peripheral hole to the source electrode 11 or the ohmic contact 121Is 1 μm; using the mask to etch Al by reactive ion etching0.3Ga0.72 x 2 cuboid hole columns 191 are etched on the N barrier layer 3, wherein the depth r of each hole column 191 is 2 nm.
The process conditions adopted for etching the hole columns 191 are as follows: cl2/BCl3The flow ratio was 3:1, the pressure was 30mTorr, and the power was 150W.
7b) Al at a thickness of 4nm0.3Ga0.7The eighth time of making a mask on the N barrier layer 3, the gate column 7 and the N-type drain column 8, etching and making the same rectangular pyramid 192 in the 2 x 2 cuboid hole columns 191 with the same size formed in the step 7a) by using the mask by adopting a reactive ion etching technology, wherein the 2 x 2 cuboid hole columns 191 with the same size and the rectangular pyramid 192 at the lower parts form the array holes 19 together. The upper surfaces of the rectangular pyramids coincide with the lower surface of the hole column 191, the depth e of the rectangular pyramids 191 is 1nm, the four sides are the same, and Al0.3Ga0.7The thickness of the N barrier layer 3 after etching was 1 nm.
The process conditions adopted for etching the rectangular pyramid 192 are as follows: BCl3The flow rate is 60sccm, the pressure is 25mTorr, and the power is 150W.
And 8, manufacturing a source electrode 11 and a drain electrode 13, as shown in fig. 8 h.
8a) And manufacturing masks on the barrier layers 3, the gate columns 7 and the upper parts of the N-type drain columns 8 for the ninth time, depositing metal on the barrier layers 3 on the left side and the right side by using an electron beam evaporation technology by using the masks, and completely filling the array holes 19, wherein the metal adopts Gd.
The process conditions adopted for depositing the metal are as follows: high purity Gd source with vacuum degree less than 1.8 x 10-3Pa, power of 400W, evaporation rate of less than
；
8b) Continuing to deposit metal again by electron beam evaporation using the mask of 8a), and depositing N2And carrying out rapid thermal annealing in the atmosphere to manufacture the source electrode 11 and the ohmic contact 12, wherein the deposited metal is a Ti/Al/Ni/Au metal combination, namely Ti, Al, Ni and Au are respectively arranged from bottom to top, and the thickness of the deposited metal is 0.018 mu m/0.135 mu m/0.046 mu m/0.052 mu m.
The process conditions adopted for depositing the metal are as follows: vacuum degree less than 1.8X 10-3Pa, power of 400W, evaporation rate of less than
(ii) a The process conditions adopted by the rapid thermal annealing are as follows: the temperature was 850 ℃ and the time was 35 s.
8c) A mask is formed tenth time on the barrier layer 3, the gate column 7, the N-type drain column 8, the source electrode 11 and the upper portion of the ohmic contact 12, a metal, which is Au/Ti/Al/Pt having a thickness of 0.018/0.135/0.046/0.052 μm, is deposited again by the electron beam evaporation technique, and the drain electrode 13 is formed, the N-type drain column 8, the ohmic contact 12 and the drain electrode 13 being electrically connected to each other.
The process conditions adopted for depositing the metal are as follows: vacuum degree less than 1.8X 10-3Pa, power of 200W, evaporation rate of less than
；
And 9, etching the barrier layer 3 on the left side of the source electrode 11 and the right side of the drain electrode 13 to manufacture a mesa 14, as shown in fig. 8 i.
And manufacturing masks on the barrier layer 3, the gate column 7, the source electrode 11 and the drain electrode 13 for the eleventh time, and etching the barrier layer 3 on the left side of the source electrode 11 and the right side of the drain electrode 13 by using the masks by using a reactive ion etching technology to form a mesa 14, wherein the etching depth is 80 nm.
The etching adopts the following process conditions: cl2The flow rate is 15sccm, the pressure is 10mTorr, and the power is 100W.
Making a mask on the barrier layer 3, the gate post 7, the source electrode 11, the drain electrode 13 and the upper part of the mesa 14 for the twelfth time, depositing metal on the gate post 7 by using an electron beam evaporation technology by using the mask to make a gate electrode 15, the lower edge of the gate electrode 15 and all N+The upper edges of the pillars 92 are coincident and have a length equal to the length of the gate pillar 7, wherein the deposited metal is a Gd/Au metal combination, i.e., Gd is present in the lower layer and Au is present in the upper layer, and the thickness is 0.045/0.20 μm.
The process conditions adopted for depositing the metal are as follows: vacuum degree less than 1.8X 10-3Pa, power of 200W, evaporation rate of less than
。
Step 11, a passivation layer 16 is formed, as shown in fig. 8 k.
Depositing SiO with a thickness of 100nm on the upper parts of the gate post 7, the source electrode 11, the drain electrode 13 and the gate electrode 15 and the peripheral area thereof by using a plasma enhanced chemical vapor deposition technique2A passivation layer 16.
The process conditions for depositing the passivation layer 14 are as follows: n is a radical of2O flow rate of 850sccm, SiH4The flow rate was 200sccm, the temperature was 250 ℃, the RF power was 20W, and the pressure was 1100 mT.
Step 12, make 3 grooves, as shown in fig. 8 l.
Making a mask on the passivation layer 16 for the thirteenth time, and etching the passivation layer 16 between the gate pillar 7 and the N-type drain pillar 8 by using the mask and a reactive ion etching technique to make 3 grooves with the same depth and width, wherein the width a of each groove30.1 μm and a depth d of 50 nm. The gate column 7 and the N-type drain column 8 use the 2 nd groove as a symmetry axis, and the distance b between the gate column 7 and the first groove is arranged on the left side of the symmetry axis10.5 μm, the distance c between the first and second grooves10.5 μm; on the right side of the symmetry axis, an N-type leakage column 8 and a 1 stSpacing b of grooves20.5 μm, the distance i between the 1 st and the 2 nd grooves1And was 0.5 μm.
The etching adopts the following process conditions: CF (compact flash)4The flow rate was 45sccm, O2The flow rate is 5sccm, the pressure is 15mTorr, and the power is 250W.
And step 13, manufacturing a left modulation board, 1 independent metal block and a right modulation board, as shown in fig. 8 m.
And manufacturing a mask on the passivation layer 16 and the upper part of the 3 grooves for the fourteenth time, depositing metal on the passivation layer 16 between the gate column 7 and the N-type drain column 8 in the 3 grooves by using an electron beam evaporation technology by using the mask to manufacture a left modulation plate, 1 independent metal block and a right modulation plate, electrically connecting the left modulation plate with the source electrode 11, electrically connecting the right modulation plate with the drain electrode 13, suspending the independent metal blocks, overlapping the left modulation plate and the gate electrode 15 in the horizontal direction, overlapping the right modulation plate and the drain electrode 13 in the horizontal direction, and symmetrically distributing the left modulation plate and the right modulation plate in the left-right direction by taking the 1 st independent metal block as the center to form a composite plate 17, wherein the deposited metal is a Ti/Au metal combination, namely the lower layer is Ti, the upper layer is Au, and the thickness of the composite plate is 0.1 mu m/0.05 mu m. Wherein the deposited metal completely fills the 3 recesses, the spacing S of the left modulator plate from its first independent metal block10.1 μm, the distance U between the right modulation plate and the 1 st independent metal block10.1 μm, the length t of the independent metal block is 0.5 μm, the distance between the right edge of the left modulation plate and the right edge of the gate pillar 7 is equal to the distance between the left edge of the right modulation plate and the left edge of the N-type drain pillar 8, and the distance L is 0.8 μm.
The process conditions adopted for depositing the metal are as follows: vacuum degree less than 1.8X 10-3Pa, power of 200W, evaporation rate of less than
。
Step 14. depositing SiO in the peripheral region of the passivation layer 16 and the composite plate 172A protective layer 18 is made, as shown in fig. 8 n.
Deposition of SiO in the peripheral region of passivation layer 16 and composite plate 17 using plasma enhanced chemical vapor deposition techniques2To make a protective layer 18And the thickness is 0.56 μm, thereby completing the manufacture of the whole device.
The process conditions adopted for depositing the protective layer are as follows: n is a radical of2O flow rate of 850sccm, SiH4The flow rate was 200sccm, the temperature was 250 deg.C, the RF power was 20W, and the pressure was 1100 mTorr.
Example two: making a P-type layer 6 with a thickness h above the barrier layer 32200nm, and the doping concentration of the P-type layer 6 is 1X 1019cm-3The length of the gate column 7 is 1800nm, and the doping concentration of the N-type drain column 8 is 5 × 1019cm-3A thickness h above the barrier layer 31200nm, and the depth of the P-shaped row column 10 is u1Is 80nm, and has a doping concentration of 1 × 1019cm-3The number w of the rectangular P columns is 3, N-Depth y of the post 911Is 100nm, and has a doping concentration of 1 × 1017cm-3，N+Depth y of the post 922Is 80nm, and has a doping concentration of 5 × 1019cm-3The number m of the rectangular N columns is 3, the array holes 19 are formed by 5 multiplied by 5 holes with the same size, the number of the grooves is 5, and the number of the independent metal blocks is 3.
Step one, a transition layer 2 is made by extending AlN and GaN materials from bottom to top on a silicon carbide substrate 1, as shown in figure 8 a.
1.1) extending an undoped AlN material with the thickness of 100nm on a silicon carbide substrate 1 by using a metal organic chemical vapor deposition technology under the process conditions that the temperature is 1000 ℃, the pressure is 45Torr, the hydrogen flow is 4600sccm, the ammonia flow is 4600sccm and the aluminum source flow is 5 mu mol/min;
1.2) using a metal organic chemical vapor deposition technology to epitaxially grow a GaN material with the thickness of 4.9 mu m on the AlN material under the process conditions that the temperature is 1000 ℃, the pressure is 45Torr, the hydrogen flow is 4600sccm, the ammonia flow is 4600sccm and the gallium source flow is 120 mu mol/min, and thus the manufacture of the transition layer 2 is completed.
Step two, depositing undoped Al on the GaN transition layer 20.2Ga0.8N produces the barrier layer 3 as shown in fig. 8 b.
Using metal organic chemical vapour deposition techniquesUnder the process conditions that the temperature is 980 ℃, the pressure is 45Torr, the hydrogen flow is 4500sccm, the ammonia flow is 4500sccm, the gallium source flow is 36 mu mol/min and the aluminum source flow is 7 mu mol/min, undoped Al with the thickness of 20nm and the aluminum component of 0.2 is deposited on the GaN transition layer 20.2Ga0.8An N barrier layer 3.
And step three, manufacturing a gate groove 4 and a drain groove 5 on the barrier layer 3, as shown in fig. 8 c.
3.1) in Al0.2Ga0.8Making mask on N barrier layer 3 for the first time, and etching in Cl by reactive ion etching technology2Etching the barrier layer 3 under the process conditions of 15sccm flow, 10mTorr pressure and 50W power to form a gate trench 4, wherein the etching depth z of the gate trench 41Is 14nm and a length a11400 nm;
3.2) in Al0.2Ga0.8Making mask on the N barrier layer 3 and the gate groove 4 for the second time, and performing reactive ion etching on Cl2Etching the barrier layer 3 under the process conditions of 15sccm flow, 10mTorr pressure and 50W power to form an etching depth z2Is 22nm and has a length a2A 1200nm drain 5.
Step four, a P-type layer 6 is epitaxially grown on the barrier layer 3, as shown in fig. 8 d.
Using molecular beam epitaxy technique under vacuum degree of 1.0 × 10-10mbar, radio frequency power of 450W, and N as reactant2Epitaxial thickness h on the barrier layer 3 under the process condition of high-purity Ga source2Is 200nm, and has a doping concentration of 1 × 1019cm-3And filling the gate trench 4 and the drain trench 5to form a P-type layer 6.
And step five, manufacturing the gate column 7 and the N-type drain column 8 as shown in fig. 8 e.
5.1) making a mask on the P-type layer 6 for the third time, and performing reactive ion etching on Cl2Etching both sides of the P-type layer 6 under the process conditions of 15sccm flow, 10mTorr pressure and 100W power, etching the outside of the leak groove 5to the upper surface of the barrier layer 3, etching the inside of the leak groove 5to the bottom thereof to form a gate post 7 with the length of 1800m, and forming a distance q between the left edge of the gate post 7 and the left edge of the gate groove 41Is a molecular weight distribution of 200nm,the distance q between the right edge of the gate groove 4 and the right edge of the gate groove2Is 200 nm;
5.2) making a mask on the barrier layer 3 and the gate post 7 for the fourth time, and using selective epitaxial growth technique under the condition of vacuum degree less than or equal to 1.0 × 10-10mbar, radio frequency power of 450W, and N as reactant2And under the process condition of high-purity Ga source, extending N-type GaN semiconductor material to form a thickness h above the barrier layer 31200nm, 1200nm in length, and 5 × 10 in doping concentration19cm-3The N-type drain pillar 8.
And step six, manufacturing the N-type row columns 9 and the P-type row columns 10, as shown in fig. 8 f.
6.1) making a mask on the barrier layer 3, the gate column 7 and the N-type drain column 8 for the fifth time, and doping 1 × 10 concentration into the P-type layer 6 by using an ion implantation technology under the process condition of implanting Si as an N-type impurity17cm-3Is formed to a depth y1+y23N at 180nm and 300nm in width-A post 91;
6.2) continuing to use the mask in 6.1), and doping the P-type layer 6 with a concentration of 5 × 10 under the process condition of implanting Si as N-type impurity by using ion implantation technology19cm-3Is formed to a depth y23N of 80nm and 300nm width+Column 92, 3N+Column 92 and 3N-The pillars 91 together form an N-type bent 9.
6.3) making a mask on the barrier layer 3, the gate column 7 and the N-type drain column 8 for the sixth time, and doping the N-type drain column 8 with the concentration of 1 × 10 under the process condition of injecting P-type impurities into Mg by using an ion implantation technology19cm-3P-type impurity of (d), formed to a depth u1And 3 rectangular P pillars of 80nm and 200nm in width, the 3 rectangular P pillars forming the P-type row pillars 10.
Step seven, manufacturing array holes 19, as shown in fig. 8 g.
7.1) Al at a thickness of 20nm0.2Ga0.8A mask is made on the N barrier layer 3, the gate column 7 and the N-type drain column 8 for the seventh time, and the mask pattern is formed by 5 multiplied by 5 side lengths k2Is an array of square holes of 1 μm, the spacing k between two adjacent holes 31 μm, outermost peripheral poresBoundary spacing k from source 11 or ohmic contact 121Is 2 μm; using the mask to perform a reactive ion etching process on Cl2/BCl3The flow ratio is 3:1, the pressure is 30mTorr and the power is 150W under the process conditions of Al0.2Ga0.8Etching and manufacturing 5 multiplied by 5 cuboid hole columns 191 on the N barrier layer 3, wherein the depth r of each hole column 191 is 8 nm;
7.2) Al at a thickness of 20nm0.2Ga0.8Making masks on the N barrier layer 3, the gate column 7 and the N-type drain column 8 for the eighth time, and using the masks to etch 5 × 5 cuboid hole columns 191 with the same size formed in 7.1) in BCl by adopting a reactive ion etching technology3Under the process conditions of the flow rate of 60sccm, the pressure of 25mTorr and the power of 150W, the same rectangular pyramid 192 is etched, and the 5 × 5 rectangular hole columns 191 with the same size and the rectangular pyramid 192 at the lower parts form the array holes 19 together. The upper surfaces of the rectangular pyramids coincide with the lower surface of the hole column 191, the depth e of the rectangular pyramids 191 is 8nm, the four sides are the same, and Al0.2Ga0.8The thickness of the N barrier layer 3 after etching was 4 nm.
And step eight, manufacturing a source electrode 11 and a drain electrode 13, as shown in fig. 8 h.
8.1) making a mask on the barrier layer 3, the gate column 7 and the upper part of the N-type drain column 8 for the ninth time, and using the mask to perform electron beam evaporation on the barrier layer 3 on the left and right sides to form a high-purity Zr source with a vacuum degree of less than 1.8 multiplied by 10-3Pa, power of 400W, evaporation rate of less than
Under the process conditions of (3), depositing metal Zr, and completely filling the array holes 19;
8.2) continuing to use the mask in 8.1), and adopting the electron beam evaporation technology again to ensure that the vacuum degree is less than 1.8 multiplied by 10- 3Pa, power of 400W, evaporation rate of less than
Under the process conditions of (1) depositing a metal and under the process conditions of a temperature of 850 ℃ and a time of 35s under N2Performing rapid thermal annealing in the atmosphere to manufacture the source electrode 11And ohmic contact 12, wherein the deposited metal is a combination of Ti/Al/Mo/Au metals, i.e., Ti, Al, Mo and Au are respectively from bottom to top, and the thickness thereof is 0.015 μm/0.132 μm/0.048 μm/0.056 μm;
8.3) making mask on the barrier layer 3, the gate column 7, the N-type drain column 8, the source 11 and the ohmic contact 12, and evaporating by electron beam under vacuum degree of less than 1.8 × 10-3Pa, power of 600W, evaporation rate of less than
Under the process conditions of (1), a combination of Ni/Al/Mo/Au metals, namely Ni, Al, Mo and Au from bottom to top are deposited, the thickness of the combination is 0.015 mu m/0.132 mu m/0.048 mu m/0.056 mu m, the drain electrode 13 is formed, and the N-type drain pillar 8, the ohmic contact 12 and the drain electrode 13 are electrically connected with each other.
And step nine, etching the barrier layer 3 on the left side of the source electrode 11 and the right side of the drain electrode 13 to manufacture a mesa 14, as shown in fig. 8 i.
Making a mask on the barrier layer 3, the gate post 7, the source electrode 11 and the drain electrode 13 for the eleventh time, and using the mask to perform reactive ion etching on the barrier layer on the left side of the source electrode 11 and the right side of the drain electrode 13 to form Cl2The mesa 14 is formed by etching vertically down to 200nm at a flow rate of 15sccm, a pressure of 10mTorr, and a power of 100W.
Step ten, manufacturing the grid 15, as shown in fig. 8 j.
Making a mask on the barrier layer 3, the gate column 7, the source electrode 11, the drain electrode 13 and the upper part of the mesa 14 for the twelfth time, and using the mask to perform electron beam evaporation on the gate column 7 under the condition that the vacuum degree is less than 1.8 multiplied by 10-3Pa, power of 600W, evaporation rate of less than
Under the process conditions of (1), depositing metal, and manufacturing the gate electrode 15, the lower edge of the gate electrode 15 and all N+The upper edges of the pillars 92 are all coincident and have a length equal to the length of the gate pillar 7, wherein the metal deposited is a Zr/Pt metal combination, i.e. Zr for the lower layer and Pt for the upper layer, and has a thickness of 0.18/0.32 μm.
Step eleven. passivation layer 16 is fabricated, as in fig. 8 k.
In the upper parts of the gate post 7, the source electrode 11, the drain electrode 13 and the gate electrode 15 and the peripheral area thereof, adopting the plasma enhanced chemical vapor deposition technique to deposit NH3The flow rate was 2.5sccm, N2Flow rate 950sccm, SiH4The SiN passivation layer 16 is deposited at a thickness of 300nm under process conditions of a flow rate of 250sccm, a temperature of 300 deg.c, a RF power of 50W and a pressure of 950 mT.
Step twelve, 5 grooves are made, as shown in fig. 8 l.
A mask is formed on the passivation layer 16 for a thirteenth time, and the mask is used to etch the CF in the passivation layer 16 between the gate pillar 7 and the N-type drain pillar 8 by using a reactive ion etching technique4The flow rate was 45sccm, O2Etching 5 grooves with the same depth and width under the process conditions of 5sccm flow, 15mT pressure and 250W power, wherein the width a of each groove30.5 μm and a depth d of 250 nm. The gate column 7 and the N-type drain column 8 use the 3 rd groove as a symmetry axis, and the distance b between the gate column 7 and the first groove is arranged on the left side of the symmetry axis 11 μm, the first and second grooves having a spacing of c1The distance between the second groove and the third groove is c2And c is and c1<c2(ii) a On the right side of the symmetry axis, the distance b between the N-type leakage column 8 and the 1 st groove2Is 1 μm, and the interval between the 1 st groove and the 2 nd groove is i1The distance between the 2 nd groove and the 3 rd groove is i2And i is1<i2，c1＝i1,c2＝i2。
And thirteen, manufacturing a left modulation plate, 3 independent metal blocks and a right modulation plate, as shown in FIG. 8 m.
Making a mask on the passivation layer 16 and the upper parts of the 5 grooves for the fourteenth time, and using the mask to perform electron beam evaporation on the passivation layer 16 in the 5 grooves and between the gate column 7 and the N-type drain column 8 under the condition that the vacuum degree is less than 1.8 multiplied by 10-3Pa, power of 600W, evaporation rate of less than
Under the process conditions of (1), the left modulation board, 3 independent metal blocks and the right modulation board are made of deposited metalAnd the left modulation plate is electrically connected with the source electrode 11, the right modulation plate is electrically connected with the drain electrode 13, the 3 independent metal blocks are suspended, the left modulation plate and the right modulation plate are symmetrically distributed in a left-right mode by taking the 3 rd independent metal block as the center to form a composite plate 17, the deposited metal is a Ti/Au metal combination, namely the lower layer is Ti, the upper layer is Au, and the thickness of the composite plate is 0.2 mu m/0.11 mu m. Wherein the deposited metal is to completely fill 5 grooves, the 2 nd independent metal block is taken as a symmetry axis, and the left side of the symmetry axis is the space S between the left modulation board and the first independent metal block10.26 μm, the spacing S of the first independent metal block and the second independent metal block20.52 μm; distance U between right modulation board and 1 st independent metal block10.26 μm, the distance U between the 1 st and 2 nd independent metal blocks20.52 μm, the length t of the independent metal block is 2 μm, the distance between the right edge of the left modulation plate and the right edge of the gate pillar 7 is equal to the distance between the left edge of the right modulation plate and the left edge of the N-type drain pillar 8, and the distance L is 2.25 μm.
Fourteen, depositing SiO on the peripheral area of the passivation layer 16 and the composite board 172A protective layer 18 is made, as shown in fig. 8 n.
Using plasma enhanced chemical vapor deposition techniques on N2O flow rate of 850sccm, SiH4SiO is deposited on the peripheral area of the passivation layer 16 and the composite board 17 under the process conditions of the flow of 200sccm, the temperature of 250 ℃, the RF power of 50W and the pressure of 1100mTorr2To produce a protective layer 18 having a thickness of 0.7 μm, thereby completing the production of the entire device.
Example three: making a P-type layer 6 with a thickness h above the barrier layer 32400nm, and the doping concentration of the P-type layer 6 is 5X 1016cm-3The length of the gate column 7 is 5000nm, and the doping concentration of the N-type drain column 8 is 1 × 1016cm-3A thickness h above the barrier layer 31600nm and the depth of the P-shaped row column 10 is u1Is 550nm and has a doping concentration of 1 × 1016cm-3The number w of the rectangular P columns is 5, N-Depth y of the post 91150nm, and a doping concentration of 1 × 1011cm-3，N+Post 92Depth y of2Is 300nm and has a doping concentration of 1 × 1018cm-3The number m of the rectangular N columns is 5, the array holes 19 are formed by 10 multiplied by 10 holes with the same size, the number of the grooves is 7, and the number of the independent metal blocks is 5.
Step A. epitaxial growth of AlN and GaN materials on a silicon substrate 1 from bottom to top to form a transition layer 2, as shown in FIG. 8 a.
Firstly, a metal organic chemical vapor deposition technology is used for extending AlN material with the thickness of 400nm on a silicon substrate 1, and the process conditions are as follows: the temperature is 800 ℃, the pressure is 40Torr, the hydrogen flow is 4000sccm, the ammonia flow is 4000sccm, and the aluminum source flow is 25 mu mol/min;
then, a GaN material with the thickness of 9.6 μm is epitaxially grown on the AlN material by using a metal organic chemical vapor deposition technology, and the manufacture of the transition layer 2 is completed, wherein the process conditions are as follows: the temperature is 980 ℃, the pressure is 45Torr, the hydrogen flow is 4000sccm, the ammonia flow is 4000sccm, and the gallium source flow is 120 mu mol/min.
Step B, depositing undoped Al on the GaN transition layer 20.1Ga0.9N produces the barrier layer 3 as shown in fig. 8 b.
Depositing undoped Al with a thickness of 60nm and an aluminum composition of 0.1 on the GaN transition layer 2 by using a metal-organic chemical vapor deposition technique0.1Ga0.9An N barrier layer 3; the deposition process conditions are as follows: the temperature was 980 ℃, the pressure was 45Torr, the hydrogen flow was 4600sccm, the ammonia flow was 4600sccm, the gallium source flow was 37. mu. mol/min, and the aluminum source flow was 7. mu. mol/min.
And step C, manufacturing a gate groove 4 and a drain groove 5 on the barrier layer 3, as shown in figure 8 c.
First, in Al0.1Ga0.9A mask is first produced on the N barrier layer 3, and the depth z is etched in the barrier layer 3 by using the mask and a reactive ion etching technology1Is 55nm and has a length a1 A gate trench 4 of 3000 nm; the process conditions adopted for etching the gate groove 4 are as follows: cl2The flow rate is 15sccm, the pressure is 10mTorr, and the power is 50W.
Then, in Al0.1Ga0.9On the N barrier layer 3A second mask is produced, by means of which the barrier layer 3 is etched to a depth z using reactive ion etching2Is 60nm and has a length a2A leak 5 of 1800 nm; the process conditions adopted for etching the leakage groove 5 are as follows: cl2The flow rate is 15sccm, the pressure is 10mTorr, and the power is 50W.
Step d. epitaxial P-type layer 6 on barrier layer 3, fig. 8 d.
Epitaxy of a thickness h on the barrier layer 3 using molecular beam epitaxy2Is 400nm, and has a doping concentration of 5 × 1016cm-3Filling the gate groove 4 and the drain groove 5 with the P-type GaN semiconductor material to form a P-type layer 6;
the process conditions adopted by molecular beam epitaxy are as follows: vacuum degree of 1.0X 10 or less-10mbar, radio frequency power of 350W, and N as reactant2And a high purity Ga source.
And E, manufacturing the gate column 7 and the N-type drain column 8 as shown in figure 8 e.
Firstly, a mask is made on a P-type layer 6 for the third time, the mask is used for etching two sides of the P-type layer 6 by using a reactive ion etching technology, the outside of a leak groove 5 is etched until the upper surface of a barrier layer 3, the inside of the leak groove 5 is etched to the bottom thereof to form a gate post 7 with the length of 5000nm, and the distance q between the left edge of the gate post 7 and the left edge of a gate groove 4 is11000nm, the distance q between the right edge and the right edge of the gate trench 42Is 1000nm, and the etching adopts the following process conditions: cl2The flow is 15sccm, the pressure is 10mTorr, and the power is 100W;
then, a mask is formed on the barrier layer 3 and the gate post 7 for the fourth time, and an N-type GaN semiconductor material is epitaxially grown in the drain trench 5 using a selective epitaxial growth technique using the mask to form a thickness h1600nm, 1800nm in length, 1X 10 in doping concentration16cm-3The process conditions adopted by the selective epitaxy are as follows: vacuum degree of 1.0X 10 or less-10mbar, radio frequency power of 350W, and N as reactant2And a high purity Ga source.
And F, manufacturing the N-type row columns 9 and the P-type row columns 10, as shown in fig. 8 f.
First, a mask is formed on the barrier layer 3, the gate pillar 7 and the N-type drain pillar 8 for the fifth timeThe mask is used to dope the P-type layer 6 with a concentration of 1X 10 by ion implantation11cm-3Is formed to a depth y1+y25N of 350nm and 500nm width-Column 91, the process conditions used for ion implantation were: injecting N-type impurities as Si;
next, the mask manufactured for the fifth time is continuously used, and the doping concentration of the P-type layer 6 is 1 × 10 by using the mask and the ion implantation technology18cm-3Is formed to a depth y25N of 300nm and 500nm width+Column 92, these 5N+Column 92 and 5N-The columns 91 together form an N-type rowed column 9, and the ion implantation adopts the following process conditions: injecting N-type impurities as S;
then, a mask is formed on the barrier layer 3, the gate column 7 and the N-type drain column 8 for the sixth time, and the N-type drain column 8 is doped with the mask to a concentration of 1 × 10 by using an ion implantation technique16cm-3P-type impurity of (d), formed to a depth u15 rectangular P columns with the width of 180nm and the width of 550nm form a P-type row column 10, and the ion implantation adopts the following process conditions: the implanted P-type impurity is Mg.
Step g. make array holes 19, as in fig. 8 g.
First, in the case of Al having a thickness of 60nm0.1Ga0.9A mask is made on the N barrier layer 3, the gate column 7 and the N-type drain column 8 for the seventh time, and the pattern of the mask is formed by 10 multiplied by 10 side lengths k2Is an array of square holes of 2 μm with a spacing k between two adjacent holes33 μm, boundary spacing k of the outermost peripheral hole to the source electrode 11 or ohmic contact 121Is 4 μm; using the mask to etch Al by reactive ion etching0.1Ga0.9Etching and manufacturing 10 multiplied by 10 cuboid hole columns 191 on the N barrier layer 3, wherein the depth r of each hole column 191 is 20nm, and the technical conditions adopted for etching the hole columns 191 are as follows: cl2/BCl3The flow ratio is 3:1, the pressure is 30mTorr, and the power is 150W;
then, in the presence of Al having a thickness of 60nm0.1Ga0.9An eighth mask is formed on the N-barrier layer 3, the gate pillar 7 and the N-type drain pillar 8, and the 10 × 10 phases formed as described above are formed using the masksThe rectangular pyramid 192 is etched and manufactured in the same manner as the rectangular hole columns 191 by adopting the reactive ion etching technology, and the rectangular hole columns 191 with the same size of 10 multiplied by 10 and the rectangular pyramid 192 at the lower parts of the rectangular hole columns form array holes 19 together. The upper surfaces of the rectangular pyramids coincide with the lower surface of the hole column 191, the depth e of the rectangular pyramids 191 is 35nm, the four sides are the same, and Al0.1Ga0.9The thickness of the N barrier layer 3 after etching was 5 nm. The adopted process conditions for etching the rectangular pyramid 192 are as follows: BCl3The flow rate is 60sccm, the pressure is 25mTorr, and the power is 150W.
Step h. make source 11 and drain 13, as in fig. 8 h.
First, a mask is formed on the barrier layer 3, the gate column 7, and the upper portion of the N-type drain column 8 for the ninth time, and Ta metal is deposited on the barrier layer 3 on the left and right sides using an electron beam evaporation technique using the mask, and the array holes 19 are completely filled. The process conditions adopted for depositing the metal are as follows: high purity Ta source, vacuum degree less than 1.8X 10-3Pa, power of 400W, evaporation rate of less than
；
Secondly, continuously utilizing the mask manufactured in the ninth time, depositing metal again by adopting the electron beam evaporation technology, and depositing N2And carrying out rapid thermal annealing in the atmosphere to manufacture the source electrode 11 and the ohmic contact 12, wherein the deposited metal is a Ti/Al/Ti/Au metal combination, namely Ti, Al, Ti and Au are respectively from bottom to top, and the thicknesses of the metals are 0.012 mu m/0.138 mu m/0.041 mu m/0.059 mu m in sequence. The process conditions adopted for depositing the metal are as follows: vacuum degree less than 1.8X 10-3Pa, power of 1000W, evaporation rate less than
(ii) a The process conditions adopted by the rapid thermal annealing are as follows: the temperature is 850 ℃ and the time is 35 s;
then, a mask is made on the barrier layer 3, the grid column 7, the N-type drain column 8, the source electrode 11 and the upper part of the ohmic contact 12 for the tenth time, the mask is used for depositing metal by adopting the electron beam evaporation technology again, the metal adopts the Pd/Ni/Co/Ni metal combination, namely Pd, Ni, Co and Ni from bottom to top respectively, and the metal comprises Pd, Ni, Co and Ni from bottom to topThe drain electrode 13 is formed to have a thickness of 0.012/0.138/0.041/0.059/m, and the N-type drain pillar 8, the ohmic contact 12 and the drain electrode 13 are electrically connected to each other. The process conditions adopted for depositing the metal are as follows: vacuum degree less than 1.8X 10-3Pa, power of 1000W, evaporation rate less than
。
Step i, etching is performed on the barrier layer 3 on the left side of the source 11 and the right side of the drain 13 to form a mesa 14, as shown in fig. 8 i.
Making masks on the barrier layer 3, the gate column 7, the source electrode 11 and the drain electrode 13 for the eleventh time, and etching the barrier layer 3 on the left side of the source electrode 11 and the right side of the drain electrode 13 by using a reactive ion etching technology by using the masks to form a table top 14 with the etching depth of 400 nm; the etching adopts the following process conditions: cl2The flow rate is 15sccm, the pressure is 10mTorr, and the power is 100W.
Step j. make gate 15, as in fig. 8 j.
Making a mask on the barrier layer 3, the gate post 7, the source electrode 11, the drain electrode 13 and the upper part of the mesa 14 for the twelfth time, depositing metal on the gate post 7 by using an electron beam evaporation technology by using the mask to make a gate electrode 15, the lower edge of the gate electrode 15 and all N+The upper edges of the pillars 92 are all coincident, and the length thereof is equal to that of the gate pillar 7, wherein the deposited metal is a Ta/Ni metal combination, namely, the lower layer is Ta, the upper layer is Ni, and the thickness thereof is 0.25 μm/0.38 μm; the process conditions adopted for depositing the metal are as follows: vacuum degree less than 1.8X 10- 3Pa, power of 1000W, evaporation rate less than
。
Step k. passivation layer 16 is fabricated as in fig. 8 k.
Depositing SiO with the thickness of 1000nm on the upper parts of the gate column 7, the source electrode 11, the drain electrode 13 and the gate electrode 15 and the peripheral area thereof by adopting a plasma enhanced chemical vapor deposition technology2A passivation layer 16; the process conditions for depositing the passivation layer 16 are: n is a radical of2O flow rate of 850sccm, SiH4The flow rate is 200sccm, the temperature is 250 ℃, and the RF power isThe rate was 100W and the pressure was 1100 mT.
Step l. make 7 grooves, as in fig. 8 l.
Making a mask on the passivation layer 16 for the thirteenth time, and etching the passivation layer 16 between the gate pillar 7 and the N-type drain pillar 8 by using the mask and a reactive ion etching technique to make 7 grooves with the same depth and width, wherein the width a of the groove 34 μm and a depth d of 600 nm. The gate column 7 and the N-type drain column 8 use the 4 th groove as a symmetry axis, and the distance b between the gate column 7 and the first groove is arranged on the left side of the symmetry axis 12 μm, the first and second grooves having a spacing of c1The distance between the second groove and the third groove is c2The distance between the third groove and the fourth groove is c3And c is and c1<c2<c3(ii) a On the right side of the symmetry axis, the distance b between the N-type leakage column 8 and the 1 st groove2Is 2 μm, and the interval between the 1 st groove and the 2 nd groove is i1The distance between the 2 nd groove and the 3 rd groove is i2The distance between the 3 rd groove and the 4 th groove is i3And i is1<i2<i3，c1＝i1,c2＝i2,c3＝i3(ii) a The etching adopts the following process conditions: CF (compact flash)4The flow rate was 45sccm, O2The flow rate is 5sccm, the pressure is 15mTorr, and the power is 250W.
And M, manufacturing a left modulation board, 5 independent metal blocks and a right modulation board, as shown in FIG. 8 m.
Manufacturing a mask on the passivation layer 16 and the upper part of the 7 grooves for the tenth time, depositing metal on the passivation layer between the gate column 7 and the N-type drain column 8 in the 7 grooves by using an electron beam evaporation technology to manufacture a left modulation plate, 5 independent metal blocks and a right modulation plate, electrically connecting the left modulation plate with the source electrode 11, electrically connecting the right modulation plate with the drain electrode 13, suspending the 5 independent metal blocks in the air, and distributing the left modulation plate and the right modulation plate in a left-right symmetrical manner by taking the 3 rd independent metal block as the center to form a composite plate 17, wherein the deposited metal is a Ti/Au metal combination, namely the lower layer is Ti, the upper layer is Au, the thickness of the composite plate is 0.35 mu m/0.28 mu m in sequence, and the deposited metal completely fills the 7 grooves;
the distances between the independent metal blocks and the modulation board and between the independent metal blocks are as follows: taking the 3 rd independent metal block as a symmetry axis, and on the left side of the symmetry axis, the distance S between the left modulation board and the first independent metal block10.35 μm; spacing S between first and second independent metal blocks20.56 μm; spacing S between second and third independent metal blocks30.97 μm; distance U between right modulation board and 1 st independent metal block10.35 μm; distance U between 1 st independent metal block and 2 nd independent metal block20.56 μm; distance U between 2 nd independent metal block and 3 rd independent metal block30.97 μm; the length t of the independent metal block is 5 micrometers, the distance between the right edge of the left modulation plate and the right edge of the grid column 7 is equal to the distance between the left edge of the right modulation plate and the left edge of the N-type drain column 8, and the distance L is 6.5 micrometers; the process conditions adopted for depositing the metal are as follows: vacuum degree less than 1.8X 10-3Pa, power of 1000W, evaporation rate less than
。
Step N. depositing SiO in the peripheral region of the passivation layer 16 and the composite plate 172A protective layer 18 is made, as shown in fig. 8 n.
Introducing N with the flow rate of 850sccm into the reaction chamber2O, SiH at a flow rate of 200sccm4The SiO is deposited in the peripheral region of the passivation layer 16 and the composite plate 17 by using a plasma enhanced chemical vapor deposition technique under the process conditions of a RF power of 100W and a pressure of 1100mTorr at a temperature of 250 DEG C2To make a protective layer 18 with a thickness of 1 μm, thereby completing the fabrication of the entire device;
the effects of the present invention can be further illustrated by the following simulations.
First, simulation parameter
The traditional GaN-based HEMT power switch device and the device of the invention adopt the same main body structure parameters, the device of the invention adopts 11 independent metal blocks, and the length of each independent metal block is 1.6 mu m.
Second, simulation content
Simulation 1: transfer characteristic simulation was performed on the conventional device and the device of the present invention, respectively, and the results are shown in fig. 9.
As can be seen from fig. 9, the threshold voltage of the conventional device is 1V, while the threshold voltage of the device of the present invention is 13.5V, which indicates that the threshold voltage of the device of the present invention is significantly greater than that of the conventional device.
Simulation 2: the conventional device and the device of the present invention were subjected to breakdown characteristic simulation, respectively, and the results are shown in fig. 10.
As can be seen from fig. 10, the conventional device can only achieve forward blocking, and the device breaks down, i.e., the drain current increases rapidly, the drain-source voltage is 296V, while the device of the present invention can achieve forward blocking and reverse blocking, and the breakdown voltage of the device is 2520V when the device breaks down forward, and the breakdown voltage of the device is 2690V when the device breaks down reversely, which indicates that the device of the present invention can achieve bidirectional blocking characteristics, and the breakdown voltage is much greater than that of the conventional device.
The foregoing description is only three specific embodiments of the present invention and is not intended to limit the present invention, and it will be apparent to those skilled in the art that various modifications and variations in form and detail can be made in the method according to the present invention without departing from the principle and scope of the invention, but these modifications and variations are within the scope of the invention as defined in the appended claims.
Claims (21)
1. A junction gate-drain power device comprising, from bottom to top: the device comprises a substrate (1), a transition layer (2), a barrier layer (3) and a passivation layer (16); a gate groove (4) and a leakage groove (5) are carved in the barrier layer (3), a table top (14) is carved on the side surface of the barrier layer, and a gate column (7) is arranged at the upper part of the gate groove (4); the upper portion of gate post (7) deposits grid (15), and its left side deposits source electrode (11), its characterized in that:
the gate column (7) consists of a P-type layer (6) in the gate groove (4) and a P-type layer (6) on the upper part of the gate groove (4), the lower end of the P-type layer (6) is completely filled in the gate groove (4), and an N-type row column (9) is injected into the gate column (7);
the upper part of the leakage groove (5) is provided with an N-shaped leakage column (8), and the right side of the leakage groove is deposited with an ohmic contact (12);
a P-type row column (10) is injected into the N-type leakage column (8), the P-type row column consists of w rectangular P columns which are equally spaced and have the same size, and w is greater than 0;
a drain electrode (13) is deposited on the upper parts of the N-type drain column (8) and the ohmic contact (12) together, the N-type drain column (8), the ohmic contact (12) and the drain electrode (13) are electrically connected with each other, and the lower end of the N-type drain column (8) is completely filled in the drain groove (5);
the N-shaped row columns (9) comprise m rectangular N columns which are equally spaced and have the same size>0, each rectangular N column is composed of a lower rectangular N-Column (91) and upper rectangle N+A column (92);
array holes (19) are etched in the barrier layer (3) at positions on the left side of the gate column (7) and on the right side of the N-type drain column (8);
the lower edge of the gate (15) and all N+The upper edges of the posts (92) are all overlapped;
2N +1 grooves with the same size are etched in the region between the grid column (7) and the N-type drain column (8) on the upper portion of the passivation layer (16); a composite plate (17) is arranged on the groove, and n is more than or equal to 1;
the composite plate (17) is composed of a left modulation plate, a right modulation plate and 2n-1 independent metal blocks with the same size, the lower ends of the metal blocks are completely filled in 2n +1 grooves, the left modulation plate is electrically connected with a source electrode (11), the right modulation plate is electrically connected with a drain electrode (13), the independent metal blocks are suspended in the air, the left modulation plate and a grid electrode (15) are overlapped in the horizontal direction, the right modulation plate and the drain electrode (13) are overlapped in the horizontal direction, and the left modulation plate and the right modulation plate are symmetrically distributed in the left-right direction by taking the nth independent metal block as the center; the composite plate (17) and the passivation layer (16) are provided with protective layers (18) at the peripheries.
2. Device according to claim 1, characterized in that the length a of the gate trench (4)1Greater than or equal to 2nm, and depth z thereof1Is less than the thickness of the barrier layer (3), and z1>0。
3. The device of claim 1The member being characterized by the length a of the discharge slot (5)2Greater than or equal to 2nm and a depth z2，z2>0。
4. The device of claim 1, wherein: the length of the grid column (7) is more than or equal to 4nm, and the distance between the left edge of the grid column and the left edge of the grid groove (4) is q1The distance between the right edge of the grid groove (4) and the right edge of the grid groove is q2And q is1＝q2The length of the grid electrode (15) is equal to that of the grid column (7).
5. The device of claim 1, wherein the N-type drain pillar (8) has a doping concentration of 1 x 1016～5×1020cm-3The lower end of the barrier layer is completely filled in the leakage groove (5) and is positioned at the thickness h above the barrier layer (3)110 to 1200 nm.
6. Device according to claim 1, characterized in that the P-type bent (10) has a depth u1The depth of the leak groove (5) is z2The thickness of the N-shaped leakage column (8) above the leakage groove (5) is h1，u1<z2+h1。
7. Device according to claim 1, characterized in that each rectangular P-pillar in the P-type row of pillars (10) has a width O1The distance between two adjacent rectangular P columns is O2The left edge of the first rectangular P column coincides with the left edge of the N-type leakage column (8), and the distance between the right edges of the w-th rectangular P column and the N-type leakage column (8) is O3The length of the leakage groove (5) is a2，O1＝O2＝O3And satisfies (2w) × (O)1)＝a2。
8. The device according to claim 7, characterized in that the P-type row pillars (10) have a doping concentration of 1 x 1016～5×1020cm-3The doping concentration of the N-type drain column (8) is less than or equal to that of the N-type drain column.
9. The device of claim 1, wherein:
in the gate column (7), N-Column (91) and N+The pillars (92) have the same width, x1Two adjacent N+The pillars (92) have a pitch x2First N+The left edge of the column (92) coincides with the left edge of the gate column (7), the mth N+The distance between the right edge of the column (92) and the grid column (7) is x3The length of the grid groove (4) is a1The distance between the left edge of the grid column (7) and the left edge of the grid groove (4) is q1The distance between the right edge of the grid groove (4) and the right edge of the grid groove is q2，x1＝x2＝x3And satisfies (2m) × x1＝q1+a1+q2。
10. The device of claim 9, wherein said N is-The depth of the column (91) is y1，N+The depth of the column (92) is y2The thickness of the P-type layer (6) is h220 to 1000nm, y1>0，y2>0, and y1+y2<h2。
11. The device of claim 9, wherein:
the doping concentration of the P-type layer (6) is 5 multiplied by 1016～5×1020cm-3，N+The doping concentration of the column (92) is 1 x 1018～5×1020cm-3，N-The doping concentration of the column (91) is 1X 1011～1×1018cm-3And N is-The doping concentration of the columns (91) is less than N+The doping concentration of the pillars (92) and the doping concentration of the P-type layer (6).
12. The device of claim 1, wherein: the array of holes (19) consists of f × g holes with the same size, f>1，g>1, each hole is composed of an upper cuboid hole column (191) and a lower rectangular pyramid (192), and the distance k between two adjacent holes30.5 to 3 μm, outermost peripheral holeA boundary distance k to the source (11) or the ohmic contact (12)11-4 μm;
the upper surface and the lower surface of the hole column (191) are both square, and the side length k of the square20.5 to 2 μm, the depth r of the hole columns (191) is 2 to 20nm, and the lower surfaces of the hole columns (191) are superposed with the upper surface of the rectangular pyramid (192);
the depth e of the rectangular pyramid (192) is 1-35 nm, and the four side faces are the same.
13. Device according to claim 1, characterized in that the source electrode (11) and the ohmic contact (12) are each of length LOAll width being WOThe length of the leakage groove (5) is a2The length of the drain electrode (13) is a2+LOWidth of WO。
14. The device according to claim 1, wherein the drain (13) is formed by a multi-layer metal combination, and the work function of the lowest layer metal is larger than 5eV, and the barrier height formed by the lowest layer metal contacting with each oblong P column in the P-type row column (10) is smaller than the barrier height formed by the lowest layer metal contacting with the N-type drain column (8).
15. The device according to claim 1, wherein the gate (15) is made of a combination of multiple layers of metals, and the work function of the lower layer metal is less than 5eV, and the barrier height formed by the lower layer metal contacting each rectangular N column in the N-type row columns (9) is less than the barrier height formed by the lower layer metal contacting the P-type layer (6).
16. Device according to claim 1, characterized in that the recesses in the passivation layer (16) are of the same size, each recess having a depth d greater than 0 μm and less than the thickness of the passivation layer (16), and each recess having a width a30.1 to 4 μm.
17. The device of claim 1, wherein the nth independent metal block is taken as a symmetry axis, and on the left side of the symmetry axis, a space between the left modulation board and the first independent metal block is formed between the left modulation board and the first independent metal blockA distance of S1The distance between the first independent metal block and the second independent metal block is S2In this way, the distance between the n-1 th independent metal block and the n-th independent metal block is Sn，S1<S2<...<Sn(ii) a On the right side of the symmetry axis, the distance between the right modulation plate and the 1 st independent metal block is U1The distance between the 1 st independent metal block and the 2 nd independent metal block is U2In this way, the distance between the n-1 th independent metal block and the n-th independent metal block is Un，U1<U2<...<UnAnd S is1＝U1，S2＝U2，...，Sn＝Un，n≥1。
18. The device according to claim 1, wherein the left modulation plate, the right modulation plate and each independent metal block have the same thickness, the length t of each independent metal block is 0.5-5 μm, and the distance between the right edge of the left modulation plate and the right edge of the gate pillar (7) is equal to the distance between the left edge of the right modulation plate and the left edge of the N-type drain pillar (8), and the distance is L.
19. Device according to claim 1, characterized in that the distance b between the gate pillar (7) and the first recess is on the left side of the symmetry axis, taking the (n + 1) th recess as the symmetry axis1And 0 μm<b1<(L-a3) The distance between the first groove and the second groove is c1And so on, the distance between the nth groove and the (n + 1) th groove is cn，c1<c2<...<cn(ii) a On the right side of the symmetry axis, the distance between the N-type leakage column (8) and the 1 st groove is b2And 0 μm<b2<(L-a3) The distance between the 1 st groove and the 2 nd groove is i1By analogy, the distance between the nth groove and the (n + 1) th groove is in，i1<i2<...<inAnd b is1＝b2,c1＝i1,c2＝i2,…,cn＝in,n≥1。
20. A method for manufacturing a junction type gate-drain power device is characterized by comprising the following steps:
A) a GaN-based wide bandgap semiconductor material is epitaxially grown on a substrate (1) by adopting a metal organic chemical vapor deposition technology to form a transition layer (2) with the thickness of 1-10 mu m;
B) extending a GaN-based wide bandgap semiconductor material on the transition layer (2) by adopting a metal organic chemical vapor deposition technology to form a barrier layer (3) with the thickness of 4-60 nm;
C) manufacturing a gate groove (4) and a drain groove (5):
C1) manufacturing a mask on the barrier layer (3) for the first time, and etching in the barrier layer (3) by using the mask to form a gate groove (4), wherein the depth of the gate groove (4) is less than the thickness of the barrier layer (3);
C2) manufacturing a mask on the barrier layer (3) and the gate groove (4) for the second time, and etching in the barrier layer (3) by using the mask to form a drain groove (5);
D) a P-type GaN semiconductor material is epitaxially grown on the barrier layer (3) by adopting a molecular beam epitaxy technology, and the gate groove (4) and the drain groove (5) are filled to form a thickness h220-1000 nm, and 5 × 10 of doping concentration16～5×1020cm-3A P-type layer (6);
E) manufacturing a gate column (7) and an N-type drain column (8):
E1) making a mask on the P-type layer (6) for the third time, etching the two sides of the P-type layer (6) by using the mask, etching the outside of the drain groove (5) until the upper surface of the barrier layer (3), and etching the inside of the drain groove (5) to the bottom thereof to form a gate column (7) with the length being more than or equal to 4 nm;
E2) fourthly, a mask is made on the barrier layer (3) and the gate column (7), and N-type GaN semiconductor material is epitaxially grown in the drain groove (5) by using the mask to form a thickness h1An N-type drain column (8) with the length of 10-1200 nm and the length of more than or equal to 2 nm;
F) manufacturing an N-type row column (9) and a P-type row column (10):
F1) making a mask on the barrier layer (3), the gate column (7) and the N-type drain column (8) for the fifth time, and implanting N-type impurities into the P-type layer (6) by using the mask and using an ion implantation technologyM equally spaced N of the same size-A column (91);
F2) continuing to use the mask of F1), implanting N-type impurities again by using ion implantation technique to form m equally spaced N with the same size+Column (92), the m N+Column (92) and m N-The columns (91) together form an N-type row column (9);
F3) making a mask on the barrier layer (3), the gate column (7) and the N-type drain column (8) for the sixth time, and implanting P-type impurities into the N-type drain column (8) by using the mask by using an ion implantation technology to form w rectangular P columns with equal spacing and same size, wherein the w rectangular P columns form a P-type row column (10)
G) Preparing array holes (19):
G1) manufacturing a mask on the barrier layer (3), the gate column (7) and the upper part of the N-type drain column (8) for the seventh time, and etching the barrier layer on the left side and the right side by using the mask to form f multiplied by g cuboid hole columns (191) with the same size;
G2) making a mask on the barrier layer (3), the gate column (7) and the upper part of the N-type drain column (8) for the eighth time, etching f × G cuboid hole columns (191) with the same size formed by G1 by using the mask to form a rectangular pyramid (192) at the lower part of the hole columns (191), wherein the f × G cuboid hole columns (191) with the same size and the rectangular pyramid (192) at the lower part form array holes (19) together;
H) manufacturing a source electrode (11) and a drain electrode (13):
H1) making masks on the barrier layers (3), the gate columns (7) and the upper parts of the N-type drain columns (8) for the ninth time, depositing metal on the barrier layers (3) on the left side and the right side by using the masks by adopting an electron beam evaporation technology, and completely filling the array holes (19), wherein the metal adopts Gd, Zr or Ta;
H2) continuing with the mask in H1), depositing metal again by electron beam evaporation, and applying a voltage to the substrate2Carrying out rapid thermal annealing in the atmosphere, wherein the metal adopts one of Ti/Al/Ni/Au, Ti/Al/Mo/Au or Ti/Al/Ti/Au to form a source electrode (11) and an ohmic contact (12);
H3) making a mask on the barrier layer (3), the gate column (7), the N-type drain column (8), the source electrode (11) and the ohmic contact (12) for the tenth time, depositing metal again by adopting an electron beam evaporation technology, wherein the metal is formed by combining multiple layers of metal, the work function of the metal at the lowest layer is more than 5eV, the barrier height formed by the contact of the metal at the lowest layer and each rectangular P column in the P-type row column (10) is less than the barrier height formed by the contact of the metal at the lowest layer and each rectangular P column in the P-type row column (8), forming a drain electrode (13), and the N-type drain column (8), the ohmic contact (12) and the drain electrode (13) are electrically connected with each other;
I) manufacturing a mask on the barrier layer (3), the gate column (7), the source electrode (11) and the drain electrode (13) for the eleventh time, etching the barrier layer (3) on the left side of the source electrode (11) and the right side of the drain electrode (13) by using the mask, and forming a table top (14) when the depth of an etching area is greater than the thickness of the barrier layer;
J) making a mask on the barrier layer (3), the gate column (7), the source electrode (11), the drain electrode (13) and the upper part of the table top (14) for the twelfth time, depositing a multi-layer metal combination on the upper part of the gate column (7) by using the mask through an electron beam evaporation technology, wherein the work function of lower layer metal is less than 5eV, the barrier height formed by the contact of the lower layer metal and each rectangular N column in the N-type row column (9) is less than the barrier height formed by the contact of the lower layer metal and the P-type layer (6), and making a gate electrode (15), wherein the length of the gate electrode (15) is equal to the length of the gate column;
K) depositing a passivation layer (16) with the thickness of more than or equal to 100nm on the upper parts of the grid column (7), the source electrode (11), the drain electrode (13) and the grid electrode (15) and the peripheral area thereof by adopting a plasma enhanced chemical vapor deposition technology;
l) manufacturing a mask on the passivation layer (16) for the thirteenth time, and etching 2N +1 grooves with the same size on the passivation layer (16) between the grid column (7) and the N-type drain column (8) by using the mask, wherein N is more than or equal to 1;
m) manufacturing a mask on the passivation layer (16) and the upper part of the groove for the fourteenth time, depositing metal on the upper part of the passivation layer (16) and in the groove by using an electron beam evaporation technology by using the mask, completely filling the lower end of the metal in the groove, sequentially manufacturing a left modulation plate, 2n-1 independent metal blocks and a right modulation plate, wherein n is more than or equal to 1, the left modulation plate is electrically connected with the source electrode (11), the right modulation plate is electrically connected with the drain electrode (13), the independent metal blocks are suspended in the air, the left modulation plate is overlapped with the grid electrode (15) in the horizontal direction, the right modulation plate is overlapped with the drain electrode (13) in the horizontal direction, and the left modulation plate and the right modulation plate are distributed in a left-right symmetrical mode by taking the nth independent metal block as the center to form a composite plate (17);
n) depositing a protective layer (18) on the peripheral area of the passivation layer (16) and the composite plate (17) by using an insulating dielectric material and adopting a plasma enhanced chemical vapor deposition technology to finish the manufacture of the whole device.
21. The method of claim 20, wherein:
the molecular beam epitaxy technology comprises the following process conditions: vacuum degree of 1.0X 10 or less-10mbar, radio frequency power of 400W, and N as reactant2A high purity Ga source;
the electron beam evaporation technology comprises the following process conditions: vacuum degree less than 1.8X 10-3Pa, power of 200-1000W, evaporation rate less than
The plasma enhanced chemical vapor deposition technology has the process condition N2O flow rate of 850sccm, SiH4The flow rate is 200sccm, the temperature is 250 ℃, the RF power is 20-100W, and the pressure is 1100 mT.
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| US20150171188A1 (en) * | 2012-12-12 | 2015-06-18 | Electronics And Telecommunications Research Institute | Field effect transistor and method of fabricating the same |
| CN106340536A (en) * | 2016-08-05 | 2017-01-18 | 苏州捷芯威半导体有限公司 | Power semiconductor device and manufacturing method thereof |
| CN107452625A (en) * | 2016-05-30 | 2017-12-08 | 意法半导体股份有限公司 | High power and high-frequency HFET |
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| US20150171188A1 (en) * | 2012-12-12 | 2015-06-18 | Electronics And Telecommunications Research Institute | Field effect transistor and method of fabricating the same |
| CN104393044A (en) * | 2014-11-18 | 2015-03-04 | 西安电子科技大学 | Insulated gate type power device of right-angled gate-drain composite field plate |
| CN107452625A (en) * | 2016-05-30 | 2017-12-08 | 意法半导体股份有限公司 | High power and high-frequency HFET |
| CN106340536A (en) * | 2016-08-05 | 2017-01-18 | 苏州捷芯威半导体有限公司 | Power semiconductor device and manufacturing method thereof |
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