CN106340536A - Power semiconductor device and manufacturing method thereof - Google Patents
Power semiconductor device and manufacturing method thereof Download PDFInfo
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- CN106340536A CN106340536A CN201610638029.1A CN201610638029A CN106340536A CN 106340536 A CN106340536 A CN 106340536A CN 201610638029 A CN201610638029 A CN 201610638029A CN 106340536 A CN106340536 A CN 106340536A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 62
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 38
- 230000004888 barrier function Effects 0.000 claims abstract description 174
- 238000000034 method Methods 0.000 claims abstract description 91
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 230000005533 two-dimensional electron gas Effects 0.000 claims abstract description 20
- 229920002120 photoresistant polymer Polymers 0.000 claims description 62
- 230000008859 change Effects 0.000 claims description 21
- 238000001259 photo etching Methods 0.000 claims description 17
- 239000011159 matrix material Substances 0.000 claims description 16
- 238000005530 etching Methods 0.000 claims description 12
- 238000009616 inductively coupled plasma Methods 0.000 claims description 7
- 238000001039 wet etching Methods 0.000 claims description 7
- 238000011161 development Methods 0.000 claims description 6
- 238000001020 plasma etching Methods 0.000 claims description 6
- 230000008569 process Effects 0.000 abstract description 11
- 238000000137 annealing Methods 0.000 description 16
- 239000000463 material Substances 0.000 description 16
- 239000012776 electronic material Substances 0.000 description 7
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 230000015556 catabolic process Effects 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 238000005036 potential barrier Methods 0.000 description 3
- 206010030113 Oedema Diseases 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 230000035935 pregnancy Effects 0.000 description 2
- 238000004151 rapid thermal annealing Methods 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 229910002601 GaN Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 description 1
- 239000010953 base metal Substances 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000004070 electrodeposition Methods 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 239000001995 intermetallic alloy Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 230000005501 phase interface Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 230000027756 respiratory electron transport chain Effects 0.000 description 1
- 238000012216 screening Methods 0.000 description 1
- 239000007790 solid phase Substances 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0688—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions characterised by the particular shape of a junction between semiconductor regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66431—Unipolar field-effect transistors with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
Abstract
The invention discloses a power semiconductor device and a manufacturing method thereof. The power semiconductor device includes a substrate, a channel layer, a barrier layer, a source electrode, a gate electrode and a drain electrode; the channel layer is arranged on the substrate; the barrier layer is arranged on the channel layer; the source electrode, the gate electrode and the drain electrode are arranged on the barrier layer; a two-dimensional electron gas is formed at the interface of the channel layer and the barrier layer; the gate electrode is located between the source electrode and the drain electrode; a groove structure corresponding to the source electrode and/or a groove structure corresponding to the drain electrode is formed in the barrier layer; and the bottom of the source electrode and/or the bottom of the drain electrode is located in the corresponding groove structure; and the groove structures are in ohmic contact with the barrier layer and/or the channel layer. With the power semiconductor device provided by the above technical schemes of the invention adopted, the technical problem of influence on device performance caused by high temperature when an RTA process is adopted to form ohmic contact in the prior art can be solved.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly, to a kind of power semiconductor and its manufacture method.
Background technology
Gallium nitride (gan), as the Typical Representative of semiconductor material with wide forbidden band, has broader energy gap, higher satisfying
The advantages of with electron transfer rate, bigger critical breakdown electric field intensity and more preferable heat conductivility, gan can be with aluminum gallium nitride
(algan) form algan/gan hetero-junctions.The device of algan/gan hetero-junctions in radio-frequency devices and power electronic devices should
With field, there are great potentiality.On such material, how to form the focus that low-resistance Ohmic contact is always research,
The quality of its electrode ohmic contact performance directly affects output source-drain current and the knee-point voltage of device, then affects penetrating of device
Frequency performance and efficiency.
In prior art, after n-gan Base Metal electrodeposition, need rapid thermal annealing (rapid thermal
Annealing, rta) forming ohm property, make barrier layer Metal Phase Transition using rta technique one side is low resistance to technique
Nitride, on the other hand makes to diffuse into one another between metal, occur solid phase interface reaction formed a series of low resistances, low work function and
Heat-staple intermetallic alloy.But higher annealing temperature is needed using rta technique, the performance of device is had certain not
Good impact.
Content of the invention
In view of this, the embodiment of the present invention provides a kind of power semiconductor and its manufacture method, to solve existing skill
When adopting rta technique to form Ohmic contact in art, high temperature affects the technical problem of device performance.
In a first aspect, embodiments providing a kind of power semiconductor, comprising:
Substrate；
Channel layer above described substrate；
Barrier layer above described channel layer and the source electrode above described barrier layer, grid and drain electrode, institute
The interface stating channel layer with described barrier layer is formed with two-dimensional electron gas, and described grid is located at described source electrode and described drain electrode
Between；
It is formed with groove structure corresponding with described source electrode and/or groove knot corresponding with described drain electrode in described barrier layer
Structure, the bottom of the bottom of described source electrode and/or described drain electrode is located in corresponding described groove structure, by described groove structure
Form Ohmic contact with described barrier layer and/or channel layer.
Optionally, the bottom of described groove structure terminates in described barrier layer or channel layer.
Optionally, at least include a sub- groove in described groove structure.
Optionally, the shape of described sub- groove include following at least one:
The sub- groove of needle pattern, vertical shape groove and the sub- groove of trapezoidal shape.
Optionally, it is formed with two groove structures, source electrode groove structure and drain recesses structure in described barrier layer, described
The bottom of source electrode forms Ohmic contact by described source electrode groove structure with described barrier layer and/or channel layer, described drain electrode
Bottom forms Ohmic contact by described drain recesses structure with described barrier layer and/or channel layer.
Second aspect, the embodiment of the present invention additionally provides a kind of manufacture method of power semiconductor, comprising:
One substrate is provided, and manufactures channel layer over the substrate；
Barrier layer is manufactured on described channel layer, described channel layer and described barrier layer interface are formed with Two-dimensional electron
Gas；
Source electrode, grid and drain electrode are manufactured on described barrier layer, described grid is located between described source electrode and described drain electrode；
Groove structure corresponding with described source electrode and/or groove knot corresponding with described drain electrode is manufactured in described barrier layer
Structure, the bottom of the bottom of described source electrode and/or described drain electrode is located in corresponding described groove structure, by described groove structure
Form Ohmic contact with described barrier layer and/or channel layer, the bottom of described groove structure terminates in described barrier layer or ditch
Channel layer.
Optionally, in described barrier layer manufacture groove structure corresponding with described source electrode and/or with described drain corresponding
Groove structure, comprising:
Photoresist layer is manufactured on described barrier layer；
Using mask plate, photoetching is carried out to described photoresist layer, after development, form change in depth trend and described groove structure
Change in depth trend identical photoresist layer；
Described photoresist layer and barrier layer are etched using lithographic method, manufactures corresponding with described source electrode in described barrier layer
Groove structure and/or with the corresponding groove structure of described drain electrode, the bottom of described groove structure terminate in described barrier layer or
Person's channel layer.
Optionally, in described barrier layer manufacture groove structure corresponding with described source electrode and/or with described drain corresponding
Groove structure, comprising:
Mask layer is manufactured on described barrier layer；
Photoresist layer is manufactured on described mask layer；
Using mask plate, photoetching is carried out to described photoresist layer and develop, form change in depth trend after development recessed with described
Slot structure change in depth trend identical photoresist layer；
Described photoresist layer and mask layer are etched using lithographic method, forms change in depth trend deep with described groove structure
Degree variation tendency identical mask layer；
Described mask layer and barrier layer are etched using lithographic method, manufactures corresponding with described source electrode in described barrier layer
Groove structure and/or with the corresponding groove structure of described drain electrode, the bottom of described groove structure terminate in described barrier layer or
Channel layer.
Optionally, described mask plate is the mask plate with shading dot matrix, by adjusting shading dot matrix in described mask plate
Density degree control described photoresist layer depth of exposure.
Optionally, described lithographic method includes following at least one:
Inductively coupled plasma etching method, reactive ion etching method and wet etching method.
Power semiconductor provided in an embodiment of the present invention and its manufacture method, by manufacturing channel layer on substrate,
Barrier layer is manufactured on channel layer, channel layer and barrier layer interface are formed with two-dimensional electron gas, barrier layer manufactures source electrode,
Grid and drain electrode, grid be located at source electrode and drain electrode between, in barrier layer formed groove structure corresponding with source electrode and/or with leakage
Extremely corresponding groove structure, the bottom of source electrode and/or the bottom of drain electrode be located at corresponding groove structure in, by groove structure with
Barrier layer and/or channel layer form Ohmic contact.Using technique scheme, because exist recessed in barrier layer or in channel layer
Slot structure, thus the side of the electrode in groove structure can with the region of barrier layer portion or channel layer interface at Two-dimensional electron
Gas forms more preferable Ohmic contact, by the annealing of lower temperature or can be without annealing, you can obtain relatively low contact
The ohm configuration of resistance, when can solve to adopt rta technique to form Ohmic contact in prior art, high temperature affects device performance
Technical problem.
Brief description
In order to the technical scheme of exemplary embodiment of the present is clearly described, below to required in description embodiment
Accompanying drawing to be used does one and simply introduces.Obviously, the accompanying drawing introduced is the present invention a part of embodiment to be described
Accompanying drawing, rather than whole accompanying drawings, for those of ordinary skill in the art, on the premise of not paying creative work, also may be used
To obtain other accompanying drawings according to these accompanying drawings.
A kind of structural representation of power semiconductor that Fig. 1 a provides for the embodiment of the present invention one；
A kind of structural representation of power semiconductor that Fig. 1 b provides for the embodiment of the present invention one；
A kind of schematic flow sheet of the manufacture method of power semiconductor that Fig. 2 provides for the embodiment of the present invention one；
A kind of structural representation of power semiconductor that Fig. 3 a provides for the embodiment of the present invention two；
A kind of structural representation of power semiconductor that Fig. 3 b provides for the embodiment of the present invention two；
A kind of structural representation of power semiconductor that Fig. 4 a provides for the embodiment of the present invention three；
A kind of structural representation of power semiconductor that Fig. 4 b provides for the embodiment of the present invention three.
Specific embodiment
For making the object, technical solutions and advantages of the present invention clearer, below with reference to attached in the embodiment of the present invention
Figure, by specific embodiment, is fully described by technical scheme.Obviously, described embodiment is the present invention
A part of embodiment, rather than whole embodiments, based on embodiments of the invention, those of ordinary skill in the art are not doing
The every other embodiment obtaining on the premise of going out creative work, each falls within protection scope of the present invention.
Additionally, in various embodiments may be using the label repeating or sign, these repeat only for simply clear
The ground narration present invention, does not represent and has any relatedness between discussed different embodiments or structure.
Embodiment one
Fig. 1 a and Fig. 1 b is a kind of structural representation of power semiconductor of the embodiment of the present invention one offer, specifically
, power semiconductor provided in an embodiment of the present invention is formed with the groove knot with the sub- groove of needle pattern on barrier layer
Structure.Specifically, in the power semiconductor shown in Fig. 1 a, groove structure terminates in barrier layer, the power shown in Fig. 1 b half
In conductor device, groove structure terminates in channel layer.As illustrated in figs. ia and ib, described power semiconductor can wrap
Include:
Substrate 101；
Channel layer 102 positioned at substrate 101 top；
Barrier layer 103 positioned at channel layer 102 top；
Source electrode 104 positioned at barrier layer 103 top, grid 105 and drain electrode 106, the boundary of channel layer 102 and barrier layer 103
It is formed with two-dimensional electron gas 107, grid 105 is located between source electrode 104 and drain electrode 106 at face；
Be formed with barrier layer 103 groove structure corresponding with source electrode 104 and/or with drain electrode 106 corresponding groove structures,
The bottom of the bottom of source electrode 104 and/or drain electrode 106 is located in corresponding described groove structure, by groove structure and barrier layer
103 and/or channel layer 102 formed Ohmic contact.
Further, the bottom of described groove structure can terminate in barrier layer 103 or channel layer 102.
Optionally, could be formed with two groove structures, source electrode groove structure 108 and drain recesses knot in barrier layer 103
Structure 109, the bottom of source electrode 104 is passed through source electrode groove structure 108 and is formed Ohmic contact with barrier layer 103 and/or channel layer 102,
The bottom of drain electrode 106 is passed through drain recesses structure 109 and is formed Ohmic contact with barrier layer 103 and/or channel layer 102.
Groove structure in the embodiment of the present invention can at least include a sub- groove, and the shape of described sub- groove can be wrapped
Include following at least one: the sub- groove of needle pattern, vertical shape groove and the sub- groove of trapezoidal shape.The embodiment of the present invention one is specifically retouched
State a kind of sub- groove structure of needle pattern, the embodiment of the present invention can also include the sub- groove structure of other shapes, specifically at this
It is introduced in bright other embodiment.
Exemplary, the material of substrate 101 can be silicon, carborundum or sapphire, can also be other materials.
Channel layer 102 is located above substrate 101, and the material of channel layer 102 can be gan or other semi-conducting materials,
Such as inaln, preferably gan here.
Barrier layer 103 is located above channel layer 102, and the material of barrier layer 103 can be algan or other quasiconductor materials
Material, such as inaln, preferably algan here.Further, channel layer 102 and barrier layer 103 composition heterojunction semiconductor knot
Structure, forms high concentration two-dimensional electron gas 107 in the interface of channel layer 102 and barrier layer 103, and different in channel layer 102
Conducting channel is produced at matter junction interface.
Source electrode 104, grid 105 and drain electrode 106 are located above barrier layer 103, and source electrode 104, drain electrode 106 are located at barrier layer 1
Grid 105 is located between source electrode 104 and drain electrode 106.Further, source electrode 104, drain electrode 106 material can for ni, ti, al,
The combination of one or more of the metals such as au, the material of grid 105 can be one of metal such as ni, pt, pb, au or many
The combination planted, grid 105 and barrier layer 103 Schottky contacts.Further, grid 105 can be t type structure, and embedded gesture
The leakage current of grid, boost device breakdown voltage in barrier layer 103, can be reduced.
Could be formed with barrier layer 103 groove structure corresponding with source electrode 104 and/or with drain electrode 106 corresponding grooves
Structure, the bottom of the bottom of source electrode 104 and/or drain electrode 106 is located in corresponding groove structure, further, in barrier layer 103
Could be formed with two groove structures, source electrode groove structure 108 and drain recesses structure 109, source electrode is passed through in the bottom of source electrode 104
Groove structure 108 forms Ohmic contact with barrier layer 103 and/or channel layer 102, and the bottom of drain electrode 106 is tied by drain recesses
Structure 109 forms Ohmic contact with barrier layer 103 and/or channel layer 102.
Further, at least include needle pattern in source electrode groove structure 108 and/or drain recesses structure 109 recessed
Groove 110, to needle pattern, the spike concrete shape of sub- groove 110 and particular number are not defined here, only need to meet source electrode
The bottom of the bottom of electrode and/or drain electrode is contacted with barrier layer 103 or channel layer 102 by the sub- groove of needle pattern 110
?.The bottom of source electrode 104 pass through the sub- groove structure of needle pattern 110 in source electrode groove structure 108 and barrier layer 103 and/or
Channel layer 102 forms Ohmic contact, the bottom of drain electrode 106 by the sub- groove structure of needle pattern of drain recesses structure 109 110 with
Barrier layer 103 and/or channel layer 102 form Ohmic contact.The bottom of the sub- groove of needle pattern 110 terminate in barrier layer 103 and/or
Channel layer 102.It is understood that when the bottom of the sub- groove of needle pattern 110 terminates in barrier layer 103, as shown in Figure 1a, position
The side of the source electrode in the sub- groove of needle pattern 110 and/or drain electrode can form Ohmic contact with barrier layer 103,
The evolving path of electronic material so can be reduced, and then reduce the temperature of annealing process；Bottom when the sub- groove of needle pattern 110
When terminating in channel layer 102, as shown in Figure 1 b, although now the lower section of the sub- groove of needle pattern 110 there is no two-dimensional electron gas 107,
But the side of the sub- groove of needle pattern 110 is contacted with two-dimensional electron gas 107, therefore, the source electrode in the sub- groove of needle pattern 110
The side of electrode and/or drain electrode can form Ohmic contact with two-dimensional electron gas 107, so can not adopt lehr attendant
Skill, can be directly realized by the structure of low ohm contact resistance.
The power semiconductor that the embodiment of the present invention one provides, is formed with groove knot corresponding with source electrode in barrier layer
Structure and/or with the corresponding groove structure that drains, specially include the groove structure of the sub- groove of needle pattern, the bottom of source electrode and/or
The bottom of drain electrode is located in corresponding groove structure, forms Ohmic contact by groove structure with barrier layer and/or channel layer, by
Terminate in barrier layer or channel layer in the bottom of groove structure, so, when electrode material pass through groove structure and barrier layer and/
Or during channel layer formation Ohmic contact, it is possible to reduce the evolving path of electronic material, and then reduce the temperature of annealing process, it is to avoid
Loss device being caused due to high annealing.
The embodiment of the present invention one also provides a kind of manufacture method of power semiconductor, specifically, in described power half
On the barrier layer of conductor device manufacture have groove structure corresponding with source electrode and/or with drain corresponding groove structure, described recessed
At least include a sub- groove in slot structure, the shape of described sub- groove can for the sub- groove of needle pattern, vertical shape groove with
And at least one in the sub- groove of trapezoidal shape.The embodiment of the present invention one specifically describes a kind of power half with the sub- groove of needle pattern
The manufacture method of conductor device, the embodiment of the present invention can also include the power semiconductor of the sub- groove structure of other shapes
Manufacture method, be specifically introduced in the other embodiment of the present invention.
As shown in Fig. 2 the manufacture of the power semiconductor of the sub- groove structure of needle pattern of the embodiment of the present invention one offer
Method may comprise steps of:
S210 a: substrate is provided, and manufactures channel layer over the substrate.
Exemplary, the material of substrate 101 can be silicon, carborundum or sapphire, can also be other materials.Optional
, the material of channel layer 102 can be gan or other semi-conducting materials, such as inaln, preferably gan here.
S220: barrier layer is manufactured on described channel layer, described channel layer and described barrier layer interface are formed with two dimension
Electron gas.
Exemplary, the material of barrier layer 103 can be algan or other semi-conducting materials, and such as inaln is excellent here
Elect algan as.Further, channel layer 102 and barrier layer 103 composition semiconductor heterostructure, in channel layer 102 and potential barrier
The interface of layer 103 forms high concentration two-dimensional electron gas 107, and produces conductive ditch at the heterojunction boundary of channel layer 102
Road.
S230: source electrode, grid and drain electrode are manufactured on described barrier layer, described grid is located at described source electrode and described drain electrode
Between.
Exemplary, source electrode 104, grid 105 and drain electrode 106, source electrode 104, drain electrode 106 are manufactured on barrier layer 103
In the two ends of barrier layer 103, grid 105 is located between source electrode 104 and drain electrode 106.Further, source electrode 104, drain electrode 106
Material can be the combination of one or more of the metal such as ni, ti, al, au, the material of grid 105 can for ni, pt, pb,
The combination of one or more of the metals such as au, grid 105 and barrier layer 103 Schottky contacts.Further, grid 105 can
Think t type structure, and in embedded barrier layer 103, the leakage current of grid, boost device breakdown voltage can be reduced.
S240: in described barrier layer manufacture groove structure corresponding with described source electrode and/or with described drain corresponding
Groove structure, the bottom of the bottom of described source electrode and/or described drain electrode is located in corresponding described groove structure, by described recessed
Slot structure forms Ohmic contact with described barrier layer and/or channel layer, and the bottom of described groove structure terminates in described barrier layer
Or channel layer.
Exemplary, groove structure corresponding with source electrode 104 and/or 106 corresponding with draining is manufactured on barrier layer 103
Groove structure, the bottom of the bottom of source electrode 104 and/or drain electrode 106 is located in corresponding described groove structure.Further, exist
Two groove structures, source electrode groove structure 108 and drain recesses structure 109 are manufactured on barrier layer 103, the bottom of source electrode 104 leads to
Cross source electrode groove structure 108 and form Ohmic contact with barrier layer 103 and/or channel layer 102, drain electrode is passed through in the bottom of drain electrode 106
Groove structure 109 forms Ohmic contact with barrier layer 103 and/or channel layer 102.Optionally, source electrode groove structure 108 and/
Or in drain recesses structure 109, manufacturing the sub- groove of at least one needle pattern 110, source electrode groove structure is passed through in the bottom of source electrode 104
The sub- groove structure of needle pattern in 108 110 forms Ohmic contact, the bottom of drain electrode 106 with barrier layer 103 and/or channel layer 102
Form ohm by the sub- groove structure of the needle pattern of drain recesses structure 109 110 with barrier layer 103 and/or channel layer 102 to connect
Touch.The bottom of the sub- groove of needle pattern 110 terminates in barrier layer 103 or channel layer 102.
Optionally, in described barrier layer manufacture groove structure corresponding with described source electrode and/or with described drain corresponding
Groove structure, may include that
Photoresist layer is manufactured on described barrier layer；
Using mask plate, photoetching is carried out to described photoresist layer, after development, form thickness changing trend and described groove structure
Thickness changing trend identical photoresist layer；
Described photoresist layer and barrier layer are etched using lithographic method, manufactures corresponding with described source electrode in described barrier layer
Groove structure and/or with the corresponding groove structure of described drain electrode, the bottom of described groove structure terminate in described barrier layer or
Person's channel layer.
Exemplary, photoresist layer is manufactured on barrier layer, described photoresist layer covers above described barrier layer, uses
Mask plate photoetching simultaneously forms thickness changing trend and described groove structure thickness changing trend identical photoresist layer, tool after developing
Body can be the sub- groove thickness of needle pattern being formed using mask plate photoetching and after developing in thickness changing trend and groove structure
Variation tendency identical photoresist layer.Optionally, it is possible to use there is the mask plate of shading dot matrix, by adjusting described mask plate
The density degree of middle shading dot matrix is in that needle pattern changes, and controls the depth of exposure of described photoresist layer, ultimately forms and groove knot
Needle pattern in structure groove thickness variation tendency identical photoresist layer.Described photoresist layer and gesture are etched using lithographic method
Barrier layer, forms the groove structure at least including the sub- groove of needle pattern.Further, described lithographic method can include following
At least one: inductively coupled plasma etching method, reactive ion etching method and wet etching method.
Optionally, in described barrier layer manufacture groove structure corresponding with described source electrode and/or with described drain corresponding
Groove structure, may include that
Mask layer is manufactured on described barrier layer；
Photoresist layer is manufactured on described mask layer；
Using mask plate, photoetching is carried out to described photoresist layer and develop, form change in depth trend after development recessed with described
Slot structure change in depth trend identical photoresist layer；
Described photoresist layer and mask layer are etched using lithographic method, forms change in depth trend deep with described groove structure
Degree variation tendency identical mask layer；
Described mask layer and barrier layer are etched using lithographic method, manufactures corresponding with described source electrode in described barrier layer
Groove structure and/or with the corresponding groove structure of described drain electrode, the bottom of described groove structure terminate in described barrier layer or
Channel layer.
Exemplary, barrier layer manufactures mask layer, photoresist layer is manufactured on described mask layer, described mask layer covers
Cover above described barrier layer, described photoresist layer covers above described mask layer, shape using mask plate photoetching and after developing
Become thickness changing trend and described groove structure thickness changing trend identical photoresist layer, can be specifically using mask plate light
Form the needle pattern groove thickness variation tendency identical photoresist in thickness changing trend and groove structure after carving and developing
Layer.Optionally, it is possible to use there is the mask plate of shading dot matrix, by adjusting the density degree of shading dot matrix in described mask plate
Change in needle pattern, control the depth of exposure of described photoresist layer, ultimately form the sub- groove with the needle pattern in groove structure thick
Degree variation tendency identical photoresist layer.Described photoresist layer and mask layer are etched using lithographic method, forms thickness change and become
Needle pattern groove thickness variation tendency identical mask layer in gesture and groove structure.Described mask is etched using lithographic method
Layer and barrier layer, form the groove structure at least including the sub- groove of needle pattern.Further, described lithographic method can wrap
Include following at least one: inductively coupled plasma etching method, reactive ion etching method and wet etching method.
The manufacture method of power semiconductor provided in an embodiment of the present invention, by channel layer is manufactured on substrate,
Barrier layer is manufactured on channel layer, channel layer and barrier layer interface are formed with two-dimensional electron gas, source electrode, grid are manufactured on barrier layer
Pole and drain electrode, grid be located at source electrode and drain electrode between, in barrier layer manufacture groove structure corresponding with source electrode and/or with drain electrode
Corresponding groove structure, the bottom of source electrode and/or the bottom of drain electrode are located in corresponding groove structure, by groove structure and gesture
Barrier layer and/or channel layer form Ohmic contact.Using technique scheme, source electrode and/or drain electrode are tied by groove
Structure forms Ohmic contact with barrier layer and/or channel layer, it is possible to reduce the evolving path of electronic material, and then reduces annealing process
Temperature, it is to avoid loss device being caused due to high annealing.
Embodiment two
A kind of structural representation of power semiconductor that Fig. 3 a and Fig. 3 b provides for the embodiment of the present invention two, this enforcement
Example, based on above-described embodiment one, improves, the shape of specially antithetical phrase groove is changed on the basis of embodiment one
Enter.Specifically, power semiconductor provided in an embodiment of the present invention is formed with barrier layer and has vertical shape groove
Groove structure.Specifically, in the power semiconductor shown in Fig. 3 a, groove structure terminates in barrier layer, shown in Fig. 3 b
In power semiconductor, groove structure terminates in channel layer.As shown in Figure 3 a and Figure 3 b shows, described power semiconductor can
To include:
Substrate 101；
Channel layer 102 positioned at substrate 101 top；
Barrier layer 103 positioned at channel layer 102 top；
Source electrode 104 positioned at barrier layer 103 top, grid 105 and drain electrode 106, the boundary of channel layer 102 and barrier layer 103
It is formed with two-dimensional electron gas 107, grid 105 is located between source electrode 104 and drain electrode 106 at face；
Be formed with barrier layer 103 groove structure corresponding with source electrode 104 and/or with drain electrode 106 corresponding groove structures,
The bottom of the bottom of source electrode 104 and/or drain electrode 106 is located in corresponding described groove structure, by groove structure and barrier layer
103 and/or channel layer 102 formed Ohmic contact.Further, could be formed with two groove structures, source electrode in barrier layer 103
One is at least included in groove structure 108 and drain recesses structure 109, source electrode groove structure 108 and/or drain recesses structure 109
Individual vertical shape groove 210, is not defined to the concrete shape and particular number of vertical shape groove 210 here, only needs
Vertical shape groove 210 and barrier layer 103 or channel layer are passed through in the bottom of the bottom and/or drain electrode that meet source electrode
102 contact.Vertical shape groove structure 210 and barrier layer in source electrode groove structure 108 are passed through in the bottom of source electrode 104
103 and/or channel layer 102 form Ohmic contact, the bottom of drain electrode 106 is by the vertical shape groove of drain recesses structure 109
Structure 210 forms Ohmic contact with barrier layer 103 and/or channel layer 102.Vertically the bottom of shape groove 210 terminates in potential barrier
Layer 103 or channel layer 102.It is understood that when the bottom of vertical shape groove 210 terminates in barrier layer 103, such as scheming
Shown in 3a, the source electrode in vertical shape groove 210 and/or the side of drain electrode can be formed with barrier layer 103
Ohmic contact, so can reduce the evolving path of electronic material, and then reduce the temperature of annealing process；When vertical shape groove
When 210 bottom terminates in channel layer 102, as shown in Figure 3 b, although now vertically the lower section of shape groove 210 does not have two dimension electricity
Edema of the legs during pregnancy 107, but the side of vertical shape groove 210 is contacted with two-dimensional electron gas 107, therefore, positioned at vertical shape groove 210
The side of interior source electrode and/or drain electrode can form Ohmic contact with two-dimensional electron gas 107, so can not adopt
Annealing process, can be directly realized by the structure of low ohm contact resistance.
The power semiconductor that the embodiment of the present invention two provides, is formed with groove knot corresponding with source electrode in barrier layer
Structure and/or with drain corresponding groove structure, specially include the groove structure of vertical shape groove, with the embodiment of the present invention one
The groove structure role with the sub- groove of needle pattern providing is compared, when source electrode and/or drain electrode pass through to erect
When straight shape groove structure forms Ohmic contact with barrier layer and/or channel layer, it is possible to reduce the evolving path of electronic material, enter
And reduce the temperature of annealing process, it is to avoid loss device being caused due to high annealing.
The embodiment of the present invention two also provides a kind of manufacture method of power semiconductor, and specially one kind has vertical shape
The manufacture method of the power semiconductor of sub- groove, the power semiconductor with the sub- groove of needle pattern providing with embodiment one
The difference of manufacture method be, it is possible to use mask plate photoetching simultaneously forms thickness changing trend and described groove structure after developing
Thickness changing trend identical photoresist layer, can be specifically formed using mask plate photoetching and after developing thickness changing trend with
Vertical shape groove thickness variation tendency identical photoresist layer in groove structure.Optionally, it is possible to use there is chopping point
The mask plate of battle array, is in vertical shape change by the density degree adjusting shading dot matrix in described mask plate, controls described photoresist
The depth of exposure of layer, ultimately forms and the vertical shape groove thickness variation tendency identical photoresist layer in groove structure.Adopt
Etch described photoresist layer and barrier layer with lithographic method, form the groove structure at least including a vertical shape groove.Also
Can be to etch described photoresist layer and mask layer, form thickness changing trend identical with described groove structure thickness changing trend
Photoresist layer, can be specifically formed using mask plate photoetching and after developing vertical in thickness changing trend and groove structure
Shape groove thickness variation tendency identical photoresist layer.Optionally, it is possible to use there is the mask plate of shading dot matrix, by adjusting
In whole described mask plate, the density degree of shading dot matrix is in vertical shape change, controls the depth of exposure of described photoresist layer, finally
Formed and the vertical shape groove thickness variation tendency identical photoresist layer in groove structure.Described using lithographic method etching
Photoresist layer and mask layer, form the vertical shape groove thickness variation tendency identical in thickness changing trend and groove structure
Mask layer.Described mask layer and barrier layer are etched using lithographic method, forms the groove at least including a vertical shape groove
Structure.Further, described lithographic method can include following at least one: inductively coupled plasma etching method, reaction
Ion etching process and wet etching method.
Embodiment three
A kind of structural representation of power semiconductor that Fig. 4 a and Fig. 4 b provides for the embodiment of the present invention three, this enforcement
Example, based on above-described embodiment one and embodiment two, improves, specially antithetical phrase groove on the basis of above-described embodiment
Shape improve.Specifically, power semiconductor provided in an embodiment of the present invention is formed with ladder on barrier layer
The groove structure of the sub- groove of shape.Specifically, in the power semiconductor shown in Fig. 4 a, groove structure terminates in barrier layer
In, in the power semiconductor shown in Fig. 4 b, groove structure terminates in channel layer.As shown in figures 4 a and 4b, described work(
Rate semiconductor device may include that
Substrate 101；
Channel layer 102 positioned at substrate 101 top；
Barrier layer 103 positioned at channel layer 102 top；
Source electrode 104 positioned at barrier layer 103 top, grid 105 and drain electrode 106, the boundary of channel layer 102 and barrier layer 103
It is formed with two-dimensional electron gas 107, grid 105 is located between source electrode 104 and drain electrode 106 at face；
Be formed with barrier layer 103 groove structure corresponding with source electrode 104 and/or with drain electrode 106 corresponding groove structures,
The bottom of the bottom of source electrode 104 and/or drain electrode 106 is located in corresponding described groove structure, by groove structure and barrier layer
103 and/or channel layer 102 formed Ohmic contact.Further, could be formed with two groove structures, source electrode in barrier layer 103
One is at least included in groove structure 108 and drain recesses structure 109, source electrode groove structure 108 and/or drain recesses structure 109
The sub- groove 310 of individual trapezoidal shape, to trapezoidal shape, the concrete shape of sub- groove 310 and particular number are not defined here, only need
The sub- groove of trapezoidal shape 310 and barrier layer 103 or channel layer are passed through in the bottom of the bottom and/or drain electrode that meet source electrode
102 contact.The sub- groove structure of trapezoidal shape 310 and barrier layer in source electrode groove structure 108 are passed through in the bottom of source electrode 104
103 and/or channel layer 102 form Ohmic contact, the bottom of drain electrode 106 is by the sub- groove of trapezoidal shape of drain recesses structure 109
Structure 310 forms Ohmic contact with barrier layer 103 and/or channel layer 102.The bottom of the sub- groove of trapezoidal shape 310 terminates in potential barrier
Layer 103 or channel layer 102.It is understood that when the bottom of the sub- groove of trapezoidal shape 310 terminates in barrier layer 103, such as scheming
Shown in 4a, the source electrode in the sub- groove of trapezoidal shape 310 and/or the side of drain electrode can be formed with barrier layer 103
Ohmic contact, so can reduce the evolving path of electronic material, and then reduce the temperature of annealing process；When the sub- groove of trapezoidal shape
When 310 bottom terminates in channel layer 102, as shown in Figure 4 b, although now the lower section of the sub- groove of trapezoidal shape 310 do not have two dimension electricity
Edema of the legs during pregnancy 107, but the side of the sub- groove of trapezoidal shape 310 is contacted with two-dimensional electron gas 107, therefore, positioned at the sub- groove of trapezoidal shape 310
The side of interior source electrode and/or drain electrode can form Ohmic contact with two-dimensional electron gas 107, so can not adopt
Annealing process, can be directly realized by the structure of low ohm contact resistance.
The power semiconductor that the embodiment of the present invention three provides, is formed with groove knot corresponding with source electrode in barrier layer
Structure and/or with drain corresponding groove structure, specially include the groove structure of the sub- groove of trapezoidal shape, with the embodiment of the present invention one
The sub- groove of needle pattern that has providing with embodiment two is compared with the groove structure role of vertical shape groove, works as source electrode
When electrode and/or drain electrode pass through the sub- groove structure of trapezoidal shape with barrier layer and/or channel layer formation Ohmic contact, can subtract
The evolving path of few electronic material, and then reduce the temperature of annealing process, it is to avoid loss device being caused due to high annealing.
The embodiment of the present invention three also provides a kind of manufacture method of power semiconductor, and specially one kind has trapezoidal shape
The manufacture method of the power semiconductor of sub- groove, the difference of the manufacture method of the power semiconductor providing with above-described embodiment
It is, it is possible to use mask plate photoetching to form thickness changing trend after developing identical with described groove structure thickness changing trend
Photoresist layer, can be specifically formed using mask plate photoetching and after developing trapezoidal in thickness changing trend and groove structure
Shape groove thickness variation tendency identical photoresist layer.Optionally, it is possible to use there is the mask plate of shading dot matrix, by adjusting
In whole described mask plate, the density degree trapezoidal shape change of shading dot matrix, controls the depth of exposure of described photoresist layer, finally
Formed and the trapezoidal shape groove thickness variation tendency identical photoresist layer in groove structure.Described using lithographic method etching
Photoresist layer and barrier layer, form the groove structure at least including the sub- groove of trapezoidal shape.Can also be the described photoetching of etching
Glue-line and mask layer, form thickness changing trend and described groove structure thickness changing trend identical photoresist layer, specifically may be used
To be to form thickness changing trend to change with the sub- groove thickness of trapezoidal shape in groove structure using mask plate photoetching and after developing
Trend identical photoresist layer.Optionally, it is possible to use there is the mask plate of shading dot matrix, by adjusting screening in described mask plate
Light dot matrix density degree trapezoidal shape change, control described photoresist layer depth of exposure, ultimately form with groove structure in
Trapezoidal shape groove thickness variation tendency identical photoresist layer.Described photoresist layer and mask are etched using lithographic method
Layer, forms the trapezoidal shape groove thickness variation tendency identical mask layer in thickness changing trend and groove structure.Using quarter
Etching method etches described mask layer and barrier layer, forms the groove structure at least including the sub- groove of trapezoidal shape.Further,
Described lithographic method can include following at least one: inductively coupled plasma etching method, reactive ion etching method with
And wet etching method.
Although it should be noted that above-described embodiment passes through some exemplary embodiments tying to the groove that has of the present invention
The power semiconductor of structure and its manufacture method are described in detail, but the above embodiment is not exhaustion
, those skilled in the art can realize various change within the spirit and scope of the present invention.Shape as sub- groove does not limit
Needle pattern in above-described embodiment, vertical shape and three kinds of situations of trapezoidal shape, the sub- groove of other shapes or structure also belongs to
The scope that the present invention is protected；Accordingly, the manufacture method of groove structure is not limited to the adjustment mask plate in above-described embodiment
The method that the density degree of middle shading dot matrix carries out photoetching, multiple etching, the method that other can manufacture structure in the present invention is equal
Belong to the scope that the present invention is protected；Accordingly, lithographic method is not limited to the inductively coupled plasma in above-described embodiment
Lithographic method, reactive ion etching method and wet etching method, other can be to photoresist layer, mask layer or barrier layer
The method performing etching belongs to the scope that the present invention is protected.
Note, above are only presently preferred embodiments of the present invention and institute's application technology principle.It will be appreciated by those skilled in the art that
The invention is not restricted to specific embodiment described here, can carry out for a person skilled in the art various obvious changes,
Readjust and substitute without departing from protection scope of the present invention.Therefore although being carried out to the present invention by above example
It is described in further detail, but the present invention is not limited only to above example, without departing from the inventive concept, also
Other Equivalent embodiments more can be included, and the scope of the present invention is determined by scope of the appended claims.
Claims (10)
1. a kind of power semiconductor is it is characterised in that include:
Substrate；
Channel layer above described substrate；
Barrier layer above described channel layer and the source electrode above described barrier layer, grid and drain electrode, described ditch
Channel layer is formed with two-dimensional electron gas with the interface of described barrier layer, and described grid is located between described source electrode and described drain electrode；
Be formed with described barrier layer groove structure corresponding with described source electrode and/or with described drain electrode corresponding groove structure,
The bottom of the bottom of described source electrode and/or described drain electrode be located at corresponding described groove structure in, by described groove structure with
Described barrier layer and/or channel layer form Ohmic contact.
2. power semiconductor according to claim 1 is it is characterised in that the bottom of described groove structure terminates in institute
State barrier layer or channel layer.
3. power semiconductor according to claim 1 is it is characterised in that at least include one in described groove structure
Sub- groove.
4. power semiconductor according to claim 3 it is characterised in that the shape of described sub- groove include following extremely
One item missing:
The sub- groove of needle pattern, vertical shape groove and the sub- groove of trapezoidal shape.
5. according to the arbitrary described power semiconductor of claim 1-4 it is characterised in that being formed with two in described barrier layer
Individual groove structure, source electrode groove structure and drain recesses structure, described source electrode groove structure and institute are passed through in the bottom of described source electrode
State barrier layer and/or channel layer forms Ohmic contact, the bottom of described drain electrode is by described drain recesses structure and described gesture
Barrier layer and/or channel layer form Ohmic contact.
6. a kind of manufacture method of power semiconductor is it is characterised in that described manufacture method includes:
One substrate is provided, and manufactures channel layer over the substrate；
Barrier layer is manufactured on described channel layer, described channel layer and described barrier layer interface are formed with two-dimensional electron gas；
Source electrode, grid and drain electrode are manufactured on described barrier layer, described grid is located between described source electrode and described drain electrode；
In described barrier layer manufacture groove structure corresponding with described source electrode and/or with described drain corresponding groove structure,
The bottom of the bottom of described source electrode and/or described drain electrode be located at corresponding described groove structure in, by described groove structure with
Described barrier layer and/or channel layer form Ohmic contact, and the bottom of described groove structure terminates in described barrier layer or raceway groove
Layer.
7. the manufacture method of power semiconductor according to claim 6 is it is characterised in that make in described barrier layer
Make groove structure corresponding with described source electrode and/or with described drain electrode corresponding groove structure, comprising:
Photoresist layer is manufactured on described barrier layer；
Using mask plate, photoetching is carried out to described photoresist layer, after development, form change in depth trend and described groove structure depth
Variation tendency identical photoresist layer；
Described photoresist layer and barrier layer are etched using lithographic method, manufactures corresponding with described source electrode recessed in described barrier layer
Slot structure and/or with described drain electrode corresponding groove structure, the bottom of described groove structure terminates in described barrier layer or ditch
Channel layer.
8. the manufacture method of power semiconductor according to claim 6 is it is characterised in that make in described barrier layer
Make groove structure corresponding with described source electrode and/or with described drain electrode corresponding groove structure, comprising:
Mask layer is manufactured on described barrier layer；
Photoresist layer is manufactured on described mask layer；
Using mask plate, photoetching is carried out to described photoresist layer and develop, after development, form change in depth trend and described groove knot
Structure change in depth trend identical photoresist layer；
Described photoresist layer and mask layer are etched using lithographic method, forms change in depth trend and become with described groove structure depth
Change trend identical mask layer；
Described mask layer and barrier layer are etched using lithographic method, manufactures groove corresponding with described source electrode in described barrier layer
Structure and/or with described drain electrode corresponding groove structure, the bottom of described groove structure terminates in described barrier layer or raceway groove
Layer.
9. the manufacture method of the power semiconductor according to claim 7 or 8 is it is characterised in that described mask plate is
There is the mask plate of shading dot matrix, described photoresist layer is controlled by the density degree adjusting shading dot matrix in described mask plate
Depth of exposure.
10. the manufacture method of the power semiconductor according to claim 7 or 8 is it is characterised in that described lithographic method
Including following at least one:
Inductively coupled plasma etching method, reactive ion etching method and wet etching method.
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| JP2019192698A (en) * | 2018-04-19 | 2019-10-31 | 富士通株式会社 | Semiconductor device, method of manufacturing the same and amplifier |
| CN111081763A (en) * | 2019-12-25 | 2020-04-28 | 大连理工大学 | Normally-off HEMT device with honeycomb groove barrier layer structure below field plate and preparation method thereof |
| CN111863950A (en) * | 2020-07-28 | 2020-10-30 | 西安电子科技大学 | Junction gate-drain power device |
| CN112885896A (en) * | 2021-01-29 | 2021-06-01 | 电子科技大学 | HEMT device |
| CN113113477A (en) * | 2021-03-01 | 2021-07-13 | 西安电子科技大学 | GaN radio frequency device based on ScAlN double-channel heterojunction structure and preparation method thereof |
| CN113809169A (en) * | 2021-08-25 | 2021-12-17 | 西安电子科技大学 | Gallium nitride device based on gate-source-drain integrated deposition and manufacturing method thereof |
| WO2022027536A1 (en) * | 2020-08-07 | 2022-02-10 | Innoscience (Zhuhai) Technology Co., Ltd. | Semiconductor device and fabrication method thereof |
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| US20040201038A1 (en) * | 2003-01-27 | 2004-10-14 | Tokuharu Kimura | Compound semiconductor device and its manufacture |
| JP2015133407A (en) * | 2014-01-14 | 2015-07-23 | トランスフォーム・ジャパン株式会社 | Semiconductor device and method of manufacturing the same |
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|---|---|---|---|---|
| JP2019192698A (en) * | 2018-04-19 | 2019-10-31 | 富士通株式会社 | Semiconductor device, method of manufacturing the same and amplifier |
| CN111081763A (en) * | 2019-12-25 | 2020-04-28 | 大连理工大学 | Normally-off HEMT device with honeycomb groove barrier layer structure below field plate and preparation method thereof |
| CN111081763B (en) * | 2019-12-25 | 2021-09-14 | 大连理工大学 | Normally-off HEMT device with honeycomb groove barrier layer structure below field plate and preparation method thereof |
| CN111863950A (en) * | 2020-07-28 | 2020-10-30 | 西安电子科技大学 | Junction gate-drain power device |
| CN111863950B (en) * | 2020-07-28 | 2021-08-20 | 西安电子科技大学 | Junction gate-drain power device |
| WO2022027536A1 (en) * | 2020-08-07 | 2022-02-10 | Innoscience (Zhuhai) Technology Co., Ltd. | Semiconductor device and fabrication method thereof |
| CN112885896A (en) * | 2021-01-29 | 2021-06-01 | 电子科技大学 | HEMT device |
| CN113113477A (en) * | 2021-03-01 | 2021-07-13 | 西安电子科技大学 | GaN radio frequency device based on ScAlN double-channel heterojunction structure and preparation method thereof |
| CN113809169A (en) * | 2021-08-25 | 2021-12-17 | 西安电子科技大学 | Gallium nitride device based on gate-source-drain integrated deposition and manufacturing method thereof |
| WO2024055776A1 (en) * | 2022-09-14 | 2024-03-21 | 华润微电子（重庆）有限公司 | Hemt contact hole structure and preparation method therefor |
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Application publication date: 20170118 |