CN114975640A - Staggered array Schottky type power device - Google Patents
Staggered array Schottky type power device Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/66196—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices with an active layer made of a group 13/15 material
- H01L29/66204—Diodes
- H01L29/66212—Schottky diodes
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
Abstract
The invention discloses a staggered array Schottky type power device, which mainly solves the problem of high turn-on voltage of the conventional Schottky diode and comprises the following components: substrate (1), transition layer (2), barrier layer (3), passivation layer (4) above barrier layer (3) left side is provided with negative pole groove (5), the negative pole groove top is provided with negative pole (6), the right side of barrier layer (3) and passivation layer (4) is provided with N group array strip, every group array strip includes M left array piece (8) and M +1 right array piece (9), these left array piece (8) and right array piece (9) crisscross distribution, these array piece upper surfaces are provided with interconnect metal (10), be used for with each array piece parallel connection, the bottom of every array piece all is located transition layer (2). The invention has small starting voltage and large conduction current, and can be used as a basic device of a power electronic system.
Description
Technical Field
The invention belongs to the technical field of microelectronics, and particularly relates to a Schottky diode device which can be used for a power electronic system.
Technical Field
Schottky barrier diodes play a crucial role in power converters and inverters, since they only have the majority carriers involved in conduction and therefore do not have the problems of minority carrier lifetime and reverse recovery. With the development of power electronics technology, the operating frequency of the circuit is increased, and the performance of the schottky barrier diode must be improved in order to maintain high power conversion efficiency of the circuit. GaN materials have excellent properties such as high breakdown field strength, good thermal properties, and high electron mobility, and thus GaN schottky barrier diodes have received much attention from researchers in high power and high frequency applications. In recent years, a great deal of research work has been carried out at home and abroad on high-performance GaN schottky barrier diodes, and particularly, the lateral AlGaN/GaN schottky barrier diodes are widely researched due to the advantage that the lateral AlGaN/GaN schottky barrier diodes are compatible with the plane process of AlGaN/GaN high electron mobility transistors. The lateral AlGaN/GaN Schottky barrier diode is beneficial to realizing the monolithic integration of the Schottky barrier diode device and the high electron mobility transistor device, thereby reducing parasitic elements and increasing the flexibility of design.
The conventional AlGaN/GaN Schottky barrier diode has high turn-on voltage and small output current, and the efficiency and the output power of a power electronic circuit and a system are seriously limited. In order to improve the above-mentioned problems of the conventional lateral AlGaN/GaN Schottky Barrier diode, the references AlGaN/GaN Schottky Barrier Diodes With Selective Si Diffusion for Low on set Voltage and High Reverse Blocking, IEEE Electron devices Letters, vol.34, No.8, 2013, propose a lateral AlGaN/GaN Schottky Barrier diode With a recessed anode structure, as shown in fig. 1, which includes: the structure comprises a substrate 1, a transition layer 2, a barrier layer 3, a passivation layer 4, a cathode 5 and an anode 6; a passivation layer 4 is deposited above the barrier layer 3, a cathode 5 is deposited on the left side of the upper surface of the barrier layer 3, and a groove anode 6 is deposited on the right sides of the barrier layer 3 and the passivation layer 4, so that although the diode can reduce the turn-on voltage of the traditional AlGaN/GaN Schottky barrier diode to a certain extent, the turn-on voltage of the structure is still larger, and the groove anode 6 in the structure can cause the reduction of a current conduction path, thereby reducing the output current.
Disclosure of Invention
The present invention is directed to overcome the above-mentioned deficiencies in the prior art, and to provide a schottky device with staggered array to further reduce the turn-on voltage and obtain a larger output current.
In order to achieve the purpose, the technical scheme of the invention is as follows:
1. a staggered array schottky-type power device comprising, from bottom to top: substrate 1, transition layer 2, barrier layer 3, passivation layer 4, above the barrier layer 3, the left side of passivation layer 4 is provided with cathode slot 5, is provided with negative pole 6, its characterized in that above the cathode slot 5:
n groups of array strips are arranged on the right sides of the barrier layer 3 and the passivation layer 4, each group of array strips comprises M left array blocks 8 and M +1 right array blocks 9, the left array blocks 8 and the right array blocks 9 are distributed in a staggered mode, and the bottoms of the array blocks are located in the transition layer 2;
the upper surfaces of the left and right array blocks 8, 9 are provided with interconnection metal 10 for connecting the array blocks together.
Further, the substrate 1 is made of sapphire, silicon carbide, silicon or graphene.
Furthermore, each group of array strips is provided with M left array blocks 8 and M +1 right array blocks 9, each group of array strips is provided with 2M +1 array blocks, N groups of array strips are provided with N x (2M +1) array blocks in total, N is more than or equal to 1, and M is more than or equal to 2.
Further, the left array block 8 and the right array block 9 have the same shape, and the length a is greater than 0, and the width b is greater than 0.
Further, in the structures of the left array block 8 and the right array block 9, the longitudinal spacing between adjacent array blocks is equal, the minimum longitudinal spacing c is greater than 0, and the spacing c is smaller than the width b of the array block; in the structures of the left array block 8 and the right array block 9, the transverse spacing of the adjacent array blocks is equal, and the minimum spacing d is greater than 0.
Further, the thickness e of the barrier layer 3 is 3nm to 100 nm; the thickness f of the passivation layer 4 is 5 nm-1000 nm; the N (2M +1) array blocks have the same height g, g > e + f.
2. The invention discloses a method for manufacturing a staggered array Schottky type power device, which comprises the following steps:
A) extending GaN semiconductor material on a substrate 1 to form a transition layer 2;
B) extending GaN-based wide bandgap semiconductor material on the transition layer 2 to form a barrier layer 3;
C) depositing an insulator on the barrier layer 3 to form a passivation layer 4;
D) manufacturing a mask on the passivation layer 4 for the first time, etching the left side of the passivation layer 4 by using the mask until the upper surface of the barrier layer 3 is etched to form a cathode slot 5;
E) making masks on the passivation layer 4 and the cathode slot 5 for the second time, depositing metal on the cathode slot 5 and the passivation layer 4 by using the masks, and performing rapid thermal annealing to form a cathode 6;
F) a mask is made on the passivation layer 4 and the cathode 6 for the third time, etching is carried out on the right side of the passivation layer 4 by using the mask until the etching is carried out below the lower surface of the barrier layer 3, and N x (2M +1) array grooves 7 are formed;
G) and manufacturing a mask on the passivation layer 4, the cathode 6 and the array groove 7 for the fourth time, and depositing metal above the array groove 7 by using the mask to form a left array block 8, a right array block 9 and interconnection metal 10, thereby completing the manufacture of the whole device.
Compared with a groove anode transverse AlGaN/GaN Schottky barrier diode device, the device has the following advantages:
1. the device adopts the anode structure distributed in an array, and a plurality of array blocks form a parallel connection relationship through the interconnection metal 10, so that the voltage drop applied to the anode end during conduction is reduced, and the starting voltage of the device is reduced.
2. Because the device adopts the structure of the plurality of array blocks, when positive voltage is applied to the anode of the device, current carriers can flow in from the edges of the M left array blocks 8 and the M +1 right array blocks 9, and compared with a single groove anode device, the current contact area of the device is increased, so that the efficiency of the current carriers for tunneling through a Schottky barrier is improved, and the on-state current can be increased while the turn-on voltage is reduced.
Drawings
FIG. 1 is a diagram of a prior art trench anode AlGaN/GaN Schottky barrier diode;
fig. 2 is a top view of a staggered array schottky type power device of the present invention;
FIG. 3 is a cross-sectional view of the device of the present invention taken along line AA' of the top view of FIG. 2;
FIG. 4 is a cross-sectional view of the device of the present invention taken along line BB' of the top view of FIG. 2;
FIG. 5 is a schematic flow chart of an implementation of the method for manufacturing a staggered array Schottky type power device according to the present invention;
fig. 6 is a graph of forward conduction output characteristics simulating the device of the present invention and a prior art recessed anode schottky barrier diode.
Detailed Description
Embodiments and effects of the present invention are described in further detail below with reference to the accompanying drawings.
Referring to fig. 2, 3 and 4, the staggered array schottky type power device of the present example includes: the structure comprises a substrate 1, a transition layer 2, a barrier layer 3, a passivation layer 4, a cathode slot 5, a cathode 6, a left array block groove 7, a right array block groove 8, an anode slot 9, a left array block 10, a right array block 11, a groove anode 12 and an interconnection metal 13. Wherein:
the substrate 1 is made of sapphire, silicon carbide, silicon or graphene;
the transition layer 2 is positioned on the upper part of the substrate 1, the thickness of the transition layer is 3-100 mu m, and the doping concentration is 1 multiplied by 10 15 ～1×10 18 cm -3 ；
The barrier layer 3 is positioned on the upper part of the transition layer 2 and is composed of a plurality of layers of same or different GaN-based wide bandgap semiconductor materials, and the thickness e of the barrier layer is 3 nm-100 nm;
the passivation layer 4 is arranged on the barrier layer3 upper part of SiO 2 、SiN、Al 2 O 3 、Sc 2 O 3 、HfO 2 、TiO 2 Any one of the above materials or other insulating dielectric materials, the thickness f is 5 nm-1000 nm;
the cathode slot 5 is positioned on the left side of the passivation layer 4, and the lower surface of the cathode slot is in contact with the barrier layer 3;
the cathode 6 is positioned at the upper part of the cathode slot 5, and the cathode 6 forms good ohmic contact with a semiconductor below;
the array groove 7 is positioned on the right side of the passivation layer 4 and the barrier layer 3, the lower part of the array groove 7 is positioned in the transition layer 2, the heights g of the array groove are the same, and g is greater than f + e;
the left array block 8 and the right array block 9 are positioned at the upper part of the array groove 7, the array blocks and the surrounding semiconductors form Schottky contact, the shape of each array block is equal, the length a is greater than 0, and the width b is greater than 0; the device structure is provided with N groups of array strips, each group of array strips comprises M left array blocks 8 and M +1 right array blocks 9, the left array blocks 8 and the right array blocks 9 are distributed in a staggered mode, and the bottoms of the array blocks are located in the transition layer 2; the array blocks are equal to the adjacent array blocks in longitudinal spacing, the minimum longitudinal spacing c is greater than 0, and c is less than b; the array blocks are equal to the adjacent array blocks in transverse distance, and the minimum distance d is greater than 0;
the interconnection metal 9 is located on the upper surfaces of the left array block 8 and the right array block 9, and the interconnection metal connects the array blocks in parallel to reduce the voltage drop on the array block structure when the array blocks are conducted in the forward direction.
Referring to fig. 5, the process of the present invention for fabricating a staggered array schottky type power device is as follows.
The first embodiment is as follows: the manufacturing method comprises the steps of manufacturing a staggered array Schottky type power device, wherein the thickness e of a barrier layer is 3nm, the thickness f of a passivation layer 4 is 5nm, the height g of an array block is 17nm, the staggered array Schottky type power device comprises 1 group of array strips consisting of a left array block 8 and two right array blocks 9, the length a of the array block is 5 micrometers, the width b of the array block is 8 micrometers, the longitudinal distance c between the array block and the adjacent array block is 5 micrometers, and the transverse distance d between the array block and the adjacent array block is 3 micrometers.
Using metal organic chemical vapor deposition technology, setting the temperature at 950 ℃, the pressure at 40Torr and using SiH 4 Is a doping source, the hydrogen flow is 4000sccm, the ammonia flow is 4000sccm, the gallium source flow is 100 mu mol/min, the epitaxial thickness on the sapphire substrate 1 is 1 mu m, the doping concentration is 1 multiplied by 10 15 cm -3 N of (A) to (B) - And a type GaN transition layer 2.
Using molecular beam epitaxy technique, setting vacuum degree to be less than or equal to 1.0 × 10 -10 mbar, radio frequency power of 400W, and N as reactant 2 High purity Ga source, high purity Al source, epitaxial growth of Al with thickness e of 3nm on GaN transition layer 2 0.5 Ga 0.5 N material forming the barrier layer 3.
Setting N using plasma enhanced chemical vapor deposition technique 2 O flow rate of 850sccm, SiH 4 Depositing SiO on the barrier layer 3 under the process conditions of the flow of 200sccm, the temperature of 250 ℃, the RF power of 25W and the pressure of 1100mTorr 2 To produce a passivation layer 4 having a thickness f of 5 nm.
And 4, manufacturing a cathode slot 5 as shown in figure 5 d.
Making a mask on the upper part of the passivation layer 4 for the first time, setting Cl by using a reactive ion etching technology 2 Etching the left side of the passivation layer 4 by using the mask under the process conditions of 15sccm, 10mTorr of pressure and 100W of power until the upper surface of the barrier layer 3 to form the cathode slot 5.
And 5, manufacturing the cathode 6, as shown in fig. 5 e.
Making a mask on the passivation layer 4 and the upper part of the cathode slot 5 formed by etching for the second time, and setting the vacuum degree to be 1.8 multiplied by 10 - 3 Pa, power 350W, evaporation rate
By electron beam evaporationDepositing metal on the upper part of the etched table top, wherein the deposited metal is a Ti/Au/Ni metal combination, namely Ti, Au and Ni are respectively deposited from bottom to top, and the thicknesses of the deposited metal are 0.02 mu m, 0.3 mu m and 0.05 mu m in sequence; and then setting the process conditions of 850 ℃ and 35s, and carrying out rapid thermal annealing on the deposited metal to finish the manufacture of the cathode 6.
And 6, manufacturing an array groove 7 as shown in fig. 5 f.
Making a mask on the upper parts of the cathode 6 and the passivation layer 4 for the third time, and setting Cl 2 And etching the right side of the passivation layer 4 by using the mask under the process conditions of 15sccm, 10mT of pressure and 100W of power, wherein the etching depth is 17nm, and 3 array grooves 7 are formed by etching at the same time.
Step 7. make three array blocks and interconnect metal 9, as in fig. 5 g.
Making a mask on the upper parts of the cathode 6, the passivation layer 4 and the array groove 7 for the fourth time, and setting the vacuum degree to be less than or equal to 1.6 multiplied by 10 -3 Pa, power set at 350W, evaporation rate at
And (3) depositing metal on the upper part of the array groove 7 by using the mask and adopting an electron beam evaporation technology, wherein the deposited metal is Ni, the thickness is 0.207 mu m, manufacturing Schottky contact, and forming a group of array strips and interconnection metal 9, wherein in each group of array strips, the number of left array blocks 8 is 1, and the number of right array blocks 9 is 2, and finishing the manufacture of the device.
Example two: the manufacturing method comprises the steps of manufacturing a staggered array Schottky type power device, wherein the thickness e of a barrier layer is 50nm, the thickness f of a passivation layer 4 is 500nm, the height g of an array block is 700nm, the staggered array Schottky type power device is provided with two groups of array strips, each group of array strips comprises two left array blocks 8 and three right array blocks 9, the length a of each array block is 3 micrometers, the width b of each array block is 5 micrometers, the longitudinal distance c between each array block and the adjacent array block is 2 micrometers, and the transverse distance d between each array block and the adjacent array block is 1 micrometer.
Step one, a transition layer 2 is manufactured, as shown in fig. 5 a.
And (3) performing epitaxial growth of a GaN material with the thickness of 4.9 mu m on the silicon carbide substrate 1 by using a metal organic chemical vapor deposition technology under the process conditions of the temperature of 1000 ℃, the pressure of 45Torr, the hydrogen flow of 4600sccm, the ammonia flow of 4600sccm and the gallium source flow of 120 mu mol/min to finish the manufacture of the transition layer 2.
Step two, epitaxial Al 0.1 Ga 0.9 N, the barrier layer 3 is produced, as shown in fig. 5 b.
Using molecular beam epitaxy technique, setting vacuum degree to be less than or equal to 1.0 × 10 -11 mbar, radio frequency power of 420W, and N as reactant 2 High purity Ga source, high purity Al source, epitaxial growth of Al with thickness of 50nm on GaN transition layer 2 0.1 Ga 0.9 And N material, and finishing the manufacture of the barrier layer 3.
Step three, depositing SiO 2 And a passivation layer 4 is fabricated, as shown in fig. 5 c.
Setting N using plasma enhanced chemical vapor deposition technique 2 O flow rate of 850sccm, SiH 4 Depositing SiO on the barrier layer 3 under the process conditions of the flow of 200sccm, the temperature of 250 ℃, the RF power of 25W and the pressure of 1100mTorr 2 To produce a passivation layer 4 having a thickness of 500 nm.
Step four, manufacturing the cathode slot 5 as shown in fig. 5 d.
Making a mask on the upper part of the passivation layer 4 for the first time, setting Cl by using a reactive ion etching technology 2 Etching the left side of the passivation layer 4 by using the mask under the process conditions of the flow of 15sccm, the pressure of 10mTorr and the power of 110W until the upper surface of the barrier layer 3 is etched to form the cathode slot 5.
Step five, manufacturing the cathode 6 as shown in fig. 5 e.
Making a mask on the passivation layer 4 and the etched cathode trench 5 for the second time, depositing metal on the etched cathode trench 5 by electron beam evaporation, and setting the vacuum degree to be less than 1.8 × 10 -3 Pa, power 400W, evaporation rate
The process conditions of (1) are that a metal combination Ti/Al/Ni/Au is deposited on the cathode slot 5, namely Ti, Al, Ni and Au are respectively deposited from bottom to top, and the thicknesses of the metal combinations are 0.02 mu m, 0.14 mu m, 0.055 mu m and 0.04 mu m in sequence5 μm; then, rapid thermal annealing was performed at 860 ℃ for 30 seconds, thereby completing the fabrication of the cathode 6.
Step six, manufacturing the array groove 7, as shown in fig. 5 f.
Making mask on the upper parts of the cathode 6 and the passivation layer 4 for the third time, adopting reactive ion etching technology, and setting Cl 2 And etching the right side of the passivation layer 4 by using the mask under the process conditions of 15sccm, 10mTorr of pressure and 110W of power, wherein the etching depth is 700nm, and ten array grooves 7 are formed.
Step seven. make array block and interconnect metal 9, as in fig. 5 g.
Making a mask on the cathode 6, the passivation layer 4 and the upper part of the array groove 7 for the fourth time, adopting an electron beam evaporation technology, and setting the vacuum degree to be 1.6 multiplied by 10 -3 Pa, power 350W, evaporation rate
The metal Wu is deposited on the upper part of the array groove 7 to manufacture Schottky contact, 2 groups of array strips and interconnection metal 9 are formed, wherein each group of array strips comprises two left array blocks 8 and three right array blocks 9, and the manufacture of the whole device is completed.
Example three: the staggered array Schottky type power device is manufactured, wherein the thickness e of a barrier layer is 100nm, the thickness f of a passivation layer 4 is 1000nm, the height g of an array block is 1.5 mu m, the staggered array Schottky type power device is provided with three groups of array strips, each group of array strips comprises three left array blocks 8 and four right array blocks 9, the length a of each array block is 1 mu m, the width b of each array block is 1 mu m, the longitudinal distance c between each array block and the adjacent array block is 0.5 mu m, and the transverse distance d between each array block and the adjacent array block is 0.5 mu m.
Step a. make the transition layer 2, as in fig. 5 a.
The temperature is 950 ℃, the pressure is 40Torr, and SiH is adopted 4 Is a doping source with hydrogen flow of 4000sccm, ammonia flow of 4000sccm and gallium source flow of 100 mu mol/min, and is prepared by epitaxially growing on a silicon substrate 1 to a thickness of 3 mu m and a doping concentration of 1 × 10 18 cm -3 N of (A) to (B) - And a type GaN transition layer 2.
Step B, epitaxial Al 0.01 Ga 0.99 N, the barrier layer 3 is produced, as shown in fig. 5 b.
The vacuum degree is less than or equal to 1.0 multiplied by 10 -10 mbar, radio frequency power of 400W, and N as reactant 2 High-purity Ga source and high-purity Al source, and epitaxial growth of Al with a thickness of 100nm on the GaN transition layer 2 by using molecular beam epitaxy technology 0.01 Ga 0.99 N material forming the barrier layer 3.
Step C, depositing SiO 2 And a passivation layer 4 is fabricated, as shown in fig. 5 c.
The temperature was set at 250 deg.C, RF power at 25W, and pressure at 1100mTorr, N 2 O flow rate of 850sccm, SiH 4 Depositing SiO on the barrier layer 3 by using the plasma enhanced chemical vapor deposition technology under the process condition of the flow rate of 200sccm 2 To produce a passivation layer 4 having a thickness of 1000 nm.
Step D, manufacturing the cathode slot 5 as shown in FIG. 5 d.
Making a mask on the upper part of the passivation layer 4 for the first time by using Cl 2 Etching the left side of the passivation layer 4 by using a reactive ion etching technology under the process conditions of 15sccm, 10mTorr of pressure and 100W of power until the upper surface of the barrier layer 3 to form the cathode slot 5.
Step e. make cathode 6, as in fig. 5 e.
Making a mask on the passivation layer 4 and the upper part of the cathode slot 5 formed by etching for the second time, wherein the vacuum degree is less than 1.8 multiplied by 10 - 3 Pa, power of 500W, evaporation rate of
Depositing metal on the upper part of the etched cathode slot 5 by using an electron beam evaporation technology, wherein the deposited metal is a Ti/Al/Mo/Au metal combination, namely Ti, Al, Mo and Au are respectively from bottom to top, and the thicknesses of the deposited metal are 0.02 mu m, 0.1 mu m, 0.03 mu m and 0.03 mu m in sequence; and (3) carrying out rapid thermal annealing by adopting the process conditions of 860 ℃ and 30s to finish the manufacture of the cathode 6.
Step f, making the array groove 7 as shown in fig. 5 f.
Making a mask on the cathode 6 and the passivation layer 4 for the third time, using CF 4 The flow rate was 45sccm, O 2 And etching the right side position of the passivation layer 4 by using a reactive ion etching technology under the process conditions of 5sccm of flow rate, 15mTorr of pressure and 300W of power to form twenty-one array grooves 7 with the depth of 1.5 mu m.
Step g. make array block and interconnect metal 9, as in fig. 5 g.
Making a mask on the cathode 6, the passivation layer 4 and the upper part of the array groove 7 for the fourth time, and setting the vacuum degree to be 1.6 multiplied by 10 -3 Pa, power 350W, evaporation rate
The process conditions of the method are that an electron beam evaporation technology is adopted, Mo metal is deposited on the upper portion of the array groove 7 through the mask to make Schottky contact, three groups of array strips and interconnection metal 9 are formed, wherein the number of the left array blocks is 8, the number of the right array blocks is four, and the whole device is manufactured.
In order to verify the effect of the present invention, forward conduction output characteristic simulations were performed on the conventional trench anode AlGaN/GaN schottky barrier diode and the device according to the second embodiment of the present invention, respectively, and the results are shown in fig. 6. As can be seen from fig. 6, the turn-on voltage of the device of the present invention is 0.25V, and the turn-on voltage of the conventional trench anode AlGaN/GaN schottky barrier diode is 0.9V. The turn-on voltage of the device is obviously lower than that of the prior art, and meanwhile, compared with the prior art, the output current of the device is obviously increased.
Claims (10)
1. A staggered array schottky-type power device comprising, from bottom to top: substrate (1), transition layer (2), barrier layer (3), passivation layer (4) left side above barrier layer (3) is provided with negative pole groove (5), is provided with negative pole (6) above negative pole groove (5), its characterized in that:
n groups of array strips are arranged on the right sides of the barrier layer (3) and the passivation layer (4), each group of array strips comprises M left array blocks (8) and M +1 right array blocks (9), the left array blocks (8) and the right array blocks (9) are distributed in a staggered mode, and the bottoms of the array blocks are located in the transition layer (2);
and the upper surfaces of the left array block (8) and the right array block (9) are provided with interconnection metal (10) for connecting the array blocks in parallel.
2. Device according to claim 1, characterized in that the substrate (1) is of sapphire or silicon carbide or silicon or graphene material.
3. The device of claim 1, wherein:
each group of array strips is provided with M left array blocks (8) and M +1 right array blocks (9), each group of array strips is provided with 2M +1 array blocks, N groups of array strips are provided with N x (2M +1) array blocks in total, N is more than or equal to 1, and M is more than or equal to 2.
4. The device of claim 1, wherein: the left array block (8) and the right array block (9) are the same in shape, the length a is larger than 0, and the width b is larger than 0.
5. The device of claim 1, wherein:
in the structures of the left array block (8) and the right array block (9), the longitudinal distances between adjacent array blocks are equal, and the minimum longitudinal distance c is greater than 0 and smaller than the width b of the array block;
in the structures of the left array block (8) and the right array block (9), the transverse distance between the adjacent array blocks is equal, and the minimum distance d is more than 0.
6. The device of claim 1, wherein:
the thickness e of the barrier layer (3) is 3 nm-100 nm;
the thickness f of the passivation layer (4) is 5 nm-1000 nm;
the left array block (8) and the right array block (9) have the same height g, and g is larger than e + f.
7. A manufacturing method of a staggered array Schottky type power device comprises the following steps:
A) epitaxial growth of GaN semiconductor material on a substrate (1) to form a transition layer (2);
B) a GaN-based wide bandgap semiconductor material is extended on the transition layer (2) to form a barrier layer (3);
C) depositing an insulator on the barrier layer (3) to form a passivation layer (4);
D) manufacturing a mask on the passivation layer (4) for the first time, etching the left side of the passivation layer (4) by using the mask until the upper surface of the barrier layer (3) is etched to form a cathode groove (5);
E) manufacturing masks on the passivation layer (4) and the cathode slot (5) for the second time, depositing metal above the cathode slot (5) and the passivation layer (4) by using the masks, and performing rapid thermal annealing to form a cathode (6);
F) making a mask on the passivation layer (4) and the cathode (6) for the third time, etching the right side of the passivation layer (4) by using the mask until the etching is below the lower surface of the barrier layer (3), and forming N x (2M +1) array grooves (7);
G) and manufacturing a mask on the passivation layer (4), the cathode (6) and the array groove (7) for the fourth time, and depositing metal above the array groove (7) by using the mask to form a left array block (8), a right array block (9) and interconnection metal (10), thereby completing the manufacture of the whole device.
8. The method of claim 7, wherein: the epitaxial technique used in the steps A) and B) comprises the following steps: chemical vapor deposition method, molecular beam epitaxy method.
9. The method of claim 7, wherein: the metal deposition process used in the steps E) and G) is electron beam evaporation, and the process conditions are as follows: vacuum degree less than 1.8X 10 -3 Pa, power range of 200-1000W, evaporation rate less than
10. The method of claim 7, wherein: the process conditions of the rapid thermal annealing used in the step E) are as follows: the temperature is set to 800-1000 ℃, and the time is set to 25-40 s.
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| CN202210580516.2A CN114975640A (en) | 2022-05-25 | 2022-05-25 | Staggered array Schottky type power device |
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