CN115000167A - Power switch device based on array Schottky leakage - Google Patents
Power switch device based on array Schottky leakage Download PDFInfo
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
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Abstract
The invention discloses a power switch device based on array Schottky leakage, which mainly solves the problems of high turn-on voltage and limited blocking capability of the existing device and comprises the following components: the device comprises a substrate, a transition layer, a barrier layer and a passivation layer, wherein a source groove and a source are arranged on the left side of the passivation layer; the right sides of the barrier layer and the passivation layer are M groups of array strips, each group of array strips comprises N left array blocks and (N +1) right array blocks, the left array blocks and the right array blocks are distributed in a staggered mode, and the bottoms of the array blocks are positioned in the transition layer; the upper side of the array blocks is provided with interconnection metal; a groove is formed in the passivation layer between the source electrode and the leftmost array strip, and a P-type block, an i-GaN block and a grid electrode are arranged in the groove from bottom to top; the source electrode, the grid electrode, the M groups of array strips and the interconnection metal form a HEMT structure, the M groups of array strips, the barrier layer and the passivation layer which are contacted with the M groups of array strips form a diode structure, and the HEMT and the diode form a bidirectional voltage-resistant device. The invention has low starting voltage and good blocking characteristic, and can be used for power electronic systems.
Description
Technical Field
The invention belongs to the technical field of microelectronics, and particularly relates to a power switch device which can be used for a power electronic system.
Technical Field
In a current-mode inverter circuit, devices on a bridge arm are often required to flow a unidirectional current, and a voltage resistance is required in the reverse direction. With the development of power electronic technology, the operating frequency of the circuit is increased, and in order to ensure that such a circuit still has high power conversion efficiency, the performance of each element on the bridge arm must be improved. With the development of the third generation semiconductor materials, GaN is gradually receiving attention from researchers. Compared with the conventional Si material, the GaN material has excellent characteristics such as high breakdown field strength, good thermal characteristics, high electron mobility and the like, and thus is increasingly applied to occasions such as high power and high frequency. Although GaN-based power devices have been developed more rapidly in recent years, conventional GaN HEMT devices have no reverse blocking capability and the devices fail at a lower drain reverse voltage. The current solution is usually to connect a discrete diode protection transistor externally to the drain, which significantly increases the on-state power loss, parasitic components, system volume and production cost.
It includes from bottom to top of traditional HEMT device: the device comprises a substrate, a transition layer and a barrier layer, wherein a source electrode and a drain electrode are respectively arranged on the left side and the right side of the upper part of the barrier layer, a P-type block is arranged on one side, close to the source electrode, of the upper part of the barrier layer, and a grid electrode is arranged on the upper part of the P-type block. The bidirectional blocking device is formed by using a traditional structure, and only a Schottky diode can be connected in series outside, so that a large parasitic effect is brought, the occupied area is large, and monolithic integration is difficult to realize. In order to improve the problems of the conventional structure, a groove SBD structure is proposed in the document AlGaN/GaN HEMT With Integrated processed Schottky-Drain Protection Diode, IEEE Electron Device Letters, vol.30, No.9, pp.901-903,2009. The conventional HEMT device is formed by embedding a groove SBD drain structure in a conventional HEMT device, as shown in FIG. 1, the HEMT device is provided with a substrate, a transition layer, a barrier layer, a P-type block and a grid from bottom to top, the left side of the upper part of the barrier layer is provided with ohmic contact, the upper part of the ohmic contact is provided with a source electrode, the barrier layer and the right side of the transition layer are provided with Schottky contact, the upper part of the Schottky contact is provided with a drain electrode, and the upper part of the whole device except the source electrode, the grid electrode and the drain electrode is provided with a passivation layer for covering. The device preparation process is compatible with the traditional GaN-based HEMT device process, and can realize bidirectional voltage resistance, but the device structure has the defects of high forward starting voltage drop and small forward output current. In order to further reduce the forward turn-on voltage drop of the device, a groove schottky junction ohmic drain structure is proposed in documents uni-directional AlGaN/GaN-on-Si HFETs with reverse blocking drain, Applied Physics Express,7(1),2014, so that the forward turn-on voltage drop of the device is 0.4V, but the forward turn-on voltage drop of the device is still to be further reduced, and the bidirectional blocking capability of the device is very limited.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provide a power switch device based on an array schottky drain, so that the turn-on voltage drop is obviously reduced, the threshold voltage and the forward output current of the device are improved, the bidirectional blocking capability is further improved, and the monolithic integration is realized.
In order to achieve the purpose, the technical scheme of the invention is as follows:
1. a power switch device based on array Schottky leakage comprises from bottom to top: substrate 1, transition layer 2, barrier layer 3 and passivation layer 4, its characterized in that:
a source electrode groove 5 is arranged on the left side of a passivation layer 4 on the upper part of the barrier layer 3, and a source electrode 6 is arranged in the source electrode groove 5;
the right sides of the barrier layer 3 and the passivation layer 4 are sequentially provided with a 1 st group of array strips and a 2 nd group of array strips … Mth group of array strips from left to right, each group of array strips comprises N parallel left array blocks 8 arranged at equal intervals and N +1 parallel right array blocks 9 arranged at equal intervals, wherein the left array blocks 8 and the right array blocks 9 are distributed in a staggered manner, and the bottoms of the array blocks are positioned in the transition layer 2;
the upper surfaces of the left array block 8 and the right array block 9 are provided with interconnection metal 10 for connecting the array blocks in parallel;
a groove 11 is formed in the passivation layer 4 between the source electrode 6 and the left side of the first group of array strips, and a P-type block 12, an i-GaN block 13 and a grid 14 are sequentially arranged in the groove from bottom to top;
the source electrode 6, the grid electrode 14, the M groups of array strips on the right side and the interconnection metal 10 form a HEMT structure, a diode structure is formed between the M groups of array strips and the barrier layer 3 and the passivation layer 4 which are in contact with the array strips, and the HEMT and the diode form a bidirectional voltage-resistant device.
Further, the substrate 1 is made of silicon carbide or silicon or sapphire or graphene.
Further, the thickness e of the barrier layer 3 is 3nm to 100nm, and the Al component is 0.1 to 0.4.
Further, the passivation layer 4 is made of SiO 2 、Al 2 O 3 、HfO 2 、Si 3 N 4 、TiO 2 Of any one of the above or other insulating dielectric materials, and the thickness f is 20nm to 1000 nm.
Furthermore, each group of array strips is provided with N left array blocks 8 and N +1 right array blocks 9, namely each group of array strips is provided with (2N +1) array blocks, M groups of array strips are provided with M x (2N +1) array blocks, wherein M is more than or equal to 1, and N is more than or equal to 2.
Further, the left array block 8 and the right array block 9 are rectangular blocks, the length a is greater than 0, and the width b is greater than 0; the longitudinal distance between two adjacent left array blocks 8 and the longitudinal distance between two adjacent right array blocks 9 are both c, c is greater than 0 and is less than b; in each group of array strips, the transverse spacing d between the left array block 8 and the right array block 9 is equal, and d is greater than 0.
Further, the left array block 8 and the right array block 9 have the same height, and are g, g > e + f, where e and f are the thicknesses of the barrier layer 3 and the passivation layer 4, respectively.
Furthermore, the P-type block 12 is made of P-GaN or CuO or NiO, the thickness of the P-type block is 10nm to 500nm, and the doping concentration of the P-type block is 5 multiplied by 10 15 cm -3 ～1×10 22 cm -3 (ii) a The thickness of the i-GaN block 13 is 10nm to 500 nm.
Further, ohmic contact is formed between the source electrode 6 and the barrier layer 3 in contact with the source electrode, and schottky contact is formed between the left array block 8 and the right array block 9 and between the transition layer 2 and the barrier layer 3 in contact with the source electrode.
2. The invention discloses a method for manufacturing a power switch device based on an array Schottky drain, which comprises the following steps:
A) extending GaN semiconductor material on a substrate 1 to form a transition layer 2;
B) extending GaN-based wide bandgap semiconductor material on the transition layer 2to form a barrier layer 3;
C) extending a dielectric material on the barrier layer 3 to form a passivation layer 4;
D) manufacturing a mask on the passivation layer 4 for the first time, etching the left side of the passivation layer 4 by using the mask until the upper surface of the barrier layer 3 is etched to form a source electrode groove 5;
E) manufacturing a mask on the passivation layer 4 and the source electrode groove 5 for the second time, depositing metal in the source electrode groove 5 by using the mask, and performing rapid thermal annealing to form a source electrode 6;
F) a mask is made on the passivation layer 4 and the source electrode 6 for the third time, etching is carried out on the right side of the passivation layer 4 by using the mask until the etching is carried out below the lower surface of the barrier layer 3, and M x (2N +1) array grooves 7 are formed;
G) making a mask on the passivation layer 4, the source electrode 6 and the array groove 7 for the fourth time, and depositing metal on the upper parts of the passivation layer 4 inside and on the right side of the array groove 7 by using the mask to form a left array block 8, a right array block 9 and interconnection metal 10;
H) making a mask on the passivation layer 4, the source electrode 6 and the interconnection metal 10 for the fifth time, etching the passivation layer 4 between the source electrode 6 and the left side of the first group of array strips by using the mask until the upper surface of the barrier layer 3 is etched to form a groove 11;
I) a mask is manufactured on the passivation layer 4, the source electrode 6, the interconnection metal 10 and the groove 11 for the sixth time, the thickness of the mask is 10nm to 500nm, the doping concentration is 5 multiplied by 10 15 cm -3 ～1×10 22 cm -3 A P-type block 12;
J) depositing an i-GaN block 13 with the thickness of 10 nm-500 nm on the upper part of the P-type block 12 by using the mask manufactured for the sixth time;
K) and manufacturing a mask on the passivation layer 4, the source electrode 6, the interconnection metal 10 and the i-GaN block 13 for the seventh time, and depositing metal on the upper part of the i-GaN block 13 by using the mask to form a grid electrode 14, thereby completing the manufacture of the whole device.
Compared with the prior device, the device of the invention has the following advantages:
1. the opening voltage drop is reduced, and the output current is increased.
The device adopts M groups of array strips, and each group of array strips consists of N left array blocks 8 and N +1 right array blocks 9. When a positive voltage is applied to the interconnection metal 10 of the device, the M groups of array strips on the lower side of the interconnection metal 10 are also at a high potential, when the gate is turned on, carriers can flow through the edges of each left array block 8 and each right array block 9, which is equivalent to increasing the contact area between a right electrode and electrons in a channel, and improving the efficiency of the carriers for tunneling through the Schottky barrier, thereby increasing the on-state current; and because the distributed array structure is adopted to replace the traditional large Schottky metal, the voltage drop of the anode end during conduction is reduced, and the turn-on voltage drop is reduced.
2. The threshold voltage is improved, and the reliability of the device is enhanced.
In the invention, the i-GaN block 13 is added on the P-type block 12, so that the threshold voltage of the device is regulated and controlled, and higher concentration of the P-type block 12 and lower work function contact metal are not needed any more than the original high threshold voltage; due to the fact that the i-GaN block 13 is added, the grid electrode 14 can be directly contacted with the i-GaN block 13, the height and the width of a contact potential barrier are increased, grid voltage shared by a potential barrier region can be increased, the requirement on the work function of grid electrode metal is lowered, namely the grid electrode only needs common metal, and therefore threshold voltage of the device is improved, and reliability of the device is improved.
3. Improving the bidirectional blocking capability.
The array electrode is added at the right end of the device, so that the forward and reverse blocking characteristics can be improved, and the method can be described as follows: when the source electrode 6 applies a low level and the M groups of array strips and the interconnection metal 10 apply a high level, the diode on the right side is in a forward bias state, and the grid electrode applies a zero potential at the moment, so that the communication of two-dimensional electron gas between the transition layer and the barrier layer is prevented, namely a channel for conducting the HEMT is not formed, the whole device cannot be conducted, and forward blocking is realized; when the source electrode 6 applies high level and the M groups of array strips and the interconnection metal 10 apply low level, no matter whether the grid is zero potential or not, because the diode on the right side can not be conducted in the forward direction, the flow of electrons is blocked, and the whole device is in a turn-off state, thereby realizing reverse blocking.
4. Monolithic integration is realized.
According to the invention, because the HEMT and the diode are integrated, an external diode is not needed when the HEMT is used, the area utilization rate of a chip is improved, and monolithic integration is realized.
Drawings
FIG. 1 is a block diagram of a prior art device;
fig. 2 is a cross-sectional view of an array schottky drain based power switching device of the present invention;
fig. 3 is a top view of the array schottky drain based power switching device of the present invention;
FIG. 4 is a schematic flow chart of an implementation of the method for manufacturing a power switch device based on an array Schottky drain;
FIG. 5 is a graph of output characteristics obtained by simulation of a device of the present invention;
fig. 6 is a graph of blocking characteristics obtained by simulation of the device of the present invention.
Detailed Description
Embodiments and effects of the present invention will be described in further detail below with reference to the accompanying drawings.
Referring to fig. 2 and 3, the power switching device based on the array schottky drain of the present embodiment includes: substrate 1, transition layer 2, barrier layer 3, passivation layer 4, source groove 5, source 6, array groove 7, left array piece 8, right array piece 9, interconnect metal 10, recess 11, P type piece 12, i-GaN piece 13, grid 14 and by the left array piece 8, the M group array strip that right array piece 9 constitutes, wherein:
the substrate 1 is made of silicon carbide or silicon or sapphire or graphene;
the transition layer 2 is positioned on the upper part of the substrate 1, the thickness of the transition layer is 3-100 mu m, and the doping concentration is 1 multiplied by 10 15 ～1×10 18 cm -3 ；
The barrier layer 3 is positioned on the upper part of the transition layer 2 and is composed of a plurality of layers of same or different GaN-based wide bandgap semiconductor materials, the thickness e of the barrier layer is 3 nm-100 nm, and the Al component of the barrier layer is 0.1-0.4. (ii) a
The passivation layer 4 is arranged on the barrier layer 3 and made of SiO 2 、Al 2 O 3 、HfO 2 、TiO 2 Any one of the above materials or other insulating dielectric materials, the thickness f is 20 nm-1000 nm;
the source electrode groove 5 is positioned on the left side of the passivation layer 4, and the lower surface of the source electrode groove is in contact with the barrier layer 3;
the source electrode 6 is positioned in the source electrode groove 5, and ohmic contact is formed between the source electrode 6 and the contacted barrier layer (3);
the array groove 7 is positioned on the right sides of the passivation layer 4 and the barrier layer 3, the lower part of the array groove 7 is positioned in the transition layer 2, the depths of the array groove 7 are g, g is greater than e + f, and e and f are the thicknesses of the barrier layer 3 and the passivation layer 4 respectively;
each group of M groups of array strips comprises N left array blocks 8 which are arranged in parallel at equal intervals and (N +1) right array blocks 9 which are arranged in parallel at equal intervals, namely each group of array strips comprises (2N +1) array blocks, the M groups of array strips have M x (2N +1) array blocks, the left array blocks 8 and the right array blocks 9 in each group of array strips are distributed in a staggered manner, the bottoms of the array blocks are positioned in the transition layer 2, M is more than or equal to 1, and N is more than or equal to 2;
the left array block 8 and the right array block 9 are both positioned in the array groove 7 and form Schottky contact with the transition layer 2 and the barrier layer 3 which are in contact with each other; each array block is a cuboid block, the length a is greater than 0, and the width b is greater than 0; the longitudinal distance between two adjacent left array blocks 8 and the longitudinal distance between two adjacent right array blocks 9 are both c, and c is less than b; in each group of array strips, the transverse distance d between the left array block 8 and the right array block 9 is equal, and d is greater than 0;
the interconnection metal 10 is positioned on the upper surfaces of the left array block 8 and the right array block 9, and the interconnection metal connects the left array block 8 and the right array block 9 in parallel so as to reduce the voltage drop on the array block structure when the array block structure is conducted in the forward direction;
the groove 11 is positioned in the passivation layer 4 between the source electrode 6 and the left side of the first array strip, and the lower end of the groove is positioned on the upper surface of the barrier layer 3;
the P-type block 12 is positioned in the groove 11, the thickness of the P-type block is 10 nm-500 nm, and the doping concentration is 5 multiplied by 10 15 cm -3 ～1×10 22 cm -3 Selecting P-GaN or CuO or NiO material;
the i-GaN block 13 is positioned inside the groove 11 and above the P-type block 12, and the thickness of the i-GaN block is 10 nm-500 nm;
the grid electrode 14 is positioned at the upper part of the i-GaN block 13, the length of the grid electrode is less than that of the i-GaN block 13, and Schottky contact is formed between the grid electrode and the i-GaN block 13;
the source electrode 6, the grid electrode 14, the M groups of array strips on the right side and the interconnection metal 10 form a High Electron Mobility Transistor (HEMT) structure, a diode structure is formed between the M groups of array strips and the barrier layer 3 and the passivation layer 4 which are contacted with the M groups of array strips, and the HEMT and the diode form a bidirectional voltage-resistant device.
Referring to fig. 4, the process of the present invention for fabricating a power switching device based on array schottky drain is as follows.
The first embodiment is as follows: the barrier layer is made on the silicon carbide substrate with the thickness e of 100nm, and the passivation layer 4 is made of SiO 2 The material has the thickness f of 1000nm, M is 4, N is 4, the height g of the array block is 1300nm, and the P-type block 15 is made of NiO material.
Step one, a transition layer 2 is manufactured, as shown in fig. 4 a.
And (3) performing epitaxial growth of a GaN material with the thickness of 6.9 mu m on the silicon carbide substrate 1 by using a metal organic chemical vapor deposition technology under the process conditions of the temperature of 1000 ℃, the pressure of 45Torr, the hydrogen flow of 4600sccm, the ammonia flow of 4600sccm and the gallium source flow of 120 mu mol/min to finish the manufacture of the transition layer 2.
Step two, epitaxial Al 0.1 Ga 0.9 N, the barrier layer 3 is produced, as shown in fig. 4 b.
Using molecular beam epitaxy technique under vacuum degree of 1.0 × 10 -11 mbar, radio frequency power of 420W, and N as reactant 2 Al with the thickness of 100nm is epitaxially grown on the GaN transition layer 2 under the process conditions of the high-purity Ga source and the high-purity Al source 0.1 Ga 0.9 And N material, and finishing the manufacture of the barrier layer 3.
Step three, depositing SiO 2 Material, making passivation layer 4, fig. 4 c.
Using plasma enhanced chemical vapor deposition techniques on N 2 O flow rate of 850sccm, SiH 4 Depositing SiO on the upper part of the barrier layer 3 under the process conditions of the flow of 200sccm, the temperature of 250 ℃, the RF power of 25W and the pressure of 1100mTorr 2 The material is used to make a passivation layer 4 with a thickness of 1000 nm.
Step four, manufacturing a source electrode groove 5 as shown in fig. 4 d.
A first mask is made on the upper part of the passivation layer 4, using the mask a reactive ion etching technique in Cl 2 Etching the left side of the passivation layer 4 until the upper surface of the barrier layer 3 is etched under the process conditions of the flow of 15sccm, the pressure of 10mTorr and the power of 110W to form a source groove 5.
And step five, manufacturing a source electrode 6 as shown in fig. 4 e.
Making a mask on the passivation layer 4 and the upper part of the source groove 5 for the second time, and performing electron beam evaporation in vacuum degree of less than 1.8 × 10 -3 Pa, power 400W, evaporation rate
Under the process conditions of (1), depositing a metal combination Ti/Al/Ni/Au in the source electrode groove 5, wherein the thicknesses of the metal combination Ti/Al/Ni/Au are 0.352 mu m, 0.174 mu m, 0.255 mu m and 0.345 mu m in sequence; then, N at 860 ℃ for 30s 2 In the atmosphere, rapid thermal annealing is performed to form the source electrode 6.
Step six, manufacturing the array groove 7, as shown in fig. 4 f.
Thirdly, a mask is manufactured on the upper parts of the passivation layer 4 and the source electrode 6, and the mask is utilized to perform the reactive ion etching technology on Cl 2 And etching the right side of the passivation layer 4 at the etching depth of 120nm under the process conditions of the flow of 15sccm, the pressure of 10mTorr and the power of 110W to form 4 multiplied by 9 array grooves 7.
Step seven, the array block and the interconnection metal 10 are fabricated as shown in fig. 4 g.
Making a mask on the passivation layer 4, the source electrode 6 and the upper part of the array groove 7 for the fourth time, and adopting an electron beam evaporation technology to ensure that the vacuum degree is 1.6 multiplied by 10 -3 Pa, power 350W, evaporation rate
Under the process conditions of (1), depositing metal W on the upper part of the array groove 7 to make Schottky contact, and forming four groups of array strips and interconnection metal 10; wherein each group of array strips comprises four left array blocks 8 and five right array blocks 9, and diode structures are formed between the barrier layers 3 and the passivation layers 4 which are contacted with the four groups of array strips.
Step eight, forming a groove 11 by etching, as shown in fig. 4 h.
Making a mask on the passivation layer 4, the source electrode 6 and the interconnection metal 10 for the fifth time, and using the mask to perform reactive ion etching on Cl 2 And etching the passivation layer 4 between the source electrode 6 and the left side of the first group of array strips under the process conditions of the flow of 15sccm, the pressure of 10mTorr and the power of 110W until the upper surface of the barrier layer 3 is etched to form a groove 11.
And step nine, manufacturing the P-type block 12 as shown in FIG. 4 i.
And (3) a mask is manufactured on the passivation layer 4, the source electrode 6, the interconnection metal 10 and the groove 11 for the sixth time, the magnetron sputtering technology is used for the mask, and the sputtering power is 110W, the temperature is 300 ℃, the Ar flow is 20sccm, O 2 Sputtering the substrate in the groove 11 at a thickness of 500nm and a doping concentration of 5 × 10 under a process condition of a flow of 30sccm 15 cm -3 Forming a P-type block 12.
Step ten, manufacturing an i-GaN block 13, as shown in FIG. 4 j.
And utilizing the mask manufactured for the sixth time, and adopting a metal organic chemical vapor deposition technology to deposit an undoped GaN material with the thickness of 500nm on the upper part of the P-type block 12 under the process conditions that the temperature is 500 ℃, the pressure is 46Torr, the hydrogen flow is 4300sccm, the ammonia flow is 4300sccm and the gallium source flow is 21 mu mol/min to form the i-GaN block 13.
Step eleven. deposit multiple layers of metal to form the gate 14, as shown in fig. 4 k.
Manufacturing a mask on the passivation layer 4, the source electrode 6, the interconnection metal 10 and the i-GaN block 13 for the seventh time, and sputtering the metal combination Ta/Au with the thickness of 0.25 mu m/0.35 mu m on the upper part of the i-GaN block 13 by utilizing the mask and adopting a sputtering technology under the process conditions that the sputtering pressure is 0.1Pa, the flow rate of Ar is 8sccm, the substrate temperature is fixed at 200 ℃ and the target radio frequency power is 150W to form a grid electrode 14; and (4) forming a High Electron Mobility Transistor (HEMT) structure by the source electrode 6, the grid electrode 14, the four groups of array strips on the right side and the interconnection metal 10, and forming a bidirectional voltage-resistant device by the HEMT and the diode formed in the step seven to finish the manufacture of the whole device.
Example two: the barrier layer is made on the sapphire substrate, the thickness e of the barrier layer is 3nm, and the passivation layer 4 is made of Al 2 O 3 The material has a thickness f of 20nm, M is 1, N is 3, the height g of the array block is 30nm, and the CuO material is selected as the P-type block 15.
Using metal organic chemical vapor deposition technology, the epitaxial thickness is 10 μm and the doping concentration is 1 × 10 on the sapphire substrate 1 15 cm -3 N of (A) to (B) - A GaN buffer layer 2;
the deposition process conditions are as follows: the temperature was 950 ℃ and the pressure was 40Torr, as SiH 4 The hydrogen flow is 4000sccm, the ammonia flow is 4000sccm, and the gallium source flow is 100 mu mol/min.
Using molecular beam epitaxy technique, epitaxially growing Al with a thickness e of 3nm on the GaN transition layer 2 0.4 Ga 0.6 N material, forming potentialA base layer 3;
the process conditions of molecular beam epitaxy are as follows: vacuum degree of 1.0X 10 or less -10 mbar, radio frequency power of 400W, and N as reactant 2 High-purity Ga source and high-purity Al source.
Depositing Al over the barrier layer 3 to a thickness of 20nm using atomic layer deposition 2 O 3 A material forming a passivation layer 4;
the deposition process conditions are as follows: the reaction sources are Trimethylaluminum (TMA) and deionized water, the reaction temperature is 300 ℃, the pressure of the reaction chamber is 5torr, and a single reaction period comprises 1.5s of trimethylaluminum gas introduction, 3s of nitrogen purging, 1s of deionized water steam introduction and 3s of nitrogen purging.
And 4, manufacturing a source electrode groove 5, as shown in fig. 4 d.
Manufacturing a mask on the upper part of the passivation layer 4 for the first time, etching the left side of the passivation layer 4 by using a reactive ion etching technology until the upper surface of the barrier layer 3 is etched to form a source electrode groove 5;
the etching process conditions are as follows: cl 2 The flow rate is 15sccm, the pressure is 10mTorr, and the power is 100W.
And 5, manufacturing a source electrode 6, as shown in fig. 4 e.
Making a mask on the passivation layer 4 and the upper part of the source groove 5 for the second time, and depositing metal inside the source groove 5 by using an electron beam evaporation technology, wherein the deposited metal is a Ti/Al/Mo/Au metal combination, and the thicknesses of the deposited metal are 0.007 mu m, 0.013 mu m, 0.005 mu m and 0.004 mu m in sequence; then carrying out rapid thermal annealing on the deposited metal to form a source electrode 6;
the process conditions of the electron beam evaporation are as follows: vacuum degree of 1.8X 10 -3 Pa, power 350W, evaporation rate
The process conditions of the rapid thermal annealing are as follows: n at a temperature of 850 DEG C 2 Atmosphere for 40 s.
And 6, manufacturing an array groove 7 as shown in figure 4 f.
A mask is manufactured on the upper portions of the passivation layer 4 and the source electrode 6 for the third time, the right side of the passivation layer 4 is etched by the mask, the etching depth is 30nm, and meanwhile, 1 × 7 array grooves 7 are formed through etching;
the etching process conditions are as follows: cl 2 The flow was 15sccm, the pressure was 10mT, and the power was 100W.
Manufacturing a mask on the passivation layer 4, the source electrode 6 and the upper part of the array groove 7 for the fourth time, and depositing metal on the passivation layer 4 inside the array groove 7 and on the right side by using the mask and adopting an electron beam evaporation technology, wherein the deposited metal is Ni, the thickness of the deposited metal is 0.047 mu m, and a group of array strips and interconnection metal 10 are formed; in the array strip, the number of the left array blocks is 8, and the number of the right array blocks is 9, wherein the number of the left array blocks is 3, and the number of the right array blocks is 4; the group of array strips forms a diode structure with the barrier layer 3 and the passivation layer 4 which are contacted with the array strips;
the deposition process conditions are as follows: vacuum degree less than or equal to 1.6 multiplied by 10 -3 Pa, power set at 350W, evaporation rate at
And 8, etching to form a groove 11, as shown in fig. 4 h.
A fifth mask is made on the passivation layer 4, the source electrode 6 and the interconnection metal 10, and a reactive ion etching technique is used to etch in Cl using the mask 2 And etching the passivation layer 4 between the source electrode 6 and the left side of the first group of array strips under the process conditions of the flow of 15sccm, the pressure of 10mTorr and the power of 110W until the upper surface of the barrier layer 3 is etched to form a groove 11.
And 9, manufacturing a P-type block 12 as shown in figure 4 i.
A mask is formed on the passivation layer 4, the source electrode 6, the interconnection metal 10 and the groove 11 for the sixth time, and magnetron sputtering is performed on the mask to form a film with a thickness of 10nm and a doping concentration of 1 × 10 in the groove 11 22 cm -3 Forming P-type blocks 12;
the technological conditions of sputtering are as follows: copper with a purity of 99.999%The sputtering gas is high-purity argon as target material, high-purity oxygen with the same purity is used as reaction gas, and the vacuum degree of the reaction chamber before sputtering is set to be 2.0 multiplied by 10 -4 Pa, keeping the flow rate of argon gas at 20sccm, the flow rate of oxygen gas at 10sccm, the pressure of the deposition chamber at 0.5Pa, the RF power at 35W, and the substrate temperature at 200 ℃.
Depositing an undoped GaN material with the thickness of 10nm on the upper part of the P-type block 12 by using the mask manufactured for the sixth time and adopting a metal organic chemical vapor deposition technology to form an i-GaN block 13;
the deposition process conditions are as follows: the temperature is 500 ℃, the pressure is 46Torr, the hydrogen flow is 4300sccm, the ammonia flow is 4300sccm, and the gallium source flow is 21 mu mol/min.
Step 11. deposit multi-layer metal to form the gate 14, as shown in fig. 4 k.
A mask is manufactured on the passivation layer 4, the source electrode 6, the interconnection metal 10 and the i-GaN block 13 for the seventh time, the electron beam evaporation technology is adopted by utilizing the mask, and the vacuum degree is less than 1.8 multiplied by 10 -3 Pa, power of 500W, evaporation rate of less than
Under the process conditions of (1), a metal combination Ni/Au with the thickness of 0.22 mu m/0.31 mu m is sputtered on the upper part of the i-GaN block 13 to form a grid electrode 14; and (3) forming a High Electron Mobility Transistor (HEMT) structure by the source electrode 6, the grid electrode 14, the group of array strips on the right side and the interconnection metal 10, and forming a bidirectional voltage-resistant device by the HEMT and the diode formed in the step (7) to finish the manufacture of the whole device.
Example three: the barrier layer is made on the silicon substrate with the thickness e of 30nm, and the passivation layer 4 is made of HfO 2 The thickness f of the material is 270nm, M is 5, N is 2, the height g of the array block is 660nm, and the GaN material is selected as the P-type block 15.
Step a. make the transition layer 2, as shown in fig. 4 a.
The temperature was set at 950 ℃ and the pressure at 40Torr as SiH 4 Is a doping source, the hydrogen flow is 4000sccm, the ammonia flow is 4000sccm, and the gallium source flow is 100 mu mol/minThe process conditions are that on the silicon substrate 1, the epitaxial thickness is 7 mu m and the doping concentration is 1 multiplied by 10 by utilizing the metal organic chemical vapor deposition technology 18 cm -3 N of (A) to (B) - And a type GaN transition layer 2.
Step B, epitaxial Al 0.15 Ga 0.85 N, the barrier layer 3 is produced, as shown in fig. 4 b.
Setting the vacuum degree to be less than or equal to 1.0 multiplied by 10 -10 mbar, radio frequency power of 400W, and N as reactant 2 High-purity Ga source and high-purity Al source, and epitaxial growth of 30 nm-thick Al on GaN transition layer 2 by molecular beam epitaxy 0.15 Ga 0.85 N material forming the barrier layer 3.
Step C, depositing HfO 2 And a passivation layer 4 is fabricated, as shown in fig. 4 c.
The sputtering pressure of the reaction chamber provided with the radio frequency magnetron reactive sputtering technology is kept at 0.1Pa, O 2 And Ar with the flow rate of 1sccm and 8sccm respectively, fixing the substrate temperature at 200 ℃, and depositing HfO with the thickness of 270nm on the barrier layer 3 by using a radio frequency magnetron reactive sputtering technology under the process condition that the radio frequency power of the Hf target is 150W 2 Material forming the passivation layer 4.
Step d, making the source trench 5, as shown in fig. 4 d.
Setting up Cl 2 The flow is 15sccm, the pressure is 10mTorr, the power is 100W, a mask is manufactured on the upper portion of the passivation layer 4 for the first time, the reactive ion etching technology is used, etching is carried out on the left side of the passivation layer 4 until the upper surface of the barrier layer 3 is etched, and the source electrode groove 5 is formed.
Step e. make source 6, as shown in fig. 4 e.
Setting the vacuum degree to be less than 1.8 multiplied by 10 -3 Pa, power of 500W, evaporation rate of
Making a mask on the upper parts of the passivation layer 4 and the source electrode groove 5 for the second time, and depositing metal in the source electrode groove 5 by using an electron beam evaporation technology, wherein the deposited metal is a Ti/Au/Ni metal combination, and the thicknesses of the metal are 0.125 mu m, 0.083 mu m and 0.153 mu m in sequence; and at a temperature of 860 ℃ of N 2 In the atmosphere, inAnd (5) performing rapid thermal annealing for 30s to complete the manufacture of the source electrode 6.
Step f. make array slot 7, as in fig. 4 f.
Setting CF 4 The flow rate was 45sccm, O 2 And under the process conditions of 5sccm flow, 15mTorr pressure and 300W power, a mask is manufactured on the upper parts of the passivation layer 4 and the source electrode 6 for the third time, and the right side position of the passivation layer 4 is etched by using a reactive ion etching technology to form 5 multiplied by 5 array grooves 7 with the depth of 660 nm.
Step g. make array block and interconnect metal 10, as in fig. 4 g.
The vacuum degree was set to 1.6X 10 -3 Pa, power 350W, evaporation rate
The process conditions of (1) manufacturing a mask for the fourth time on the passivation layer 4, the source electrode 6 and the upper part of the array groove 7, and depositing metal Mo on the upper parts of the passivation layer 4 on the inner part and the right side of the array groove 7 by using the mask to manufacture Schottky contact by adopting an electron beam evaporation technology to form five groups of array strips and interconnection metal 10; the number of the left array blocks 8 in each group of array strips is two, the number of the right array blocks 9 in each group of array strips is three, and diode structures are formed between the five groups of array strips and the barrier layers 3 and the passivation layers 4 which are in contact with the five groups of array strips.
Step h. etch to form the recess 11, as shown in fig. 4 h.
Setting up Cl 2 And manufacturing a mask on the passivation layer 4, the source electrode 6 and the interconnection metal 10 for the fifth time under the process conditions that the flow is 15sccm, the pressure is 10mTorr and the power is 110W, etching the passivation layer 4 between the source electrode 6 and the left side of the first group of array strips by utilizing the mask and adopting a reactive ion etching technology until the upper surface of the barrier layer 3 is etched, and forming the groove 11.
Step i. make P-type block 12, as in fig. 4 i.
Setting the technological conditions of 950 deg.c, 42Torr pressure, 4100sccm hydrogen flow, high purity Mg source as dopant, 4100sccm ammonia flow and 100 micromole/min gallium source flow, and making mask on the passivation layer 4, the source 6, the interconnection metal 10 and the notch 11, and utilizing the mask to use metal organic compoundThe mechanochemical vapor deposition technique deposits the silicon nitride with the thickness of 170nm and the doping concentration of 6 multiplied by 10 in the groove 11 19 cm -3 Forming a P-type block 12.
Step J. make i-GaN block 13, as in FIG. 4 j.
Setting the process conditions of 500 ℃ of temperature, 46Torr of pressure, 4300sccm of hydrogen flow, 4300sccm of ammonia flow and 21 mu mol/min of gallium source flow, and depositing the undoped GaN material with the thickness of 150nm on the upper part of the P-type block 12 by using the mask manufactured at the sixth time and adopting the metal organic chemical vapor deposition technology to form the i-GaN block 13.
Step k. deposit multiple layers of metal to form the gate 14, as shown in fig. 4 k.
Setting the vacuum degree to be less than 1.8 multiplied by 10 -3 Pa, power of 500W, evaporation rate of less than
The process conditions of (1) manufacturing a mask on the passivation layer 4, the source electrode 6, the interconnection metal 10 and the i-GaN block 13 for the seventh time, and sputtering metal combination Gd/Au with the thickness of 0.25 mu m/0.42 mu m on the upper part of the i-GaN block 13 by utilizing the mask and adopting an electron beam evaporation technology to form a grid electrode 14; and G, forming a High Electron Mobility Transistor (HEMT) structure by the source electrode 6, the grid electrode 14, the three groups of array strips on the right side and the interconnection metal 10, and forming a bidirectional voltage-resistant device by the HEMT and the diode formed in the step G to finish the manufacture of the whole device.
The effects of the present invention can be further illustrated by the following simulations.
Simulation 1: the output characteristic simulation of the device according to the second embodiment of the present invention is performed, and the result is shown in fig. 5.
Simulation 2: the blocking characteristic simulation of the device of the second embodiment of the present invention is performed, and the result is shown in fig. 6.
As can be seen from fig. 5, the turn-on voltage drop of the device of the present invention is low, about 0.32V.
As can be seen from FIG. 6, the forward blocking voltage of the present invention is 1798V and the reverse blocking voltage is-1657V.
The simulation result shows that the invention not only has lower starting voltage drop, but also has good conduction characteristic and bidirectional blocking characteristic.
The foregoing description is only three specific embodiments of the invention and is not intended to limit the invention, it will be obvious to those skilled in the art that, upon attaining an understanding of the disclosure and principles of the invention, may be practiced with modification and alteration of form and detail in accordance with the method of the invention without departing from the spirit and scope of the invention, such as: the substrate 1 is made of graphene material, and the passivation layer 4 is made of Si 3 N 4 、TiO 2 However, such modifications and variations are within the scope of the invention as defined by the appended claims.
Claims (10)
1. A power switch device based on array Schottky leakage comprises from bottom to top: substrate (1), transition layer (2), barrier layer (3) and passivation layer (4), its characterized in that:
a source electrode groove (5) is formed in the left side of the passivation layer (4) on the upper portion of the barrier layer (3), and a source electrode (6) is arranged in the source electrode groove (5);
the right sides of the barrier layer (3) and the passivation layer (4) are sequentially provided with a 1 st group of array strips and a 2 nd group of array strips … Mth group of array strips from left to right, each group of array strips comprises N parallel left array blocks (8) arranged at equal intervals and N +1 parallel right array blocks (9) arranged at equal intervals, the left array blocks (8) and the right array blocks (9) are distributed in a staggered manner, and the bottoms of the array blocks are positioned in the transition layer (2);
the upper surfaces of the left array block (8) and the right array block (9) are provided with interconnection metal (10) which is used for connecting the array blocks in parallel;
a groove (11) is formed in the passivation layer (4) between the source electrode (6) and the left side of the first array strip, and a P-type block (12), an i-GaN block (13) and a grid electrode (14) are sequentially arranged in the groove from bottom to top;
the source electrode (6), the grid electrode (14), the M groups of array strips on the right side and the interconnection metal (10) form an HEMT structure, a diode structure is formed between the M groups of array strips and the barrier layer (3) and the passivation layer (4) which are in contact with the M groups of array strips, and the HEMT and the diode form a bidirectional voltage-resistant device.
2. Device according to claim 1, characterized in that the substrate (1) is made of silicon carbide or silicon or sapphire or graphene material.
3. The device of claim 1, wherein:
the thickness e of the barrier layer (3) is 3 nm-100 nm, and the Al component is 0.1-0.4;
the passivation layer (4) adopts SiO 2 、Al 2 O 3 、HfO 2 、Si 3 N 4 、TiO 2 Of any one of the above or other insulating dielectric materials, and the thickness f is 20nm to 1000 nm.
4. The device of claim 1, wherein:
each group of array strips is provided with N left array blocks (8) and N +1 right array blocks (9), namely each group of array strips is provided with (2N +1) array blocks, M groups of array strips have M x (2N +1) array blocks, wherein M is more than or equal to 1, and N is more than or equal to 2.
5. The device of claim 1, wherein: the size parameters of the left array block (8) and the right array block (9) are as follows:
the left array block (8) and the right array block (9) are both rectangular blocks, the length a is greater than 0, and the width b is greater than 0;
the longitudinal distance between two adjacent left array blocks (8) and the longitudinal distance between two adjacent right array blocks (9) are both c, c is greater than 0, and c is less than b;
in each group of array strips, the transverse distance d between the left array block (8) and the right array block (9) is equal, and d is greater than 0;
the left array block (8) and the right array block (9) are the same in height and are g, g is larger than e + f, and e and f are thicknesses of the barrier layer (3) and the passivation layer (4) respectively.
6. The device of claim 1, wherein:
the P-type block (12) is made of P-GaN or CuO or NiO material, the thickness of the P-type block is 10 nm-500 nm, and the doping concentration is 5 multiplied by 10 15 cm -3 ～1×10 22 cm -3 ；
The thickness of the i-GaN block (13) is 10nm to 500 nm.
7. The device of claim 1, wherein:
ohmic contact is formed between the source electrode (6) and the contacted barrier layer (3);
the left array block (8) and the right array block (9) are in Schottky contact with the transition layer (2) and the barrier layer (3) which are in contact with each other.
8. A manufacturing method of a power switch device based on array Schottky leakage comprises the following steps:
A) extending GaN semiconductor materials on a substrate (1) to form a transition layer (2);
B) a GaN-based wide bandgap semiconductor material is extended on the transition layer (2) to form a barrier layer (3);
C) extending a dielectric material on the barrier layer (3) to form a passivation layer (4);
D) manufacturing a mask on the passivation layer (4) for the first time, etching the left side of the passivation layer (4) by using the mask until the upper surface of the barrier layer (3) is etched to form a source electrode groove (5);
E) manufacturing a mask on the passivation layer (4) and the source electrode groove (5) for the second time, depositing metal in the source electrode groove (5) by using the mask, and performing rapid thermal annealing to form a source electrode (6);
F) a mask is made on the passivation layer (4) and the source electrode (6) for the third time, etching is carried out on the right side of the passivation layer (4) through the mask until the etching is carried out below the lower surface of the barrier layer (3), and M x (2N +1) array grooves (7) are formed;
G) manufacturing a mask on the passivation layer (4), the source electrode (6) and the array groove (7) for the fourth time, and depositing metal on the upper part of the passivation layer (4) inside and on the right side of the array groove (7) by using the mask to form a left array block (8), a right array block (9) and interconnection metal (10);
H) making a mask on the passivation layer (4), the source electrode (6) and the interconnection metal (10) for the fifth time, etching the passivation layer (4) between the source electrode (6) and the left side of the first group of array strips by using the mask until the upper surface of the barrier layer (3) is etched to form a groove (11);
I) a mask is manufactured on the passivation layer (4), the source electrode (6), the interconnection metal (10) and the groove (11) for the sixth time, the thickness of the mask is 10nm to 500nm, the doping concentration is 5 multiplied by 10, and the thickness of the mask is 5 nm to 500nm 15 cm -3 ～1×10 22 cm -3 A P-type block (12);
J) depositing an i-GaN block (13) with the thickness of 10 nm-500 nm on the upper part of the P-type block (12) by using the mask manufactured at the sixth time;
K) and (3) manufacturing a mask on the passivation layer (4), the source electrode (6), the interconnection metal (10) and the i-GaN block (13) for the seventh time, and depositing metal on the upper part of the i-GaN block (13) by using the mask to form a grid electrode (14) so as to finish the manufacture of the whole device.
9. The method of claim 8, wherein:
the epitaxy or deposition technique used in said steps A), B), C), I), J) comprises: metal organic chemical vapor deposition, plasma enhanced chemical vapor deposition, molecular beam epitaxy, magnetron sputtering;
the metal deposition process used in the steps E), G) and K) comprises the following steps: electron beam evaporation process and sputtering process.
10. The method of claim 8, wherein:
the process conditions of the rapid thermal annealing used in the step E) are as follows: setting the temperature to 800-900 ℃ and the time to 30-40 s;
the process conditions for etching the passivation layer (4) are as follows: CF (compact flash) 4 Flow rate of 20sccm, O 2 The flow rate was 2sccm, the pressure was 20mT, and the bias voltage was 100V.
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