CN114937698A - Composite drain power transistor - Google Patents
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- CN114937698A CN114937698A CN202210587495.7A CN202210587495A CN114937698A CN 114937698 A CN114937698 A CN 114937698A CN 202210587495 A CN202210587495 A CN 202210587495A CN 114937698 A CN114937698 A CN 114937698A
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- 239000002131 composite material Substances 0.000 title claims abstract description 15
- 238000002161 passivation Methods 0.000 claims abstract description 111
- 230000004888 barrier function Effects 0.000 claims abstract description 84
- 229910052751 metal Inorganic materials 0.000 claims abstract description 71
- 239000002184 metal Substances 0.000 claims abstract description 71
- 238000004519 manufacturing process Methods 0.000 claims abstract description 35
- 230000007704 transition Effects 0.000 claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 238000000034 method Methods 0.000 claims description 48
- 238000000151 deposition Methods 0.000 claims description 39
- 238000005516 engineering process Methods 0.000 claims description 38
- 238000005530 etching Methods 0.000 claims description 29
- 239000000463 material Substances 0.000 claims description 28
- 238000005229 chemical vapour deposition Methods 0.000 claims description 10
- 239000004065 semiconductor Substances 0.000 claims description 9
- 238000004151 rapid thermal annealing Methods 0.000 claims description 6
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 5
- 238000001451 molecular beam epitaxy Methods 0.000 claims description 5
- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims description 4
- 229910010413 TiO 2 Inorganic materials 0.000 claims description 3
- 238000000231 atomic layer deposition Methods 0.000 claims description 3
- 238000005546 reactive sputtering Methods 0.000 claims description 3
- 238000000407 epitaxy Methods 0.000 claims description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 2
- 230000000903 blocking effect Effects 0.000 abstract description 21
- 230000002457 bidirectional effect Effects 0.000 abstract description 10
- 229910002601 GaN Inorganic materials 0.000 description 51
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 16
- 238000004544 sputter deposition Methods 0.000 description 15
- 238000001020 plasma etching Methods 0.000 description 12
- 238000005566 electron beam evaporation Methods 0.000 description 11
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 8
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 8
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 8
- 229910021529 ammonia Inorganic materials 0.000 description 8
- 238000006243 chemical reaction Methods 0.000 description 8
- 230000008020 evaporation Effects 0.000 description 8
- 238000001704 evaporation Methods 0.000 description 8
- 229910052733 gallium Inorganic materials 0.000 description 8
- 239000001257 hydrogen Substances 0.000 description 8
- 229910052739 hydrogen Inorganic materials 0.000 description 8
- 238000001755 magnetron sputter deposition Methods 0.000 description 6
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 5
- 229910052786 argon Inorganic materials 0.000 description 5
- 239000007789 gas Substances 0.000 description 5
- 239000013077 target material Substances 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 230000010354 integration Effects 0.000 description 4
- 229910052594 sapphire Inorganic materials 0.000 description 4
- 239000010980 sapphire Substances 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 4
- 229910010271 silicon carbide Inorganic materials 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 239000000376 reactant Substances 0.000 description 3
- JLTRXTDYQLMHGR-UHFFFAOYSA-N trimethylaluminium Chemical compound C[Al](C)C JLTRXTDYQLMHGR-UHFFFAOYSA-N 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 238000013329 compounding Methods 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 239000008367 deionised water Substances 0.000 description 2
- 229910021641 deionized water Inorganic materials 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 229910001882 dioxygen Inorganic materials 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 238000005036 potential barrier Methods 0.000 description 2
- 238000010926 purge Methods 0.000 description 2
- 239000012495 reaction gas Substances 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- YTAHJIFKAKIKAV-XNMGPUDCSA-N [(1R)-3-morpholin-4-yl-1-phenylpropyl] N-[(3S)-2-oxo-5-phenyl-1,3-dihydro-1,4-benzodiazepin-3-yl]carbamate Chemical compound O=C1[C@H](N=C(C2=C(N1)C=CC=C2)C1=CC=CC=C1)NC(O[C@H](CCN1CCOCC1)C1=CC=CC=C1)=O YTAHJIFKAKIKAV-XNMGPUDCSA-N 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 230000005533 two-dimensional electron gas Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
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- Manufacturing & Machinery (AREA)
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Abstract
The invention discloses a composite drain power transistor and a manufacturing method thereof, mainly solving the problems of high starting voltage drop and limited bidirectional blocking capability of the traditional device, comprising the following steps: the HEMT structure comprises a substrate, a transition layer, a barrier layer and a passivation layer, wherein the left side and the right side of the passivation layer are respectively a source electrode and an ohmic electrode, the left side of the ohmic electrode is sequentially provided with M anode blocks, N Schottky electrodes and K P-type array blocks from right to left, the upper sides of the ohmic electrodes, the P-type array blocks, the Schottky electrodes and the anode blocks are made of interconnection metal, a window is formed in the passivation layer between the source electrode and the P-type array blocks, the P-type block, an i-GaN block and a grid electrode are sequentially arranged in the passivation layer, the source electrode, the grid electrode, the ohmic electrode, the Schottky electrodes and the anode blocks form an HEMT structure, and the Schottky electrodes and the anode blocks form a diode structure with the barrier layer and the passivation layer which are in contact with the Schottky electrodes and the anode blocks. The invention reduces the starting voltage drop and the reverse leakage current, improves the bidirectional blocking capability and can be used for power electronic systems.
Description
Technical Field
The invention belongs to the technical field of microelectronics, and particularly relates to a power transistor which can be used as a basic device of a power electronic system.
Technical Field
In application scenarios such as wireless charging, aerospace, and radio frequency, a device is often required to have a bidirectional blocking characteristic, so as to maintain high power conversion efficiency and improve device reliability. Due to the superior material properties of GaN, such as high breakdown field strength, good thermal properties, and high electron mobility, GaN-based enhancement mode hemts have received great attention from researchers in high power and high frequency applications. However, the conventional GaN-based enhancement mode hemt can only realize unidirectional blocking, that is, only the drain voltage is higher than the source voltage, and the gate is turned off to realize forward blocking, which severely limits the application of the device.
The main body part of the traditional gallium nitride-based power switch device is of a gallium nitride-based heterojunction structure, and the traditional gallium nitride-based power switch device comprises: the device comprises a substrate, a transition layer, a channel layer, a barrier layer, a P-GaN block, a drain electrode, a source electrode and a grid electrode; the left side of the upper portion of the barrier layer is deposited with a drain electrode, the right side of the upper portion of the barrier layer is deposited with a source electrode, the middle portion of the upper portion of the barrier layer is deposited with a P-GaN block, the upper portion of the P-GaN block is deposited with a grid electrode, a bidirectional blocking device is formed by using a traditional structure, only a Schottky diode can be connected in series with the outside, a large parasitic effect is brought, power consumption is increased, the occupied area is large, and monolithic integration is difficult to achieve. In order to improve the problems of the conventional structure, a recess SBD drain structure was first proposed by the fisher-bloan institute of fedunan-blonam, germany, 2009. The groove SBD drain structure is embedded into a traditional enhancement type high electron mobility transistor, namely the existing gallium nitride-based power switch device shown in figure 1, a substrate, a transition layer, a barrier layer, a grid and a source electrode are arranged from bottom to top, ohmic contact is arranged on the left side of the upper portion of the barrier layer, the barrier layer and the right side of the transition layer are provided with Schottky contact, the drain electrode is arranged on the upper portion of the barrier layer, and passivation layers are arranged on the upper portion of the whole device except the source electrode, the grid electrode and the drain electrode to cover the upper portion of the whole device. The device preparation process is compatible with the traditional GaN-based HEMT device process, and can realize bidirectional blocking. However, the device structure has the problems of high forward opening voltage drop, low forward output current, large reverse leakage current and limited bidirectional blocking capability.
Disclosure of Invention
The invention aims to provide a composite drain power transistor, which aims to solve the problems of high forward starting voltage drop, low forward output current, large reverse leakage current and limited bidirectional blocking capability in the prior art, reduce power consumption and improve the monolithic integration level.
In order to achieve the purpose, the technical scheme of the invention is realized as follows:
first, device structure
A composite drain power transistor comprising, from bottom to top: substrate 1, transition layer 2, barrier layer 3, passivation layer 4, its characterized in that:
a source electrode groove 5 is arranged on the left side of a passivation layer 4 on the upper portion of the barrier layer 3, and a source electrode 7 is arranged in the source electrode groove;
the rightmost side of the passivation layer 4 is provided with an ohmic groove 6, an ohmic electrode 8 is arranged in the groove, and the bottom of the groove is in contact with the upper surface of the barrier layer 3;
the left side of the ohmic electrode 8 is sequentially provided with M anode blocks 14, N Schottky electrodes 13 and K P-type array blocks 10 from right to left, the lower parts of the anode blocks 14 and the Schottky electrodes 13 are positioned in the transition layer 2, and the lower surfaces of the P-type array blocks 10 are in contact with the upper surface of the barrier layer 3;
the upper surfaces of the ohmic electrode 8, the P-type array block 10, the schottky electrode 13 and the anode block 14 are provided with interconnection metal 15 for connecting the ohmic electrode 8, the P-type array block 10, the schottky electrode 13 and the anode block 14 to keep the equipotential of the parts;
a window 16 is formed in the passivation layer 4 between the source electrode 7 and the P-type array block 10, and a P-type block 17, an i-GaN block 18 and a grid 19 are sequentially arranged in the passivation layer from bottom to top;
the source electrode 7, the grid electrode 19, the ohmic electrode 8 on the right side, the Schottky electrode 13 and the anode block 14 form a HEMT structure, a diode structure is formed between the Schottky electrode 13 and the anode block 14 and the barrier layer 3 and the passivation layer 4 which are in contact with the Schottky electrode and the anode block, and the HEMT and the diode are compounded to form a power switching device.
Further, the barrier layer 3 has a thickness a of 3to 100 nm.
Further, the passivation layer 4 is made of SiO 2 、SiN、Al 2 O 3 、Sc 2 O 3 、HfO 2 、TiO 2 Wherein the thickness b is 20nm to 1000 nm.
Further, the source electrode 7 and the ohmic electrode 8 are both in ohmic contact with the barrier layer 3, and the schottky electrode 13 and the anode block 14 are both in schottky contact with the contacted barrier layer 3.
Further, the K P-type array blocks 10 are distributed front and back at equal intervals, and the distance g between two adjacent array blocks is greater than 0; the lateral spacing d between each P-type array block 10 and the schottky electrode 13 is greater than 0.
Furthermore, the N Schottky electrodes 13 are distributed in a front-back mode at equal intervals, the interval h between every two adjacent Schottky electrodes is larger than 0, the Schottky electrodes 13 and the K P-type array blocks 10 are distributed in a staggered mode, N is larger than or equal to 1, and K is larger than or equal to 2; the lateral spacing e between the schottky electrode 13 and the anode block 14 is greater than 0.
Furthermore, the M anode blocks 14 are distributed at equal intervals in the front and back directions, the longitudinal interval i between two adjacent anode blocks is greater than 0, when the device is in a balanced state, a depletion region is generated between the anode blocks 14, a current path is pinched off by the depletion region, and M is greater than or equal to 2; the lateral spacing f between each anode block 14 and the ohmic electrode 8 is greater than 0; each anode block 14 has the same height c as the respective schottky electrode 13, c > a + b, where a is the thickness of the barrier layer 3 and b is the thickness of the passivation layer 4.
Second, the manufacturing method
A method for manufacturing the composite drain power transistor is characterized by comprising the following steps:
A) extending GaN semiconductor material on a substrate 1 to form a transition layer 2;
B) extending GaN-based wide bandgap semiconductor material on the transition layer 2to form a barrier layer 3;
C) depositing a medium on the barrier layer 3to form a passivation layer 4;
D) manufacturing a mask on the passivation layer 4 for the first time, simultaneously etching the left side and the right side of the passivation layer 4 by using the mask until the upper surface of the barrier layer 3 is etched to form a source electrode groove 5 and an ohmic groove 6;
E) manufacturing a mask on the passivation layer 4, the source electrode groove 5 and the ohmic groove 6 for the second time, depositing metal above the source electrode groove 5 and the ohmic groove 6 by using the mask, and performing rapid thermal annealing to form a source electrode 7 and an ohmic electrode 8;
F) making masks on the passivation layer 4, the source electrode 7 and the ohmic electrode 8 for the third time, etching the middle part of the passivation layer 4 at the position which is slightly to the right by using the masks until the upper surface of the barrier layer 3, and forming K P-shaped array block grooves 9 which are arranged at the front and the back at equal intervals;
G) making masks on the passivation layer 4, the source electrode 7, the ohmic electrode 8 and the P-type array block groove 9 for the fourth time, and depositing a P-type material in the P-type array block groove 9 by using the masks to form K P-type array blocks 10;
H) making a mask on the passivation layer 4, the source electrode 7, the ohmic electrode 8 and the P-type array block 10 for the fifth time, etching the right side of the P-type array block 10 by using the mask to the inside of the transition layer 2, and forming N Schottky grooves 11 and M anode slots 12;
I) making masks on the passivation layer 4, the source electrode 7, the ohmic electrode 8, the P-type array block 10, the schottky groove 11 and the anode groove 12 for the sixth time, and depositing metal above the ohmic electrode 8, the schottky groove 11, the anode groove 12 and the P-type array block 10 by using the masks to form N schottky electrodes 13, M anode blocks 14 and interconnection metal 15;
J) a mask is manufactured on the passivation layer 4, the source electrode 7 and the interconnection metal 15 for the seventh time, the passivation layer 4 between the source electrode 7 and the P-type array block 10 is etched by using the mask until the upper surface of the barrier layer 3 is etched, and a window 16 is formed;
K) making a mask on the passivation layer 4, the source electrode 7, the interconnection metal 15 and the window 16 for the eighth time, and depositing the mask in the window 16 to a thickness of 10 nm-500 nm and a doping concentration of 5 × 10 15 cm -3 ～1×10 22 cm -3 A P-type block 17;
l) utilizing the mask manufactured at the eighth time to epitaxially form an i-GaN block 18 with the thickness of 10 nm-500 nm on the upper part of the P-type block 17;
m) making a mask on the passivation layer 4, the source electrode 7, the interconnection metal 15 and the i-GaN block 18 for a ninth time, and depositing metal on the upper part of the i-GaN block 18 by using the mask to form a gate electrode 19, thereby completing the manufacture of the whole device.
Compared with the existing gallium nitride-based power switch device, the device of the invention has the following advantages:
firstly, the device has strong bidirectional blocking capability and good reliability.
The invention can realize excellent blocking characteristics of forward direction and reverse direction due to the introduction of the P-type array block 10, the Schottky electrode 13 and the anode block 14 at the right end of the device. The method specifically comprises the following steps:
when the source 7 applies a low level and the schottky electrode 13 and the anode block 14 apply a high level, the diode on the right side is in a forward bias state, and the gate applies a zero potential at the moment, so that the two-dimensional electron gas communication between the transition layer and the barrier layer is prevented, i.e. a channel for conducting the HEMT is not formed, so that the device cannot be conducted, and forward blocking is realized, and after a depletion region formed by the semiconductor layer on the lower part of the gate is adhered to the P-type array block 10, the depletion region formed by the semiconductor layer on the lower part of the P-type array block 10 can continue to expand towards the direction of the schottky electrode 13 and the anode block 14, so that a higher voltage can be applied to the schottky electrode 13 and the anode block 14, and the forward blocking capability of the device is remarkably enhanced;
when the source electrode 7 is applied with a high level and the schottky electrode 13 and the anode block 14 are applied with a low level, no matter whether the grid is zero potential or not, the diode on the right side cannot be conducted in the forward direction, and the whole device is in a turn-off state, so that reverse blocking is realized, and because the depletion region of the semiconductor layer on the lower portion of the P-type array block 10 is adhered to the depletion regions of the semiconductor layers around the schottky electrode 13 and the anode block 14, a higher voltage can be applied to the source electrode 7, and the reverse blocking capability of the device is remarkably enhanced.
And secondly, reducing the starting voltage and increasing the output current.
According to the Schottky barrier diode, due to the fact that the Schottky electrode 13 and the anode block 14 are adopted, when the Schottky barrier diode is in a conducting state, current carriers can flow in from the edges of the Schottky electrode 13 and the anode block 14, the contact area of the anode of the Schottky barrier diode and current is increased, accordingly, starting voltage is remarkably reduced, and conducting current is increased; in addition, since the ohmic electrode 8 is disposed on the right side of the passivation layer and connected to the schottky electrode 13 and the anode block 14 through the interconnection metal 15, the voltage drop of the anode terminal in the on state of the schottky diode device is reduced by virtue of the ultra-low voltage turn-on of the ohmic contact, so that the turn-on voltage of the device is greatly reduced.
Third, reverse leakage current is reduced.
Due to the fact that the P-type array block 10 is adopted, when the device is in a reverse turn-off state, a depletion region generated by the P-type array block 10 can pinch off a channel, and reverse leakage current of the device is reduced.
And fourthly, the threshold voltage is improved, and the reliability of the device is enhanced.
In the invention, the i-GaN block 18 is added on the P-type block 17, so that the threshold voltage of the device is regulated and controlled, and higher concentration of the P-type block 17 and lower work function contact metal are not needed any more than the original high threshold voltage; due to the fact that the i-GaN block 18 is added, the grid electrode 19 can be directly contacted with the i-GaN block 18, the height and the width of a contact potential barrier are increased, grid voltage shared by a potential barrier region can be increased, the requirement on the work function of grid electrode metal is lowered, namely the grid electrode only needs common metal, and therefore threshold voltage of the device is improved, and reliability of the device is improved.
Fifthly, monolithic integration is realized, and the system volume is reduced.
In the device of the invention, three parts of the Schottky electrode 13, the anode block 14 and the ohmic electrode are equipotential through the interconnection metal 15, and the three parts are used as a drain part of the HEMT structure and an anode part of the diode structure, so that the connection is realized through multiplexing. Compared with the traditional method of interconnecting through external metal, the invention can save the chip area and improve the integration level.
Drawings
FIG. 1 is a block diagram of a prior art device;
FIG. 2 is a top view of the composite drain power transistor of the present invention;
FIG. 3 is a cross-sectional view taken along line AB of FIG. 2;
FIG. 4 is a cross-sectional view taken along the CD of FIG. 2;
FIG. 5 is a block diagram of the overall process for fabricating the composite drain power transistor of the present invention;
fig. 6 is a diagram showing the results of simulation of the output characteristics and the blocking characteristics of the present invention.
Detailed Description
Embodiments and effects of the present invention will be described in further detail below with reference to the accompanying drawings.
Referring to fig. 2, 3, and 4, the composite drain power transistor according to the present embodiment includes: the device comprises a substrate 1, a transition layer 2, a barrier layer 3, a passivation layer 4, a source groove 5, an ohmic groove 6, a source electrode 7, an ohmic electrode 8, a P-type array block groove 9, a P-type array block 10, a Schottky groove 11, an anode groove 12, a Schottky electrode 13, an anode block 14, interconnection metal 15, a window 16, a P-type block 17, an i-GaN block 18 and a grid 19. Wherein:
the substrate 1 is made of silicon carbide or silicon or sapphire;
the transition layer 2 is arranged on the upper part of the substrate 1 and has the doping concentration of 1 multiplied by 10 15 ～1×10 18 cm -3 The thickness is 5to 100 μm;
the barrier layer 3 is positioned on the upper part of the transition layer 2 and is composed of a plurality of layers of same or different GaN-based wide bandgap semiconductor materials, the thickness a is 3 nm-100 nm, and the Al component is 0.1-0.4;
the passivation layer 4 is arranged on the barrier layer 3 and is made of SiO 2 、SiN、Al 2 O 3 、Sc 2 O 3 、HfO 2 、TiO 2 Or other insulating dielectric materialThe thickness b is 20 nm-1000 nm;
the source electrode groove 5 is positioned on the left side of the passivation layer 4, and the lower surface of the source electrode groove is in contact with the barrier layer 3;
the ohmic groove 6 is positioned on the right side of the passivation layer 4, and the lower surface of the ohmic groove is in contact with the barrier layer 3;
the source electrode 7 is positioned inside the source electrode groove 5, and the source electrode 7 and the barrier layer 3 form ohmic contact;
the ohmic electrode 8 is positioned in the ohmic groove 6, and the ohmic electrode 8 and the barrier layer 3 form ohmic contact;
the P-type array block groove 9 is positioned at the right side of the middle part of the passivation layer 4, and the lower surface of the P-type array block groove is in contact with the barrier layer 3;
the number of the P-type array blocks 10 is K, the P-type array blocks are distributed in the front and the back at equal intervals and are positioned in the grooves 9 of the P-type array blocks, the lower surfaces of the P-type array blocks 10 are in contact with the upper surface of the barrier layer 3, the distance g between every two adjacent array blocks is greater than 0, and K is greater than or equal to 2;
the Schottky groove 11 is positioned in the passivation layer 4, the barrier layer 3 and the transition layer 2 on the right side of the P-type array block groove 9, and the depth of the Schottky groove is c;
the anode groove 12 is positioned in the passivation layer 4, the barrier layer 3 and the transition layer 2 on the right side of the Schottky groove 11, and the depth of the anode groove is c;
the number of the Schottky electrodes 13 is N, the Schottky electrodes are distributed in the front and the back at equal intervals and are positioned in the Schottky groove 11, the N Schottky electrodes 13 and the K P-type array blocks 10 are distributed in a staggered manner, and the transverse distance d between each P-type array block 10 and each Schottky electrode 13 is larger than 0; the distance h between every two adjacent electrodes is larger than 0, the height c of each Schottky electrode 13 is the same, c is larger than a + b, wherein a is the thickness of the barrier layer 3, b is the thickness of the passivation layer 4, Schottky contact is formed between the Schottky electrode 13 and the contacted barrier layer 3, and N is larger than or equal to 1;
the anode blocks 14 are distributed in the front and the back at equal intervals and are positioned in the anode slot 12, the height of each anode block 14 is c, the longitudinal interval i between every two adjacent anode blocks is larger than 0, when the device is in a balanced state, a depletion region is generated between the anode blocks 14, a current path is clamped off by the depletion region, the transverse interval e between each anode block 14 and the Schottky electrode 13 is larger than 0, the transverse interval f between each anode block 14 and the ohmic electrode 8 is larger than 0, Schottky contact is formed between each anode block 14 and the contacted barrier layer 3, wherein M is larger than or equal to 2;
the interconnection metal 15 is positioned on the upper surfaces of the ohmic electrode 8, the P-type array block 10, the schottky electrode 13 and the anode block 14;
the window 16 is positioned inside the passivation layer 4 between the source electrode 7 and the P-type array block 10, and the lower surface of the window is in contact with the barrier layer 3;
the P-type block 17 is positioned in the window 16, is made of P-GaN or CuO or NiO material, has the thickness of 10 nm-500 nm and the doping concentration of 5 multiplied by 10 15 cm -3 ～1×10 22 cm -3 ；
The i-GaN block 18 is positioned inside the window 16 and above the P-type block 17, and has a thickness of 10 nm-500 nm;
the grid electrode 19 is positioned at the upper part of the i-GaN block 18, the length of the grid electrode is less than that of the i-GaN block 18, and Schottky contact is formed between the grid electrode and the i-GaN block 18;
the source electrode 7, the grid electrode 19, the right ohmic electrode 8, the Schottky electrode 13 and the anode block 14 form a HEMT structure, a diode structure is formed between the Schottky electrode 13 and the anode block 14 and the barrier layer 3 and the passivation layer 4 which are in contact with the Schottky electrode and the anode block, and the HEMT and the diode are compounded to form a power switching device.
Referring to fig. 5, the method of fabricating a composite drain power transistor according to the present invention provides the following three examples.
The first embodiment is as follows: the barrier layer 3 is made on the silicon substrate with the thickness a of 60nm, and the passivation layer 4 is made of Al 2 O 3 The thickness b is 320nm, K is 6, N is 5, M is 6, the heights c of the schottky electrode 13 and the anode block 14 are 480nm, and both the P-type array block 10 and the P-type block 17 are composite drain power transistors made of CuO materials.
And A, epitaxially forming a transition layer 2 on the upper part of the silicon substrate 1.
The temperature was set at 960 ℃ and the pressure at 45Torr, and SiH was used 4 The hydrogen flow is 4200sccm, the ammonia flow is 4200sccm and the gallium source flow is 110 mu mol/min as a doping source, and the epitaxial thickness is formed on the silicon substrate 1 by the metal organic chemical vapor deposition technologyDegree of 5.2 μm and doping concentration of 8 × 10 19 cm -3 N of (A) to (B) - And a type GaN transition layer 2.
Step B, extending Al on the transition layer 2 0.25 Ga 0.75 N, the barrier layer 3 is produced.
Setting the vacuum degree to be less than or equal to 1.0 multiplied by 10 -10 mbar, radio frequency power of 420W, and N as reactant 2 High-purity Ga source and high-purity Al source, and epitaxial growth of Al with a thickness of 60nm on the GaN transition layer 2 by using molecular beam epitaxy technology 0.25 Ga 0.75 N material forming the barrier layer 3.
Step C, depositing Al on the barrier layer 3 2 O 3 Material forming the passivation layer 4.
Setting the reaction temperature to be 300 ℃, the reaction sources to be Trimethylaluminum (TMA) and deionized water, the pressure of a reaction chamber to be 5torr, and setting the process conditions of 1.5s of trimethylaluminum gas introduction, 3s of nitrogen purging, 1s of deionized water steam introduction and 3s of nitrogen purging in a single reaction period, and depositing 320nm of Al above the barrier layer 3 by using an atomic layer deposition technology 2 O 3 Material forming the passivation layer 4.
And D, manufacturing a source electrode groove 5 and an ohmic groove 6.
Setting CF 4 Flow rate of 20sccm, O 2 The method comprises the steps of manufacturing a mask on the upper portion of a passivation layer 4 for the first time under the process conditions that the flow is 2sccm, the pressure is 20mT and the bias voltage is 100V, simultaneously etching the left side and the right side of the passivation layer 4 by utilizing the mask through a reactive ion etching technology until the upper surface of a barrier layer 3 is etched, and forming a source electrode groove 5 and an ohmic groove 6.
And E, depositing metal in the source electrode groove 5 and the ohmic groove 6to respectively form a source electrode 7 and an ohmic electrode 8.
Setting the vacuum degree to be less than 1.8 multiplied by 10 -3 Pa, power 400W, evaporation rate
The process conditions of (1) second manufacturing a mask on the passivation layer 4, the source trench 5 and the ohmic recess 6, using the mask to form the source trench 5 and the ohmic recess using electron beam evaporation techniquesDepositing a metal combination Ti/Al/Mo/Au above the groove 6, wherein the thicknesses of the metal combination Ti/Al/Mo/Au are 0.112 μm, 0.123 μm, 0.075 μm and 0.084 μm in sequence; then, rapid thermal annealing was performed at a temperature of 850 ℃ for 35 seconds to form the source electrode 7 and the ohmic electrode 8.
And F, manufacturing a P-type array block groove 9.
Setting CF 4 The flow rate was 28sccm, O 2 And under the process conditions of the flow rate of 3sccm, the pressure of 25mT and the bias voltage of 110V, making a mask on the passivation layer 4, the source electrode 7 and the ohmic electrode 8 for the third time, etching the middle part of the passivation layer 4 to the right by using the mask until the upper surface of the barrier layer 3 is etched, and forming six P-type array block grooves 9 which are arranged at the front and the back at equal intervals.
And G, manufacturing the P-type array block 10.
Setting copper with the purity of 99.999 percent as a target material, sputtering gas as high-purity argon, high-purity oxygen with the same purity as the target material as reaction gas, and ensuring the vacuum degree of a reaction chamber before sputtering to be 2.0 multiplied by 10 -4 Pa, keeping the flow rate of argon gas at 20sccm, the flow rate of oxygen gas at 10sccm, the pressure of the deposition chamber at 0.5Pa, the radio-frequency power at 35W and the substrate temperature at 200 ℃, making masks on the passivation layer 4, the source electrode 7, the ohmic electrode 8 and the six P-type array block grooves 9 for the fourth time, and sputtering the six P-type array block grooves 9 to a thickness of 320nm and a doping concentration of 7 x 10 by using the masks and using a magnetron sputtering technology 20 cm -3 Forming six P-type array blocks 10.
And H, etching to form the Schottky groove 11 and the anode groove 12.
Setting CF 4 Flow rate of 25sccm, O 2 And manufacturing a mask on the passivation layer 4, the source electrode 7, the ohmic electrode 8 and the P-type array block 10 for the fifth time under the process conditions of the flow rate of 4sccm, the pressure of 25mT and the bias voltage of 110V, and etching the right side of the P-type array block 10 by using the mask to the etching depth of 480nm to form five Schottky grooves 11 and six anode grooves 12.
Step i. deposit metal to form schottky electrode 13, anode block 14 and interconnect metal 15.
The vacuum degree was set to 1.6X 10 -3 Pa，Power 350W and evaporation rate
The process conditions of the method are that a mask is manufactured on a passivation layer 4, a source electrode 7, an ohmic electrode 8, a P-type array block 10, a Schottky groove 11 and an anode groove 12 for the sixth time, the mask is utilized to deposit metal Mo above the ohmic electrode 8, the Schottky groove 11, the anode groove 12 and the P-type array block 10 by adopting an electron beam evaporation technology, Schottky contact is manufactured, and five Schottky electrodes 13, six anode blocks 14 and interconnection metal 15 are formed; a diode structure is formed between the barrier layer 3 and the passivation layer 4 with which the schottky electrode 13 and the anode block 14 are in contact.
Step j. the passivation layer 4 is etched to form a window 16.
Setting CF 4 The flow rate was 28sccm, O 2 And manufacturing a mask on the passivation layer 4, the source electrode 7 and the interconnection metal 15 for the seventh time under the process conditions of the flow rate of 3sccm, the pressure of 25mT and the bias voltage of 100V, etching the passivation layer 4 between the source electrode 7 and the P-type array block 10 by using the mask and a reactive ion etching technology until the upper surface of the barrier layer 3 is etched, and forming a window 16.
Step k. sputtering P-type material in the window 16 to form a P-type block 17.
Setting copper with the purity of 99.999 percent as a target material, a sputtering gas as high-purity argon, high-purity oxygen with the same purity as the target material as a reaction gas, and setting the vacuum degree of a reaction chamber before sputtering as 2.0 multiplied by 10 -4 Pa, keeping the flow rate of argon gas at 20sccm, the flow rate of oxygen gas at 10sccm, the pressure of the deposition chamber at 0.5Pa, the radio frequency power at 35W and the substrate temperature at 200 deg.C, forming a mask on the passivation layer 4, the source electrode 7, the interconnection metal 15 and the window 16 for the eighth time, and depositing the mask in the window 16 by magnetron sputtering to a thickness of 300nm and a doping concentration of 7 × 10 20 cm -3 Forming P-type blocks 17.
And L, setting the process conditions of 500 ℃ of temperature, 46Torr of pressure, 4300sccm of hydrogen flow, 4300sccm of ammonia flow and 21 mu mol/min of gallium source flow, and depositing the undoped GaN material with the thickness of 240nm on the upper part of the P-type block 17 by using the eighth manufactured mask and adopting a metal organic chemical vapor deposition technology to form the i-GaN block 18.
Step m. metal is deposited on top of the i-GaN block 18 to form the gate 19.
Setting the vacuum degree to be less than 1.8 multiplied by 10 -3 Pa, power of 500W, evaporation rate of less than
Making a mask on the passivation layer 4, the source electrode 7, the interconnection metal 15 and the i-GaN block 18 for the ninth time, and depositing metal combinations Ni/Au with the thicknesses of 0.020 mu m/0.32 mu m on the upper part of the i-GaN block 18 by using an electron beam evaporation technology by using the mask to form a grid electrode 19; and (4) forming a HEMT structure by the source electrode 7, the grid electrode 19, the ohmic electrode 8 on the right side, the Schottky electrode 13 and the anode block 14, compounding the HEMT device with the diode formed in the step I to form a power switch device, and finishing the manufacture of the whole device.
Example two: the barrier layer 3 with the thickness a of 100nm is manufactured on the sapphire substrate, and the passivation layer 4 is made of HfO 2 The thickness b is 1000nm, K is 3, N is 4, M is 4, the height c of the schottky electrode 13 and the anode block 14 is 1520nm, and the P-type array block 10 and the P-type block 17 are both selected from composite drain power transistors made of NiO material.
Using metal organic chemical vapor deposition technology, the epitaxial thickness of the sapphire substrate 1 is 6.3 μm, and the doping concentration is 1 × 10 16 cm -3 N of (A) to (B) - A GaN-type transition layer 2;
the deposition process conditions are as follows: at 950 ℃ under 40Torr, in SiH 4 The hydrogen flow is 4000sccm, the ammonia flow is 4000sccm, and the gallium source flow is 100 mu mol/min.
Using molecular beam epitaxy technique, Al with a thickness a of 100nm is epitaxially grown on the GaN transition layer 2 0.1 Ga 0.9 N material forming the barrier layer 3;
the process conditions of the molecular beam epitaxy technology are as follows: degree of vacuumLess than or equal to 1.0 x 10 -10 mbar, radio frequency power of 400W, and N as reactant 2 High-purity Ga source and high-purity Al source.
Step 3, depositing HfO 2 And (5) preparing a passivation layer 4.
Depositing HfO with the thickness of 1000nm on the barrier layer 3 by using a radio frequency magnetron reactive sputtering technology 2 A material forming a passivation layer 4;
the technological conditions of the radio frequency magnetron reactive sputtering technology are as follows: the sputtering pressure in the reaction chamber is kept at about 0.1Pa, and O 2 And Ar flow rates are respectively 1sccm and 8sccm, the substrate temperature is fixed at 200 ℃, and the Hf target radio frequency power is 150W.
And 4, manufacturing and forming a source electrode groove 5 and an ohmic groove 6.
A mask is manufactured on the upper portion of the passivation layer 4 for the first time, the left side and the right side of the passivation layer 4 are etched simultaneously by utilizing the mask and using a reactive ion etching technology until the upper surface of the barrier layer 3 is etched, and a source electrode groove 5 and an ohmic groove 6 are formed;
the process conditions of the reactive ion etching technology are as follows: CF (compact flash) 4 Flow rate of 44sccm, O 2 The flow is 6sccm, the pressure is 16mT, and the power is 270W;
and 5, depositing metal in the source groove 5 and the ohmic groove 6to form a source electrode 7 and an ohmic electrode 8.
Manufacturing a mask on the passivation layer 4, the source electrode groove 5 and the ohmic groove 6 for the second time, and respectively depositing Ti/Au/Ta/Au metal combinations with the thicknesses of 0.257 micrometers, 0.168 micrometers, 0.308 micrometers and 0.377 micrometers inside the source electrode groove 5 and the ohmic groove 6 by using an electron beam evaporation technology by using the mask; then carrying out rapid thermal annealing to finish the manufacture of the source electrode 7 and the ohmic electrode 8;
the technological conditions of the electron beam evaporation technology are as follows: under the vacuum degree of less than 1.9 multiplied by 10 -3 Pa, power 410W, evaporation rate
The process conditions of the rapid thermal annealing are as follows: the temperature was 870 ℃ for 35 s.
And 6, manufacturing a P-type array block groove 9.
Manufacturing a mask on the passivation layer 4, the source electrode 7 and the ohmic electrode 8 for the third time, etching the position, which is on the right side, in the middle of the passivation layer 4 by using reactive ion etching by using the mask until the upper surface of the barrier layer 3 is etched, and forming three P-type array block grooves 9 which are arranged at equal intervals in the front and back directions;
the etching process conditions are as follows: CF 4 Flow rate of 50sccm, O 2 The flow rate was 8sccm, the pressure was 18mT, and the power was 270W.
And 7, depositing a P-type material to form a P-type array block 10.
Making a mask on the passivation layer 4, the source electrode 7, the ohmic electrode 8 and the P-type array block groove 9 for the fourth time, and sputtering the mask in the P-type array block groove 9 by using a magnetron sputtering technology to form a layer with the thickness of 1000nm and the doping concentration of 5 multiplied by 10 15 cm -3 Forming three P-type array blocks 10;
the technological conditions of the magnetron sputtering technology are as follows: the sputtering power is 120W, the temperature is 300 ℃, the Ar flow is 22sccm, O 2 The flow rate was 33 sccm.
And 8, etching to form a Schottky groove 11 and an anode groove 12.
Making masks on the passivation layer 4, the source electrode 7, the ohmic electrode 8 and the P-type array block 10 for the fifth time, etching the right side of the P-type array block 10 by using reactive ion etching by using the masks, wherein the etching depth is 70nm, and forming four Schottky grooves 11 and four anode grooves 12;
the etching process conditions are as follows: CF (compact flash) 4 The flow rate was 48sccm, O 2 The flow was 6sccm, the pressure was 18mT, and the power was 270W.
And 9, depositing metal to form a Schottky electrode 13, an anode block 14 and interconnection metal 15.
Making masks on the passivation layer 4, the source electrode 7, the ohmic electrode 8, the P-type array block 10, the schottky groove 11 and the anode groove 12 for the sixth time, and depositing metal Ni with the thickness of 1520nm on the ohmic electrode 8, the schottky groove 11, the anode groove 12 and the P-type array block 10 by using the masks through an electron beam evaporation technology to form four schottky electrodes 13, four anode blocks 14 and interconnection metal 15; a diode structure is formed between the barrier layer 3 and the passivation layer 4, which are in contact with the schottky electrode 13 and the anode block 14;
the technological conditions of the electron beam evaporation technology are as follows: vacuum degree less than or equal to 1.6 multiplied by 10 -3 Pa, power set at 350W, evaporation rate at
And step 10, etching the passivation layer 4 to form a window 16.
A mask is manufactured on the passivation layer 4, the source electrode 7 and the interconnection metal 15 for the seventh time, the passivation layer 4 between the source electrode 7 and the P-type array block 10 is etched by utilizing the mask and using a reactive ion etching technology until the upper surface of the barrier layer 3 is etched, and a window 16 is formed;
the etching process conditions are as follows: CF (compact flash) 4 The flow rate was 48sccm, O 2 The flow was 6sccm, the pressure was 18mT, and the power was 270W.
And 11, sputtering a P-type material in the window 16 to form a P-type block 17.
An eighth mask is made on the passivation layer 4, the source electrode 7, the interconnection metal 15 and the window 16, by means of which a magnetron sputtering technique is used to sputter a layer with a thickness of 500nm and a doping concentration of 5 x 10 into the window 16 15 cm -3 To form a P-type block 17;
the technological conditions of the magnetron sputtering technology are as follows: sputtering power is 110W, temperature is 300 ℃, Ar flow is 20sccm, O 2 The flow rate was 30 sccm.
And step 12, depositing an undoped GaN material on the upper part of the P-type block 17 to manufacture an i-GaN block 18.
And depositing the undoped GaN material with the thickness of 500nm on the upper part of the P-type block 17 by using the mask manufactured for the eighth time again and adopting the metal organic chemical vapor deposition technology to form the i-GaN block 18.
The deposition process conditions are as follows: the temperature was 520 deg.C, the pressure was 48Torr, the hydrogen flow was 4400sccm, the ammonia flow was 4400sccm, and the gallium source flow was 22. mu. mol/min.
And step 13, depositing metal on the upper part of the i-GaN block 18 to form a grid electrode 19.
A mask is manufactured on the passivation layer 4, the source electrode 7, the interconnection metal 15 and the i-GaN block 18 for the ninth time, and the metal combination Ta/Au with the thickness of 0.034 mu m/0.127 mu m is deposited on the upper part of the i-GaN block 18 by using the mask through an electron beam evaporation technology to form a grid electrode 19; the source electrode 7, the grid electrode 19, the right ohmic electrode 8, the Schottky electrode 13 and the anode block 14 form a HEMT structure, and the HEMT device and the diode formed in the step 9 are compounded to form a power switch device to complete the manufacture of the whole device;
wherein the process conditions of the electron beam evaporation are as follows: vacuum degree less than 1.8X 10 -3 Pa, power of 500W, evaporation rate of less than
Example three: the barrier layer 3 with the thickness a of 3nm is manufactured on the silicon carbide substrate, and the passivation layer 4 is made of SiO 2 The thickness b of the material is 20nm, K is 3, N is 1, M is 3, the height c of the schottky electrode 13 and the anode block 14 is 44nm, and the P-type array block 10 and the P-type block 17 are both selected from GaN composite drain power transistors.
Step one, a transition layer 2 is manufactured on a silicon carbide substrate 1.
And (3) performing epitaxy on a GaN material with the thickness of 7.7 mu m on the silicon carbide substrate 1 by using a metal organic chemical vapor deposition technology under the process conditions that the temperature is 1050 ℃, the pressure is 43Torr, the hydrogen flow is 4400sccm, the ammonia flow is 4400sccm and the gallium source flow is 110 mu mol/min to finish the manufacture of the transition layer 2.
Step two, epitaxial Al 0.4 Ga 0.6 N, the barrier layer 3 is produced.
Using molecular beam epitaxy technique under vacuum degree of 1.0 × 10 -11 mbar, radio frequency power of 420W, and N as reactant 2 And Al with the thickness of 3nm is epitaxially grown on the GaN transition layer 2 under the process conditions of the high-purity Ga source and the high-purity Al source 0.4 Ga 0.6 N material forming the barrier layer 3.
Step three, depositing SiO 2 And a passivation layer 4 is produced.
Using plasma enhanced chemical vapor deposition at 240 deg.C and pressureA strong 1050mTorr, an RF power of 25W, N 2 O flow rate of 840sccm, SiH 4 SiO with the thickness of 20nm is deposited on the barrier layer 3 under the process condition of the flow rate of 200sccm 2 To produce the passivation layer 4.
And step four, etching to form a source electrode groove 5 and an ohmic groove 6.
A first mask is made on the upper part of the passivation layer 4, using the mask a reactive ion etching technique is used, in CF 4 Flow rate of 20sccm, O 2 And etching the left side and the right side of the passivation layer 4 at the same time under the process conditions of the flow rate of 2sccm, the pressure of 20mT and the bias voltage of 100V until the upper surface of the barrier layer 3 is etched to form a source groove 5 and an ohmic groove 6.
And step five, depositing metal in the source electrode groove 5 and the ohmic groove 6to form a source electrode 7 and an ohmic electrode 8.
A second mask is formed on the passivation layer 4, the source trenches 5 and the ohmic recesses 6, by means of which a electron beam evaporation technique is used in a vacuum of less than 1.8 x 10 -3 Pa, power 380W, evaporation rate
Under the process conditions of (1), depositing a metal combination Ti/Al/Mo/Au metal combination above the source electrode groove 5 and the ohmic groove 6, wherein the thicknesses of the metal combination Ti/Al/Mo/Au metal combination are 0.05 mu m, 0.014 mu m, 0.005 mu m and 0.008 mu m in sequence; then, rapid thermal annealing was performed at 860 ℃ for 30 seconds to form the source electrode 7 and the ohmic electrode 8.
And sixthly, etching to form the P-type array block groove 9.
Making a third mask on the passivation layer 4 and the source electrode 6, and performing reactive ion etching on the third mask in Cl 2 And etching the right part of the middle part of the passivation layer 4 by using the mask under the process conditions of 15sccm flow, 10mTorr pressure and 130W power until the upper surface of the barrier layer 3to form three P-type array block grooves 9 which are arranged front and back.
And step seven, depositing a P-type material to form a P-type array block 10.
On the passivation layer 4, the source electrode 7, the ohmic electrode 8 and the P-type arrayMaking a mask on the block grooves 9 for the fourth time, and depositing 20nm thick and 1 × 10 doping concentration in the two P-type array block grooves 9 by using the mask and using metal organic chemical vapor deposition technology under the process conditions that the temperature is 950 ℃, the pressure is 42Torr, the hydrogen flow is 4100sccm, the high-purity Mg source is used as a doping agent, the ammonia flow is 4100sccm and the gallium source flow is 100 μmol/min 22 cm -3 Three P-type array blocks 10 are formed.
And step eight, etching to form a Schottky groove 11 and an anode groove 12.
Making a mask on the passivation layer 4, the source electrode 7, the ohmic electrode 8 and the P-type array block 10 for the fifth time, and performing reactive ion etching on Cl by using a reactive ion etching technology 2 And etching the right side of the P-type array block 10 by using the mask under the process conditions of the flow of 15sccm, the pressure of 10mTorr and the power of 130W, wherein the etching depth is 44nm, and a Schottky groove 11 and three anode grooves 12 are formed.
Step nine, metal is deposited to form the schottky electrode 13, the anode block 14 and the interconnection metal 15.
Making a mask on the passivation layer 4, the source electrode 7, the ohmic electrode 8, the P-type array block 10, the schottky groove 11 and the anode groove 12 for the sixth time, and adopting an electron beam evaporation technology by using the mask to ensure that the vacuum degree is 1.6 multiplied by 10 -3 Pa, power 350W, evaporation rate
Under the process conditions of (1), depositing metal W above the ohmic electrode 8, the Schottky groove 11, the anode slot 12 and the P-type array block 10, making Schottky contact, and forming a Schottky electrode 13, three anode blocks 14 and interconnection metal 15; a diode structure is formed between the barrier layer 3 and the passivation layer 4 with which the schottky electrode 13 and the anode block 14 are in contact.
Step ten, the passivation layer 4 is etched to form the window 16.
A seventh mask is made on the passivation layer 4, the source electrode 7, the interconnection metal 15, using this mask, using reactive ion etching techniques in Cl 2 The source electrode 7 and the P-type array block are aligned under the process conditions of the flow rate of 18sccm, the pressure of 14mTorr and the power of 120WEtching the passivation layer 4 between the barrier layers 10 until the upper surface of the barrier layer 3 is etched to form a window 16;
step eleven sputtering P-type material in the window 16 to form a P-type block 17.
Making a mask on the passivation layer 4, the source electrode 7, the interconnection metal 15 and the window 16 for the eighth time, using the mask and using metal organic chemical vapor deposition technology, depositing 15nm thick and 1 × 10 doping concentration in the window 16 under the process conditions of 950 ℃ of temperature, 42Torr of pressure, 4100sccm of hydrogen flow, 4100sccm of high-purity Mg source as dopant, 4100sccm of ammonia flow and 100 μmol/min of gallium source flow 22 cm -3 Forming P-type block 17.
And a twelfth step of manufacturing an i-GaN block 18 on the upper part of the P-type block 17.
And depositing an undoped GaN material with the thickness of 17nm by using the mask manufactured in the eighth step and adopting a metal organic chemical vapor deposition technology on the upper part of the P-type block 17 under the process conditions of 500 ℃ of temperature, 46Torr of pressure, 4300sccm of hydrogen flow, 4300sccm of ammonia flow and 21 mu mol/min of gallium source flow to form the i-GaN block 18.
Step thirteen, depositing multiple layers of metal to form the gate 19.
Manufacturing a mask on the passivation layer 4, the source electrode 7, the interconnection metal 15 and the i-GaN block 18 for the ninth time, and sputtering metal combination Gd/Au with the thickness of 0.28 mu m/0.39 mu m on the upper part of the i-GaN block 18 by using a sputtering technology to form a grid electrode 19 by using the mask under the process conditions that the sputtering air pressure is 0.1Pa, the flow of Ar is 8sccm, the substrate temperature is fixed at 200 ℃, and the target material radio frequency power is 150W; and (3) forming a HEMT structure by the source electrode 7, the grid electrode 19, the ohmic electrode 8 on the right side, the Schottky electrode 13 and the anode block 14, and compounding the HEMT device with the diode formed in the ninth step to form a power switch device to complete the manufacture of the whole device.
In order to verify the effect of the present invention, the output characteristics and blocking characteristics of the device according to the third embodiment of the present invention are respectively simulated, and the result is shown in fig. 6, where: fig. 6(a) is an output characteristic graph, and fig. 6(b) is a bidirectional blocking characteristic graph.
As can be seen from fig. 6, the turn-on voltage of the device of the present invention is about 0.29V, the forward blocking voltage is 1836V, and the reverse blocking voltage is-1802V, which indicates that the device of the present invention can achieve a low turn-on voltage and has a better bidirectional blocking characteristic.
Claims (10)
1. A composite drain power transistor comprising, from bottom to top: substrate (1), transition layer (2), barrier layer (3), passivation layer (4), its characterized in that:
a source electrode groove (5) is formed in the left side of a passivation layer (4) on the upper portion of the barrier layer (3), and a source electrode (7) is arranged in the source electrode groove;
an ohmic groove (6) is formed in the rightmost side of the passivation layer (4), an ohmic electrode (8) is arranged in the groove, and the bottom of the ohmic electrode is in contact with the upper surface of the barrier layer (3);
the left side of the ohmic electrode (8) is sequentially provided with M anode blocks (14), N Schottky electrodes (13) and K P-type array blocks (10) from right to left, the lower parts of the anode blocks (14) and the Schottky electrodes (13) are located in the transition layer (2), and the lower surfaces of the P-type array blocks (10) are in contact with the upper surface of the barrier layer (3);
the upper surfaces of the ohmic electrode (8), the P-type array block (10), the Schottky electrode (13) and the anode block (14) are provided with interconnection metal (15) which is used for connecting the ohmic electrode (8), the P-type array block (10), the Schottky electrode (13) and the anode block (14) so as to keep the equal potentials of the parts;
a window (16) is formed in the passivation layer (4) between the source electrode (7) and the P-type array block (10), and a P-type block (17), an i-GaN block (18) and a grid electrode (19) are sequentially arranged in the passivation layer from bottom to top;
the source electrode (7), the grid electrode (19), the ohmic electrode (8) on the right side, the Schottky electrode (13) and the anode block (14) form a HEMT structure, a diode structure is formed between the Schottky electrode (13) and the anode block (14) and the barrier layer (3) and the passivation layer (4) which are in contact with the Schottky electrode and the anode block, and the HEMT and the diode are compounded to form a power switch device.
2. The device of claim 1, wherein:
the thickness a of the barrier layer (3) is 3 nm-100 nm;
the passivation layer (4)By means of SiO 2 、SiN、Al 2 O 3 、Sc 2 O 3 、HfO 2 、TiO 2 Wherein the thickness b is 20nm to 1000 nm.
3. The device of claim 1, wherein:
the source electrode (7) and the ohmic electrode (8) form ohmic contact with the barrier layer (3);
the Schottky electrode (13) and the anode block (14) form Schottky contact with the contacted barrier layer (3).
4. The device of claim 1, wherein: the K P-type array blocks (10) are distributed in a front and back mode at equal intervals, and the distance g between every two adjacent array blocks is larger than 0; the transverse distance d between each P-type array block (10) and the Schottky electrode (13) is larger than 0.
5. The device of claim 1, wherein:
the N Schottky electrodes (13) are distributed in the front and back at equal intervals, the interval h between every two adjacent electrodes is larger than 0, the Schottky electrodes (13) and the K P-type array blocks (10) are distributed in a staggered mode, N is larger than or equal to 1, and K is larger than or equal to 2;
the lateral spacing e between the Schottky electrode (13) and the anode block (14) is greater than 0.
6. The device according to claim 1, wherein the M anode blocks (14) are distributed front and back at equal intervals, the longitudinal interval i between two adjacent anode blocks is greater than 0, when the device is in a balanced state, a depletion region is generated between the anode blocks (14), a current path is pinched off by the depletion region, and M is greater than or equal to 2; the lateral spacing f between each anode block (14) and the ohmic electrode (8) is greater than 0; each anode block (14) has the same height c as the Schottky electrode (13), wherein c > a + b, wherein a is the thickness of the barrier layer (3) and b is the thickness of the passivation layer (4).
7. A manufacturing method of a composite drain power transistor is characterized by comprising the following steps:
A) extending GaN semiconductor materials on a substrate (1) to form a transition layer (2);
B) a GaN-based wide bandgap semiconductor material is extended on the transition layer (2) to form a barrier layer (3);
C) depositing a medium on the barrier layer (3) to form a passivation layer (4);
D) manufacturing a mask on the passivation layer (4) for the first time, simultaneously etching the left side and the right side of the passivation layer (4) by using the mask until the upper surface of the barrier layer (3) is etched to form a source electrode groove (5) and an ohmic groove (6);
E) manufacturing a mask on the passivation layer (4), the source electrode groove (5) and the ohmic groove (6) for the second time, depositing metal above the source electrode groove (5) and the ohmic groove (6) by using the mask, and performing rapid thermal annealing to form a source electrode (7) and an ohmic electrode (8);
F) manufacturing a mask on the passivation layer (4), the source electrode (7) and the ohmic electrode (8) for the third time, etching the middle part of the passivation layer (4) at the right position by using the mask until the upper surface of the barrier layer (3) to form K P-type array block grooves (9) which are arranged at the front and the back at equal intervals;
G) making masks on the passivation layer (4), the source electrode (7), the ohmic electrode (8) and the P-type array block groove (9) for the fourth time, and depositing a P-type material inside the P-type array block groove (9) by using the masks to form K P-type array blocks (10);
H) making a mask on the passivation layer (4), the source electrode (7), the ohmic electrode (8) and the P-type array block (10) for the fifth time, etching the right side of the P-type array block (10) by using the mask to the inside of the transition layer (2), and forming N Schottky grooves (11) and M anode grooves (12);
I) manufacturing a mask on the passivation layer (4), the source electrode (7), the ohmic electrode (8), the P-type array block (10), the Schottky groove (11) and the anode slot (12) for the sixth time, and depositing metal above the ohmic electrode (8), the Schottky groove (11), the anode slot (12) and the P-type array block (10) by using the mask to form N Schottky electrodes (13), M anode blocks (14) and interconnection metal (15);
J) manufacturing a mask on the passivation layer (4), the source electrode (7) and the interconnection metal (15) for the seventh time, etching the passivation layer (4) between the source electrode (7) and the P-type array block (10) by using the mask until the upper surface of the barrier layer (3) is etched, and forming a window (16);
K) making a mask on the passivation layer (4), the source electrode (7), the interconnection metal (15) and the window (16) for the eighth time, and depositing the mask in the window (16) to a thickness of 10-500 nm and a doping concentration of 5 multiplied by 10 15 cm -3 ～1×10 22 cm -3 A P-type block (17);
l) utilizing the mask manufactured at the eighth time to epitaxially form an i-GaN block (18) with the thickness of 10 nm-500 nm on the upper part of the P-type block (17);
and M) manufacturing a mask on the passivation layer (4), the source electrode (7), the interconnection metal (15) and the i-GaN block (18) for the ninth time, and depositing metal on the upper part of the i-GaN block (18) by using the mask to form a grid electrode (19) to finish the manufacturing of the whole device.
8. The method according to claim 7, characterized in that the epitaxy process in steps A), B), G), K), L) comprises: metal organic chemical vapor deposition technology, plasma enhanced chemical vapor deposition technology, atomic layer deposition technology, molecular beam epitaxy technology.
9. Method according to claim 7, characterized in that the technique of producing the passivation layer (4) in step C) comprises: chemical vapor deposition technology, atomic layer deposition technology and radio frequency magnetron reactive sputtering technology.
10. The method of claim 7, wherein: the etching process comprises the following process conditions: CF (compact flash) 4 The flow rate is 40-45 sccm, O 2 Flow rate of 5-10 sccm, pressure of 15-25 mT, power of 180-270W or Cl 2 The flow rate is 12-20 sccm, the pressure is 7-15 mT, and the power is 80-130W.
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| CN202210587495.7A CN114937698A (en) | 2022-05-25 | 2022-05-25 | Composite drain power transistor |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210587495.7A CN114937698A (en) | 2022-05-25 | 2022-05-25 | Composite drain power transistor |
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