CN114141872A - Enhanced GaN-based composite switch device and manufacturing method thereof - Google Patents

Enhanced GaN-based composite switch device and manufacturing method thereof Download PDF

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CN114141872A
CN114141872A CN202111439008.4A CN202111439008A CN114141872A CN 114141872 A CN114141872 A CN 114141872A CN 202111439008 A CN202111439008 A CN 202111439008A CN 114141872 A CN114141872 A CN 114141872A
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gan
anode
barrier layer
source electrode
layer
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毛维
裴晨
杨翠
杜鸣
马佩军
张鹏
张进成
郝跃
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Xidian University
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    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
    • H—ELECTRICITY
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
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    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT

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Abstract

The invention discloses an enhanced GaN-based composite switch device and a manufacturing method thereof, which mainly solve the problems of unidirectional conduction and unidirectional blocking of the existing GaN-based enhanced power switch device. It includes from bottom to top: the left side and the right side of the upper part of the barrier layer are respectively provided with m left and right P-GaN islands, the front side and the rear side of the left island and the right island are respectively provided with a left isolation groove and a right isolation groove, the left side of the left island is crossly distributed with a left source electrode and a left anode, the left source electrode is connected with the left anode through a left electrode, the right side of the right island is crossly distributed with a right source electrode and a right anode, the right source electrode is connected with the right anode through a right electrode, the left island and the right island are respectively provided with a left grid electrode and a right grid electrode, the grid electrodes are partially covered by the passivation layer, and the left island and the right island are connected with the corresponding right and left anodes through the barrier layer to form a diode and triode composite structure. The invention can improve the integration level of the device, realize the bidirectional conduction and bidirectional blocking characteristics, and can be used as a power switch device.

Description

Enhanced GaN-based composite switch device and manufacturing method thereof
Technical Field
The invention belongs to the technical field of microelectronics, and particularly relates to an enhanced GaN-based composite switch device which can be used as a basic device of a power electronic system.
Technical Field
The green, low-carbon, energy-saving and emission-reduction effects become the key of sustainable development of human society, and high-performance power switching transistors are vigorously researched and developed to remarkably improve the efficiency and the overall performance of a power electronic system, so that the power switching transistor is one of effective ways for realizing sustainable development. The normally-off gallium nitride-based high-electron-mobility transistor based on the P-type cap layer, namely the gallium nitride-based enhanced power switch transistor, can realize the characteristics of low on-resistance, fast switching speed, high breakdown voltage and the like by virtue of the characteristics of wide forbidden band, high saturated electron drift speed, strong breakdown electric field, stable chemical property and the like of a gallium nitride material, and remarkably improves the performance of a power electronic system. Therefore, the high-performance gallium nitride-based enhanced power switch transistor has very wide and special application prospect in the fields of national economy and military.
The traditional gallium nitride-based enhancement type power switch transistor is based on a GaN-based heterojunction structure and comprises the following components: the structure comprises a substrate 1, a transition layer 2, a barrier layer 3, a P-GaN gate 4, a source electrode 5, a drain electrode 6 and gate metal 7; a source electrode 5 is deposited on the left side of the upper portion of the barrier layer 3, a drain electrode 6 is deposited on the right side of the upper portion of the barrier layer 3, a P-GaN gate 4 is deposited on the middle portion of the upper portion of the barrier layer 3, and a gate metal 7 is deposited on the upper portion of the P-GaN gate 4, as shown in FIG. 1.
However, in the conventional GaN-based enhancement mode power switching transistor, the current in the device can only be conducted in one direction when in an on state and the drain potential of the device can only be higher than the source potential when in an off state, i.e., the conventional GaN-based enhancement mode power switching transistor can only achieve one-way conduction and one-way blocking, see Gate and barrier layer design of E-mode GaN HEMT with p-GaN Gate structure, 201920 th International Conference on Electronic Packaging Technology (ICEPT),2019, 1-4. The requirements of the prior multi-level voltage type inverter, the alternating current-alternating current frequency converter and other fields on the power switch transistor with the bidirectional conduction and bidirectional blocking characteristics cannot be met. Therefore, it is necessary and urgent to develop and develop a high-performance gan-based enhancement-type power switching transistor with simple process and bidirectional conduction and blocking characteristics.
Disclosure of Invention
The invention aims to provide an enhanced GaN-based composite switch device and a manufacturing method thereof aiming at the defects of the prior art, so as to realize the bidirectional conduction and bidirectional blocking characteristics, reduce the loss, simplify the manufacturing process and improve the integration level.
To achieve the above object, the enhanced GaN-based composite switching device of the present invention comprises, from bottom to top: a substrate 1, a transition layer 2, a barrier layer 3 and a passivation layer 8; the method is characterized in that:
the left side and the right side of the upper part of the barrier layer 3 are respectively provided with m left P-GaN islands 4 which are arranged in parallel at equal intervals and m right P-GaN islands 5 which are arranged in parallel at equal intervals, the front side and the rear side of each left P-GaN island 4 are respectively provided with a left isolation groove 6, the front side and the rear side of each right P-GaN island 5 are respectively provided with a right isolation groove 7, and the left P-GaN islands 4 and the right P-GaN islands 5 are distributed in a crossed manner;
the left sides of the m left P-GaN islands 4 are provided with left source electrodes 9, the left sides of the m right P-GaN islands 5 are provided with left anodes 11, the left sides of the left source electrodes 9 and the left anodes 11 are provided with left electrodes 13 in parallel, and the source electrodes and the anodes are partially covered by the left electrodes and are electrically connected;
the right sides of the m left P-GaN islands 4 are provided with right anodes 12, the right sides of the m right P-GaN islands 5 are provided with right source electrodes 10, the right sides of the right source electrodes 10 and the right anodes 12 are provided with right electrodes 14 in parallel, and the source electrodes and the anodes are partially covered by the right electrodes and are electrically connected;
the upper parts of the m left P-GaN islands 4 are provided with left grids 15, the upper parts of the m right P-GaN islands 5 are provided with right grids 16, the two sides of the left and right grids and the m left and right P-GaN islands are covered by passivation layers 8, the left P-GaN island 4 at the lower part of the left grid 15 and the corresponding right anode 12 thereof are connected through barrier layers 3, and the right P-GaN island 5 at the lower part of the right grid 16 and the corresponding left anode 11 thereof are connected to form a composite structure of a diode and a triode;
further, the substrate 1 is made of sapphire, silicon carbide, silicon, graphene or other materials;
further, the barrier layer 3 has a thickness a of 2nm to 60 nm;
further, the m left P-GaN islands 4 are the same in size, all have a thickness of b, the right edges of the m left P-GaN islands are aligned, and the distance between two adjacent left P-GaN islands 4 is w;
further, the m right P-GaN islands 5 have the same size and thickness of b, the left edges are aligned, and the distance between two adjacent right P-GaN islands 5 is w; the horizontal distance t between the m right P-GaN islands 5 and the m left P-GaN islands 4 is more than or equal to 1 μm.
Furthermore, the left isolation grooves 6 are the same in size, the lower ends of the left isolation grooves are located in the transition layer 2, and the distance c between the lower ends of the left isolation grooves 6 and the interface between the barrier layer 3 and the transition layer 2 is larger than 40 nm; the right edge of each left isolation groove 6 is aligned with the right edges of the m left P-GaN islands 4, and the left edge of each left isolation groove 6 is positioned on the left side of the right edge of the left anode 11;
furthermore, the right isolation grooves 7 are the same in size, the lower ends of the right isolation grooves are located in the transition layer 2, and the distance c between the lower ends of the right isolation grooves 7 and the interface between the barrier layer 3 and the transition layer 2 is larger than 40 nm; the left edge of each right isolation groove 7 is aligned with the left edges of the m right P-GaN islands 5, and the right edge of each right isolation groove 7 is positioned on the right side of the left edge of the right anode 12;
further, the m left source electrodes 9 and the m right source electrodes 10 are all located on the upper portion of the barrier layer 3, and the lower ends of the m left anode electrodes 11 and the m right anode electrodes 12 are all located inside the barrier layer 3 or inside the transition layer 2;
further, the m left source electrodes 9 and the m left anode electrodes 11 are alternately arranged, and the right edges of the source electrodes and the right edges of the left anode electrodes are located in the same vertical plane;
further, the m right source electrodes 10 and the m right anode electrodes 12 are alternately arranged, and left edges of the source electrodes and the anode electrodes are all located in the same vertical plane.
In order to achieve the above object, the method for manufacturing an enhanced GaN-based composite switching device according to the present invention comprises the steps of:
A) a GaN-based wide bandgap semiconductor material is epitaxially grown on a substrate 1 by using an epitaxial process to form a transition layer 2;
B) extending a GaN-based wide bandgap semiconductor material on the transition layer 2 by using an epitaxial process to form a barrier layer 3 with the thickness of a;
C) and manufacturing a left P-GaN island 4 and a right P-GaN island 5 on the barrier layer 3:
C1) a P-type GaN semiconductor material is epitaxially formed on the barrier layer 3 by an epitaxial process to have a thickness of b and a doping concentration of 1 × 1016～1×1022cm-3The P-type GaN layer of (1);
C2) manufacturing a mask on the P-GaN layer for the first time, etching the P-GaN layer by using the mask until the upper surface of the barrier layer 3 is etched to form m left P-GaN islands 4 and m right P-GaN islands 5;
D) making masks on the barrier layer 3, the left P-GaN island 4 and the right P-GaN island 5 for the second time, and sequentially etching the barrier layer 3 and the transition layer 2 by using the masks to form a left isolation groove 6 and a right isolation groove 7, wherein the distance c between the lower ends of the left isolation groove 6 and the right isolation groove 7 and the interfaces of the barrier layer 3 and the transition layer 2 is more than 40 nm;
E) depositing a passivation layer 8 on the barrier layer 3, the left P-GaN island 4, the right P-GaN island 5, the left isolation groove 6 and the right isolation groove 7;
F) manufacturing a left source electrode 9 and a right source electrode 10 on the barrier layer 3;
F1) a mask is manufactured on the passivation layer 8 for the third time, the passivation layer 8 on the left side and the right side is etched by the mask until the upper surface of the barrier layer 3 is etched, and m source electrode half grooves on the left side and m source electrode half grooves on the right side are formed;
F2) depositing multiple layers of metal in the source electrode half-grooves by using a metal deposition process by using the mask made for the third time again, and depositing N2Performing rapid thermal annealing for 30s in the atmosphere to form m left source electrodes 9 and m right source electrodes 10;
G) a left anode 11 and a right anode 12 are formed on and in the barrier layer 3:
G1) fourth-time masks are made on the barrier layer 3, the passivation layer 8, the left source electrode 9 and the right source electrode 10, the masks are utilized to etch the passivation layer 8 on the left side and the right side until the upper surface of the barrier layer 3, m anode half grooves on the left side and m anode half grooves on the right side are formed, and the anode half grooves and the source electrode half grooves in F1) are alternately arranged;
G2) making masks on the barrier layer 3, the passivation layer 8, the left source electrode 9, the right source electrode 10, the left m anode half grooves and the right m anode half grooves for the fifth time, etching the left and right anode half grooves again by using the masks, wherein the etching depth is greater than 0 mu m, and forming left m anode grooves and right m anode grooves;
G3) depositing a plurality of layers of metal in the anode grooves by using a metal deposition process by using the mask manufactured for the fifth time again to form Schottky contact, and finishing the manufacture of the m left anodes 11 and the m right anodes 12;
H) making masks on the barrier layer 3, the passivation layer 8, the left source electrode 9, the right source electrode 10, the left anode 11 and the right anode 12 for the sixth time, depositing metal on the barrier layer 3, the left source electrode 9, the right source electrode 10, the left anode 11 and the right anode 12 by using a metal deposition process by using the masks to form a left electrode 13 and a right electrode 14, wherein the left electrode 13 covers and electrically connects each left source electrode 9 and each left anode 11 partially, and the right electrode 14 covers and electrically connects each right source electrode 10 and each right anode 12 partially;
I) a mask is manufactured on the barrier layer 3, the passivation layer 8, the left source electrode 9, the right source electrode 10, the left anode 11, the right anode 12, the left electrode 13 and the right electrode 14 for the seventh time, the m left P-GaN islands 4 and the passivation layer 8 on the upper parts of the m right P-GaN islands 5 are etched by using the mask until the upper surfaces of the P-GaN islands are etched, and m left gate grooves and m right gate grooves are formed;
J) and depositing a plurality of layers of metal in the m left and right gate grooves by using the mask manufactured for the seventh time by using a metal deposition process to respectively form a left gate 15 and a right gate 16, thereby finishing the manufacture of the whole device.
Compared with the traditional gallium nitride-based enhanced power switch device, the device has the following advantages:
firstly, in the device, all the left anodes and the right anodes are in Schottky contact, all the left source electrodes and the right source electrodes are in ohmic contact, all the left source electrodes are electrically connected with the left anodes, and all the right source electrodes are electrically connected with the right anodes, so that the unidirectional conduction and unidirectional blocking characteristics of the traditional gallium nitride-based enhanced power switch transistor can be realized by controlling the voltages on the left grid electrode and the right grid electrode, the conduction loss of the device is reduced, and the bidirectional conduction and bidirectional blocking characteristics can also be realized.
Secondly, the device of the invention adopts the multiplexing barrier layer active region between the left grid 15 and the right grid 16, thereby greatly saving the area of the device and improving the integration level of the switch device.
Thirdly, the manufacturing process of the device is compatible with that of the traditional gallium nitride-based enhanced power switch device, so that the manufacturing process is simple.
Simulation results show that the device has good reliability and output power characteristics.
Drawings
Fig. 1 is a block diagram of a conventional gallium nitride based enhancement mode power switching transistor;
FIG. 2 is a top view structural diagram of the enhanced GaN-based composite switching device of the present invention;
FIG. 3 is a cross-sectional view along AB of FIG. 2;
FIG. 4 is a cross-sectional view along the CD of FIG. 2;
FIG. 5 is a cross-sectional view taken along EF of FIG. 2;
FIG. 6 is a schematic overall flow chart of the present invention for fabricating an enhanced GaN-based composite switch device;
fig. 7 is a graph of test results of chopper modulation of an ac signal using the device of the present invention.
Detailed Description
Embodiments and effects of the present invention will be described in further detail below with reference to the accompanying drawings.
Referring to fig. 2, 3, 4, and 5, the enhanced GaN-based composite switching device according to the present example includes: the structure comprises a substrate 1, a transition layer 2, a barrier layer 3, m left P-GaN islands 4, m right P-GaN islands 5, a left isolation groove 6, a right isolation groove 7, a passivation layer 8, m left source electrodes 9, m right source electrodes 10, m left anodes 11, m right anodes 12, a left electrode 13, a right electrode 14, m left grid electrodes 15 and m right grid electrodes 16, wherein m is larger than or equal to 1. Wherein:
the substrate 1 is made of sapphire, silicon carbide, silicon, graphene or other materials;
the transition layer 2 is positioned on the upper part of the substrate 1 and is composed of a plurality of layers of same or different GaN-based wide bandgap semiconductor materials, and the thickness of the transition layer is 0.5-50 mu m;
the barrier layer 3 is positioned on the upper part of the transition layer 2 and is composed of a plurality of layers of same or different GaN-based wide bandgap semiconductor materials, and the thickness of the barrier layer is 2 nm-60 nm;
the m left P-GaN islands 4 are positioned on the left side of the upper part of the barrier layer 3, each left P-GaN island 4 has the same size, the thickness b is 5 nm-200 nm, and the doping concentration is 1 multiplied by 1016～1×1022cm-3And the right edges are aligned, and the distance between two adjacent left P-GaN islands 4 is w; the front side and the rear side of each left P-GaN island 4 are respectively provided with a left isolation groove 6, the left isolation grooves have the same size, the lower ends of the left isolation grooves are positioned in the transition layer 2, and the distance c between the lower end of each left isolation groove and the interface between the barrier layer 3 and the transition layer 2>40nm, and the right edge of each left isolation groove 6 is aligned with the right edges of the m left P-GaN islands 4;
the m right P-GaN islands 5 are positioned on the right side of the upper part of the barrier layer 3, each right P-GaN island 5 has the same size, the thickness b is 5 nm-200 nm, and the doping concentration is 1 multiplied by 1016～1×1022cm-3And the left edges are aligned, and the distance between two adjacent right P-GaN islands 5 is w; the front side and the rear side of each right P-GaN island 5 are respectively provided with a right isolation groove 7, the right isolation grooves are the same in size, the lower ends of the right isolation grooves are positioned in the transition layer 2, and the distance c between the lower end of each right isolation groove and the interface between the barrier layer 3 and the transition layer 2>40nm and left of each right isolation trench 7The edges are aligned with the left edges of the m right P-GaN islands 5; the horizontal distance t between the m right P-GaN islands 5 and the m left P-GaN islands 4 is more than or equal to 1 mu m;
the passivation layer 8 is positioned on the upper part of the barrier layer 3 and conformally covers the left P-GaN island 4, the right P-GaN island 5, the left isolation grooves 6 and the right isolation grooves 7;
the m left source electrodes 9 are positioned on the left side of the left P-GaN island 4, the m right source electrodes 10 are positioned on the right side of the right P-GaN island 5, the left source electrodes 9 and the right source electrodes 10 are equal in size, the distance between every two adjacent left source electrodes 9 is equal to the distance between every two adjacent right source electrodes 10, and the source electrodes are positioned on the upper portion of the barrier layer 3 and form ohmic contact with the barrier layer 3;
the m right anodes 12 are positioned on the right side of the left P-GaN island 4, the m left anodes 11 are positioned on the left side of the right P-GaN island 5, the left anodes 11 and the right anodes 12 are equal in size, the distance between every two adjacent left anodes 11 is equal to the distance between every two adjacent right anodes 12, the lower ends of the anodes are positioned in the barrier layer 3 or in the transition layer 2 and form Schottky contact with the barrier layer 3 and the transition layer 2; the right edge of each left anode 11 is positioned on the right side of the left edge of the left isolation groove 6; the left edge of each right anode 12 is positioned on the left side of the right edge of the right isolation groove 7;
the m left source electrodes 9 and the m left anodes 11 are alternately arranged, and the right edges of the source electrodes and the right edges of the anodes are positioned in the same vertical plane;
the m right source electrodes 10 and the m right anodes 12 are alternately arranged, and the left edges of the source electrodes and the left edges of the anodes are located in the same vertical plane;
the left electrode 13 is positioned at the left side of each left source electrode 9 and each left anode electrode 11, and partially covers and electrically connects the source electrodes and the anode electrodes;
the right electrode 14 is positioned at the right side of each right source electrode 10 and each right anode electrode 12, and partially covers and electrically connects the source electrodes and the anode electrodes;
the m left gates 15 are all located on the upper portion of the left P-GaN island 4, and two sides of each left gate 15 are covered by the passivation layer 8;
the m right gates 16 are all positioned at the upper part of the right P-GaN island 5, and two sides of each right gate 16 are covered by the passivation layer 8;
the left P-GaN islands 4 at the lower parts of the m left gates 15 and the corresponding right anodes 12 thereof, and the right P-GaN islands 5 at the lower parts of the m right gates 16 and the corresponding left anodes 11 thereof are connected through barrier layers 3, so that a composite structure of a diode and a triode is formed.
Referring to fig. 6, the enhanced GaN-based composite switching device fabricated by the present invention provides the following three examples.
The first embodiment is as follows: a sapphire substrate is adopted, the thickness a of a barrier layer 3 is 2nm, the number of left P-GaN islands 4 and right P-GaN islands 5 is 1, the thickness b is 5nm, the doping concentration is 5 multiplied by 1017cm-3The enhanced GaN-based composite switching device of (1).
Step 1, a GaN material is epitaxially grown on a sapphire substrate 1 to form a transition layer 2.
1.1) a GaN material with the thickness of 30nm is epitaxially grown on a sapphire substrate 1 by using a metal organic chemical vapor deposition technology, and the process conditions are as follows: the temperature is 530 ℃, the pressure is 45Torr, the hydrogen flow is 4500sccm, the ammonia flow is 4500sccm, and the gallium source flow is 20 mu mol/min;
1.2) extending a GaN material with the thickness of 0.97 mu m on the GaN material by using a metal organic chemical vapor deposition technology to form an undoped transition layer 2; the process conditions are as follows: the temperature is 960 deg.C, the pressure is 45Torr, the hydrogen flow is 4400sccm, the ammonia flow is 4400sccm, and the gallium source flow is 120 μmol/min.
Step 2, depositing undoped Al on the undoped GaN transition layer 20.4Ga0.6N forms the barrier layer 3.
Depositing undoped Al with a thickness of 2nm and an aluminum composition of 0.4 on the GaN transition layer 2 by using a metal organic chemical vapor deposition technique0.4Ga0.6An N barrier layer 3; the process conditions are as follows: the temperature is 980 ℃, the pressure is 45Torr, the hydrogen flow is 4400sccm, the ammonia flow is 4400sccm, the gallium source flow is 35 mu mol/min, and the aluminum source flow is 7 mu mol/min.
And 3, manufacturing a left P-GaN island 4 and a right P-GaN island 5 on the barrier layer 3.
3.1) epitaxial thickness b of 5nm and doping concentration of 5X 10 on the barrier layer 3 using molecular beam epitaxy17cm-3Of the P typeA GaN semiconductor material forming a P-type GaN layer; the process conditions of molecular beam epitaxy are as follows: vacuum degree of 1.0X 10 or less-10mbar, radio frequency power of 400W, and N as reactant2A high purity Ga source;
3.2) manufacturing a mask on the P-GaN layer formed in the step 3.1) for the first time, etching the P-GaN layer by using the mask until the upper surface of the barrier layer 3 is etched to form 1 left P-GaN island 4 and 1 right P-GaN island 5, wherein the distance t between the left P-GaN island 4 and the right P-GaN island 5 is 1 mu m; the etching adopts the following process conditions: cl2Flow rate of 15sccm, pressure of 10mTorr, and power of 100W.
And 4, manufacturing a left isolation groove 6 and a right isolation groove 7.
Manufacturing masks on the barrier layer 3, the left P-GaN island 4 and the right P-GaN island 5 for the second time, etching the barrier layer 3 and the transition layer 2 in sequence by using the masks to finish the manufacture of each left isolation groove 6 and each right isolation groove 7, wherein the lower ends of each left isolation groove 6 and each right isolation groove 7 are positioned in the transition layer 2 and are spaced from the interface between the barrier layer 3 and the transition layer 2 by the distance c>40 nm; the etching adopts the following process conditions: cl2The flow rate is 18sccm, the pressure is 14mTorr, and the power is 120W;
and 5, manufacturing a passivation layer 8.
A passivation layer 8 with the thickness of 350nm is deposited on the barrier layer 3, the left P-GaN island 4, the right P-GaN island 5, the left isolation groove 6 and the right isolation groove 7 by adopting a plasma enhanced chemical vapor deposition technology, and the process conditions for depositing the passivation layer 8 are as follows: n is a radical of2O flow rate of 840sccm, SiH4The flow rate was 300sccm, the temperature was 250 ℃, the RF power was 10W, and the pressure was 2000 mT.
And 6, manufacturing a left source electrode 9 and a right source electrode 10 on the barrier layer 3.
6.1) making a mask on the passivation layer 8 for the third time, etching the passivation layer 11 on the left side and the right side by using the mask until the upper surface of the barrier layer 3, and forming 1 source electrode half groove on the left side and 1 source electrode half groove on the right side, wherein the etching adopts the following process conditions: cl2The flow is 15sccm, the pressure is 10mTorr, and the power is 100W;
6.2) masks on the left and right sides with the third fabricationDepositing a plurality of layers of metal in the 2 source electrode half-grooves, wherein the deposited metal adopts Ti/Al/Au metal combination, namely Ti, Al and Au are respectively arranged from bottom to top, the thicknesses of the deposited metal are respectively 0.012 mu m/0.053 mu m/0.035 mu m, and performing rapid thermal annealing to form a left source electrode 9 and a right source electrode 10, and the process conditions adopted by the deposited metal are as follows: vacuum degree of 1.7X 10-3Pa, power 400W, evaporation rate
Figure BDA0003377762200000071
The process conditions adopted by the rapid thermal annealing are as follows: the temperature was 850 ℃ and the time was 35 s.
And 7, manufacturing a left anode 11 and a right anode 12 on the upper part and the inner part of the barrier layer 3.
7.1) making masks on the barrier layer 3, the passivation layer 8, the left source electrode 9 and the right source electrode 10 for the fourth time, etching the passivation layers 10 on the left side and the right side by using the masks until the upper surface of the barrier layer 3 is etched to form 1 anode half-groove on the left side and 1 anode half-groove on the right side, wherein the anode half-grooves and the source electrode half-grooves in the 6.1) are alternately arranged; the etching adopts the following process conditions: cl2The flow is 15sccm, the pressure is 10mTorr, and the power is 100W;
7.2) making masks on the barrier layer 3, the passivation layer 8, the left source electrode 9, the right source electrode 10, the left 1 anode half groove and the right 1 anode half groove for the fifth time, etching the anode half grooves on the left side and the right side again by using the masks, wherein the etching depth is 1nm, and forming 1 anode groove on the left side and 1 anode groove on the right side; the etching adopts the following process conditions: cl2The flow rate is 20sccm, the pressure is 25mTorr, and the power is 125W;
7.3) depositing a plurality of layers of metal in the 2 anode grooves by using the mask again, wherein the deposited metal is a W/Au metal combination, namely the lower layer is W, the upper layer is Au, the thicknesses of the deposited metal and the barrier layer 3 are respectively 0.025 mu m/0.10 mu m, Schottky contact is formed between the deposited metal and the barrier layer, and the left anode 11 and the right anode 12 are manufactured; the process conditions adopted for depositing the metal are as follows: vacuum degree of 1.7X 10-3Pa, power 380W, evaporation rate
Figure BDA0003377762200000081
And 8, manufacturing a left electrode 13 and a right electrode 14.
Making masks on the barrier layer 3, the passivation layer 8, the left source electrode 9, the right source electrode 10, the left anode 11 and the right anode 12 for the sixth time, and depositing metal by using the masks to cover the barrier layer 3, the left source electrode 9, the right source electrode 10, the left anode 11 and the right anode 12 to form a left electrode 13 and a right electrode 14; wherein the left electrode 13 electrically connects the 1 left source 9 with the 1 left anode 11, and the right electrode 14 electrically connects the 1 right source 10 with the 1 right anode 12; wherein the deposited metal is Al/Au combination, namely the lower layer is Al and the upper layer is Au, and the thicknesses of the Al/Au combination and the Au combination are respectively 0.035 mu m/0.015 mu m; the process conditions adopted for depositing the metal are as follows: vacuum degree of 1.6X 10-3Pa, power of 200W, evaporation rate of
Figure BDA0003377762200000082
And 9, manufacturing a left grid 15 and a right grid 16.
9.1) making masks on the barrier layer 3, the passivation layer 8, the left source electrode 9, the right source electrode 10, the left anode 11, the right anode 12, the left electrode 13 and the right electrode 14 for the seventh time, respectively etching the passivation layers 8 on the upper parts of the 1 left P-GaN island 4 and the 1 right P-GaN island 5 by using the masks until the upper surfaces of the P-GaN islands are etched to form a gate groove; the etching adopts the following process conditions: cl2The flow rate is 18sccm, the pressure is 14mTorr, and the power is 120W;
9.2) depositing a metal combination Ni/Au in the gate groove by using the mask manufactured for the seventh time again, namely, the lower layer is Ni, the upper layer is Au, and a left gate 15 and a right gate 16 are respectively formed; the process conditions adopted for depositing the metal are as follows: vacuum degree of 1.5X 10- 3Pa, power 300W, evaporation rate
Figure BDA0003377762200000083
And finishing the manufacture of the whole device.
Example two: adopting a silicon carbide substrate, manufacturing a barrier layer 3 with the thickness a of 8nm, five left P-GaN islands 4 and five right P-GaN islands 5, the thickness b of 70nm and the doping concentration of 1 multiplied by 1016cm-3The enhanced GaN-based composite switching device of (1).
Step one, a transition layer 2 is made by extending AlN and GaN materials on a silicon carbide substrate 1 from bottom to top.
1a) Extending an undoped AlN material with the thickness of 100nm on the silicon carbide substrate 1 by using a metal organic chemical vapor deposition technology under the process conditions that the temperature is 1000 ℃, the pressure is 45Torr, the hydrogen flow is 4600sccm, the ammonia flow is 4600sccm and the aluminum source flow is 5 mu mol/min;
1b) a metal organic chemical vapor deposition technology is used for forming a transition layer 2 by extending a GaN material with the thickness of 4.9 mu m on the AlN material under the process conditions that the temperature is 1000 ℃, the pressure is 45Torr, the hydrogen flow is 4600sccm, the ammonia flow is 4600sccm and the gallium source flow is 120 mu mol/min.
Step two, depositing undoped Al on the GaN transition layer 20.15Ga0.85N forms the barrier layer 3.
Using metal organic chemical vapor deposition technology to deposit undoped Al with the thickness of 8nm and the aluminum component of 0.15 on the GaN transition layer 2 under the process conditions that the temperature is 980 ℃, the pressure is 45Torr, the hydrogen flow is 4600sccm, the ammonia flow is 4600sccm, the gallium source flow is 37 mu mol/min and the aluminum source flow is 7 mu mol/min0.15Ga0.85An N barrier layer 3.
And step three, manufacturing a left P-GaN island 4 and a right P-GaN island 5 on the barrier layer 3.
3a) Using molecular beam epitaxy technique under vacuum degree of 1.0 × 10-10mbar, radio frequency power of 420W, and N as reactant2Under the process conditions of the high-purity Ga source, the epitaxial thickness b on the barrier layer 3 is 70nm, and the doping concentration is 1 multiplied by 1016cm-3Forming a P-type GaN layer;
3b) first forming a mask on the P-GaN layer formed in 3a), using the mask to form Cl2Etching the P-GaN layer under the process conditions of the flow of 18sccm, the pressure of 13mTorr and the power of 80W till the upper surface of the barrier layer 3 to form five left P-GaN islands 4 and five right P-GaN islands 5, wherein the five left P-GaN islands 4 and the five right P-islands 5 are formedThe spacing t between the GaN islands 5 is 5 μm.
And step four, manufacturing a left isolation groove 6 and a right isolation groove 7.
Making a mask on the barrier layer 3, the left P-GaN island 4 and the right P-GaN island 5 for the second time, and using the mask to form a layer of Cl2Etching the barrier layer 3 and the transition layer 2 in sequence under the process conditions of 18sccm flow, 14mTorr pressure and 120W power to complete the manufacture of each left isolation groove 6 and each right isolation groove 7, wherein the lower ends of each left isolation groove 6 and each right isolation groove 7 are positioned in the transition layer 2, and the distance c between the lower ends of each left isolation groove 6 and each right isolation groove 7 and the interface of the barrier layer 3 and the transition layer 2 is>40nm。
Fifthly, adopting plasma enhanced chemical vapor deposition technology on the barrier layer 3, the left P-GaN island 4, the right P-GaN island 5, the left isolation groove 6 and the right isolation groove 7, and depositing N2O flow rate of 900sccm, SiH4The passivation layer 8 is deposited with a thickness of 450nm under the process conditions of a flow of 340sccm, a temperature of 220 ℃, an RF power of 12W and a pressure of 2100 mT.
And step six, manufacturing a left source electrode 9 and a right source electrode 10 on the barrier layer 3.
6a) A third mask is formed on the passivation layer 8, using which a third Cl layer is formed2Etching the passivation layers 11 on the left side and the right side under the process conditions of 15sccm flow, 10mTorr pressure and 100W power until the upper surface of the barrier layer 3 to form five source electrode half grooves on the left side and five source electrode half grooves on the right side;
6b) using electron beam evaporation technique in the source electrode half-grooves at the left and right sides, and the vacuum degree is 1.7 multiplied by 10-3Pa, power 400W, evaporation rate
Figure BDA0003377762200000101
The deposited metal adopts Ti/Pd/Au metal combination, namely Ti, Pd and Au are respectively arranged from bottom to top, the thicknesses of the metals are respectively 0.015 mu m/0.050 mu m/0.035 mu m, and the metals are subjected to rapid thermal annealing for 35s at the temperature of 850 ℃ to form five left source electrodes 9 and five right source electrodes 10.
And step seven, manufacturing a left anode 11 and a right anode 1 on the upper part and in the barrier layer 3.
7a) Fourth, a mask is formed on the barrier layer 3, the passivation layer 8, the left source electrode 9 and the right source electrode 10, and the mask is used to mask Cl2Etching the passivation layers 10 on the left side and the right side under the process conditions of 15sccm flow, 10mTorr pressure and 100W power until the upper surface of the barrier layer 3 to form five anode half-grooves on the left side and five anode half-grooves on the right side, wherein the anode half-grooves and the source half-grooves in 6a) are alternately arranged;
7b) a mask is manufactured on the barrier layer 3, the passivation layer 8, the left source electrode 9, the right source electrode 10, the left 5 anode half grooves and the right 5 anode half grooves for the fifth time, and Cl is coated with the mask2Etching the anode half grooves on the left side and the right side again under the process conditions of 25sccm flow, 30mTorr pressure and 100W power, wherein the etching depth is 70nm, and forming five anode grooves on the left side and five anode grooves on the right side;
7c) the mask was reused under a vacuum of 1.9X 10-3Pa, power of 350W, evaporation rate of
Figure BDA0003377762200000102
Under the process conditions of (1), metal Ni/Pt/Au metal combinations are deposited in the ten anode grooves, namely Ni, Pt and Au are respectively arranged from bottom to top, the thicknesses of the metal combinations are respectively 0.019 mu m/0.030 mu m/0.031 mu m, Schottky contact is formed between the deposited metal and the barrier layer 3, and the manufacture of five left anodes 11 and five right anodes 12 is completed.
And step eight, manufacturing the left electrode 13 and the right electrode 14.
A mask was formed on the barrier layer 3, the passivation layer 8, the left source electrode 9, the right source electrode 10, the left anode 11, and the right anode 12 for the sixth time, and the mask was used to form a thin film in a degree of vacuum of 1.6 × 10-3Pa, power of 200W, evaporation rate of
Figure BDA0003377762200000103
Depositing metal to cover the barrier layer 3, the left source electrode 9, the right source electrode 10, the left anode 11, and the right anode 12 to form a left electrode 13 and a right electrode 14; wherein the left electrode 13 electrically connects the five left source electrodes 9 with the five left anodes 11, and the right electrode 14 electrically connects the five right source electrodes 10 with the five right anodesThe poles 12 are electrically connected; the deposited metal is Ti/Au, namely the lower layer is Ti and the upper layer is Au, and the thicknesses of the deposited metal and the upper layer are 0.045 mu m/0.025 mu m respectively.
And step nine, manufacturing a left grid 15 and a right grid 16.
9a) A mask is formed on the barrier layer 3, the passivation layer 8, the left source electrode 9, the right source electrode 10, the left anode 11, the right anode 12, the left electrode 13 and the right electrode 14 for the seventh time, and Cl is formed using the mask2Etching the passivation layers 8 on the upper parts of the five left P-GaN islands 4 and the five right P-GaN islands 5 under the process conditions of the flow rate of 18sccm, the pressure of 14mTorr and the power of 120W until the upper surfaces of the P-GaN islands are etched to form gate grooves;
9b) the mask manufactured for the seventh time is reused under the vacuum degree of 1.5 multiplied by 10-3Pa, power 300W, evaporation rate
Figure BDA0003377762200000111
Under the process conditions of (1), depositing a metal combination W/Au in the gate groove, namely a lower layer is W and an upper layer is Au, and respectively forming five left gates 15 and five right gates 16 to finish the manufacture of the whole device.
Example three: a silicon substrate is adopted, the thickness a of a barrier layer 3 is 60nm, the number of left P-GaN islands 4 and right P-GaN islands 5 is three, the thickness b is 200nm, the doping concentration is 1 multiplied by 1022cm-3The enhanced GaN-based composite switching device of (1).
And step A, epitaxially growing AlN and GaN materials on the silicon substrate 1 from bottom to top to manufacture a transition layer 2.
A1) Setting the process conditions of 800 ℃ of temperature, 40Torr of pressure, 4000sccm of hydrogen flow, 4000sccm of ammonia flow and 25 mu mol/min of aluminum source flow, and extending an AlN material with the thickness of 400nm on the silicon substrate 1 by using a metal organic chemical vapor deposition technology;
A2) setting the technological conditions of 980 deg.C, 45Torr pressure, 4000sccm hydrogen flow, 4000sccm ammonia flow and 120 μmol/min gallium source flow, and using metal organic chemical vapor deposition to epitaxially grow 8.6 μm GaN material on AlN material to complete the fabrication of the transition layer 2.
Step B, depositing undoped Al on the GaN transition layer 20.1Ga0.9N forms the barrier layer 3.
Setting the deposition process conditions of 980 ℃, 45Torr, 4500sccm of hydrogen flow, 4500sccm of ammonia flow, 36 mu mol/min of gallium source flow and 7 mu mol/min of aluminum source flow, and depositing undoped Al with the thickness of 60nm and the aluminum component of 0.1 on the GaN transition layer 2 by using the metal organic chemical vapor deposition technology0.1Ga0.9An N barrier layer 3.
And step C, manufacturing a left P-GaN island 4 and a right P-GaN island 5 on the barrier layer 3.
C1) Setting molecular beam epitaxy to vacuum degree of 1.0 × 10 or less-10mbar, radio frequency power of 400W, and N as reactant2The process conditions of the high-purity Ga source are that a molecular beam epitaxy technology is used, the epitaxial thickness b is 200nm, the doping concentration is 1 multiplied by 10 on the barrier layer 322cm-3Forming a P-type GaN layer;
C2) setting the technological conditions adopted by etching: cl2A mask is firstly manufactured on the P-GaN layer formed in C1) with the flow of 15sccm, the pressure of 10mTorr and the power of 100W, the P-GaN layer is etched by the mask until the upper surface of the barrier layer 3, three left P-GaN islands 4 and three right P-GaN islands 5 are formed, and the distance t between the three left P-GaN islands 4 and the three right P-GaN islands 5 is 20 micrometers.
And D, manufacturing a left isolation groove 6 and a right isolation groove 7.
Setting the technological conditions adopted by etching: cl2Making masks on the barrier layer 3, the left P-GaN island 4 and the right P-GaN island 5 for the second time at a flow rate of 18sccm, a pressure of 14mTorr and a power of 120W, etching the barrier layer 3 and the transition layer 2 by using the masks in sequence to complete the manufacture of each left isolation groove 6 and each right isolation groove 7, wherein the lower ends of each left isolation groove 6 and each right isolation groove 7 are positioned in the transition layer 2, and the distance c between the interfaces of the barrier layer 3 and the transition layer 2>40nm；
And E, manufacturing a passivation layer 8.
Setting N2O flow rate of 840sccm, SiH4RF power at a flow rate of 300sccm and a temperature of 250 ℃Under the process conditions of 10W and 2000mT pressure, a passivation layer 8 with the thickness of 200nm is deposited on the barrier layer 3, the left P-GaN island 4, the right P-GaN island 5, the left isolation groove 6 and the right isolation groove 7 by adopting a plasma enhanced chemical vapor deposition technology;
and F, manufacturing a left source electrode 9 and a right source electrode 10 on the barrier layer 3.
F1) Setting the technological conditions adopted by etching: cl2Making a mask on the passivation layer 8 for the third time at a flow rate of 15sccm, a pressure of 10mTorr and a power of 100W, etching the passivation layer 11 on the left side and the right side by using the mask until the upper surface of the barrier layer 3 is etched to form three source electrode half grooves on the left side and three source electrode half grooves on the right side;
F2) the vacuum degree was set to 1.7X 10-3Pa, power 400W, evaporation rate
Figure BDA0003377762200000121
The process conditions of (1) depositing a plurality of layers of metal in the source electrode half grooves at the left side and the right side, wherein the deposited metal adopts Ta/Pt/Au metal combination, namely Ta, Pt and Au are respectively arranged from bottom to top, the thicknesses of the metals are respectively 0.012 mu m/0.051 mu m/0.037 mu m, and the three left source electrodes 9 and the three right source electrodes 10 are formed by performing rapid thermal annealing for 30s at the temperature of 870 ℃.
And G, manufacturing a left anode 11 and a right anode 12 on the upper part and the inner part of the barrier layer 3.
G1) Set up using Cl2Etching process conditions of 16sccm flow, 12mTorr pressure and 120W power, wherein a mask is manufactured on the barrier layer 3, the passivation layer 8, the left source electrode 9 and the right source electrode 10 for the fourth time, the passivation layer 10 on the left side and the right side is etched by using the mask until the upper surface of the barrier layer 3, three anode half grooves on the left side and three anode half grooves on the right side are formed, and the anode half grooves and the source electrode half grooves in F1) are alternately arranged;
G2) setting the technological conditions adopted by etching: cl2A mask is made on the barrier layer 3, the passivation layer 8, the left source electrode 9, the right source electrode 10, the left three anode half-tanks and the right three anode half-tanks at a flow rate of 20sccm, a pressure of 25mTorr and a power of 125W for the fifth time, and the left and right anodes are masked by the maskEtching the polar half groove again, wherein the etching depth is 70nm, and three anode grooves on the left side and three anode grooves on the right side are formed;
G3) the mask was reused under a vacuum of 1.7X 10-3Pa, power 380W, evaporation rate
Figure BDA0003377762200000122
Under the process conditions of (1), the deposited metal in the six anode grooves is Mo, the thickness of the Mo is 0.13 mu m, Schottky contact is formed between the deposited metal and the barrier layer 3, and the manufacture of three left anodes 11 and three right anodes 12 is completed.
And H, manufacturing a left electrode 13 and a right electrode 14.
The technological conditions adopted for depositing the metal are as follows: vacuum degree of 1.6X 10-3Pa, power of 200W, evaporation rate of
Figure BDA0003377762200000123
Making masks on the barrier layer 3, the passivation layer 8, the left source electrode 9, the right source electrode 10, the left anode 11 and the right anode 12 for the sixth time, and depositing metal by using the masks to cover the barrier layer 3, the left source electrode 9, the right source electrode 10, the left anode 11 and the right anode 12 to form a left electrode 13 and a right electrode 14, wherein the left electrode 13 electrically connects the three left source electrodes 9 with the three left anode 11, and the right electrode 14 electrically connects the three right source electrodes 10 with the three right anode 12; wherein the deposited metal is Ni/Au combination, namely the lower layer is Ni, the upper layer is Au, and the thicknesses of the Ni/Au combination and the Au combination are respectively 0.06 mu m/0.24 mu m;
step i, manufacturing the left gate 15 and the right gate 16.
I1) Setting up Cl2Etching process conditions of 18sccm flow, 14mTorr pressure and 120W power, wherein a mask is manufactured on the barrier layer 3, the passivation layer 8, the left source electrode 9, the right source electrode 10, the left anode 11, the right anode 12, the left electrode 13 and the right electrode 14 for the seventh time, the three left P-GaN islands 4 and the passivation layer 8 on the upper portions of the three right P-GaN islands 5 are etched by using the mask until the upper surfaces of the three P-GaN islands are etched to form gate grooves;
I2) the mask was reused under a vacuum of 1.5X 10-3Pa, power of300W, evaporation rate of
Figure BDA0003377762200000131
Under the process conditions of (1), depositing a metal combination Pt/Au in the gate groove, namely depositing Pt on the lower layer and Au on the upper layer, and respectively forming three left gates 15 and three right gates 16 to finish the manufacture of the whole device.
The effects of the present invention can be further illustrated by the following experimental results.
The experimental contents are as follows: the ac voltage signal chopping test was performed on the device of the second embodiment of the present invention, and the result is shown in fig. 7.
As can be seen from fig. 7, the device of the present invention can effectively realize chopping of an ac voltage signal, and it is proved that the device of the present invention has excellent bidirectional conduction and bidirectional blocking characteristics.
The foregoing description is only three specific embodiments of the present invention and is not intended to limit the present invention, and it will be apparent to those skilled in the art that various modifications and variations in form and detail can be made in the method according to the present invention without departing from the principle and scope of the invention, but these modifications and variations are within the scope of the invention as defined in the appended claims.

Claims (9)

1. An enhanced GaN-based composite switch device comprising, from bottom to top: the device comprises a substrate (1), a transition layer (2), a barrier layer (3) and a passivation layer (8); the method is characterized in that:
the left side and the right side of the upper part of the barrier layer (3) are respectively provided with m left P-GaN islands (4) which are arranged in parallel at equal intervals and m right P-GaN islands (5) which are arranged in parallel at equal intervals, the front side and the rear side of each left P-GaN island (4) are respectively provided with a left isolation groove (6), the front side and the rear side of each right P-GaN island (5) are respectively provided with a right isolation groove (7), and the left P-GaN islands (4) and the right P-GaN islands (5) are distributed in a cross way;
the left sides of the m left P-GaN islands (4) are respectively provided with a left source electrode (9), the left sides of the m right P-GaN islands (5) are respectively provided with a left anode (11), the left sides of the left source electrodes (9) and the left anodes (11) are respectively provided with a left electrode (13) in parallel, and the source electrodes and the anodes are partially covered by the left electrodes and are electrically connected;
the right sides of the m left P-GaN islands (4) are respectively provided with a right anode (12), the right sides of the m right P-GaN islands (5) are respectively provided with a right source electrode (10), the right side of each right source electrode (10) and the right side of each right anode (12) are respectively provided with a right electrode (14) in parallel, and the source electrodes and the anodes are partially covered by the right electrodes and are electrically connected;
the upper parts of the m left P-GaN islands (4) are provided with left grids (15), the upper parts of the m right P-GaN islands (5) are provided with right grids (16), the two sides of the left and right grids and the m left and right P-GaN islands are covered by passivation layers (8), the left P-GaN islands (4) at the lower parts of the left grids (15) are connected with the corresponding right anodes (12), and the right P-GaN islands (5) at the lower parts of the right grids (16) are connected with the corresponding left anodes (11) through barrier layers (3), so that a composite structure of a diode and a triode is formed.
2. Device according to claim 1, characterized in that the substrate (1) is made of sapphire or silicon carbide or silicon or graphene or other materials.
3. The device according to claim 1, characterized in that the barrier layer (3) has a thickness a of 2-60 nm.
4. The device of claim 1, wherein:
the m left P-GaN islands (4) are the same in size, the thicknesses of the left P-GaN islands are all b, the right edges of the left P-GaN islands are aligned, and the distance between every two adjacent left P-GaN islands (4) is w;
the m right P-GaN islands (5) are the same in size, the thicknesses of the m right P-GaN islands are all b, the left edges of the m right P-GaN islands are aligned, and the distance between every two adjacent right P-GaN islands (5) is w; the horizontal distance t between the m right P-GaN islands (5) and the m left P-GaN islands (4) is more than or equal to 1 μm.
5. The device of claim 1, wherein:
the left isolation grooves (6) are the same in size, the lower ends of the left isolation grooves are located in the transition layer (2), and the distance c between the lower ends of the left isolation grooves (6) and the interface of the barrier layer (3) and the transition layer (2) is larger than 40 nm; the right edge of each left isolation groove (6) is aligned with the right edges of the m left P-GaN islands (4), and the left edge of each left isolation groove (6) is positioned on the left side of the right edge of the left anode (11);
the right isolation grooves (7) are the same in size, the lower ends of the right isolation grooves are located in the transition layer (2), and the distance c between the lower ends of the right isolation grooves (7) and the interface of the barrier layer (3) and the transition layer (2) is larger than 40 nm; the left edge of each right isolation groove (7) is aligned with the left edges of the m right P-GaN islands (5), and the right edge of each right isolation groove (7) is positioned on the right side of the left edge of the right anode (12).
6. The device of claim 1, wherein:
the m left source electrodes (9) and the m right source electrodes (10) are positioned at the upper part of the barrier layer (3), and the lower ends of the m left anodes (11) and the m right anodes (12) are positioned in the barrier layer (3) or in the transition layer (2);
the m left source electrodes (9) and the m left anodes (11) are alternately arranged, and the right edges of the source electrodes and the right edges of the anodes are positioned in the same vertical plane;
the m right source electrodes (10) and the m right anode electrodes (12) are arranged alternately, and the left edges of the source electrodes and the anode electrodes are all located in the same vertical plane.
7. The device of claim 1, wherein:
ohmic contact is formed between each left source electrode (9) and each right source electrode (10) and the barrier layer (3) respectively;
schottky contact is formed between each left anode (11) and each right anode (12) and the barrier layer (3).
8. A method for manufacturing an enhanced GaN-based composite switch device is characterized by comprising the following steps:
A) a GaN-based wide bandgap semiconductor material is epitaxially grown on a substrate (1) by using an epitaxial process to form a transition layer (2);
B) a GaN-based wide bandgap semiconductor material is epitaxially grown on the transition layer (2) by using an epitaxial process to form a barrier layer (3) with the thickness of a;
C) manufacturing a left P-GaN island (4) and a right P-GaN island (5) on the barrier layer (3):
C1) a P-type GaN semiconductor material is epitaxially formed on the barrier layer (3) by an epitaxial process to have a thickness of b and a doping concentration of 1 × 1016～1×1022cm-3The P-type GaN layer of (1);
C2) manufacturing a mask on the P-GaN layer for the first time, etching the P-GaN layer by using the mask until the upper surface of the barrier layer (3) is etched to form m left P-GaN islands (4) and m right P-GaN islands (5);
D) masks are manufactured on the barrier layer (3), the left P-GaN island (4) and the right P-GaN island (5) for the second time, the barrier layer (3) and the transition layer (2) are sequentially etched by using the masks to form a left isolation groove (6) and a right isolation groove (7), and the distance c between the lower end of each of the left isolation groove (6) and the right isolation groove (7) and the interface of the barrier layer (3) and the transition layer (2) is more than 40 nm;
E) depositing a passivation layer (8) on the barrier layer (3), the left P-GaN island (4), the right P-GaN island (5), the left isolation groove (6) and the right isolation groove (7);
F) manufacturing a left source electrode (9) and a right source electrode (10) on the barrier layer (3);
F1) manufacturing a mask on the passivation layer (8) for the third time, etching the passivation layer (8) on the left side and the right side by using the mask until the upper surface of the barrier layer (3) is etched to form m source electrode half grooves on the left side and m source electrode half grooves on the right side;
F2) depositing multiple layers of metal in the source electrode half-grooves by using a metal deposition process by using the mask made for the third time again, and depositing N2Carrying out rapid thermal annealing in the atmosphere to form m left source electrodes (9) and m right source electrodes (10);
G) a left anode (11) and a right anode (12) are manufactured on the upper part and the inner part of the barrier layer (3):
G1) manufacturing masks on the barrier layer (3), the passivation layer (8), the left source electrode (9) and the right source electrode (10) for the fourth time, etching the passivation layer (8) on the left side and the right side by using the masks until the upper surface of the barrier layer (3) to form m anode half grooves on the left side and m anode half grooves on the right side, wherein the anode half grooves and the source electrode half grooves in F1) are alternately arranged;
G2) making masks on the barrier layer (3), the passivation layer (8), the left source electrode (9), the right source electrode (10), the left m anode half grooves and the right m anode half grooves for the fifth time, etching the left and right anode half grooves again by using the masks, wherein the etching depth is greater than 0 mu m, and forming left m anode grooves and right m anode grooves;
G3) depositing a plurality of layers of metal in the anode grooves by using a metal deposition process by using the mask manufactured for the fifth time again to form Schottky contact, and finishing the manufacture of m left anodes (11) and m right anodes (12);
H) sixthly, masks are manufactured on the barrier layer (3), the passivation layer (8), the left source electrode (9), the right source electrode (10), the left anode (11) and the right anode (12), metal is deposited on the barrier layer (3), the left source electrode (9), the right source electrode (10), the left anode (11) and the right anode (12) through the masks by using a metal deposition process, a left electrode (13) and a right electrode (14) are formed, the left electrode (13) covers and electrically connects the left source electrodes (9) and the left anode (11) partially, and the right electrode (14) covers and electrically connects the right source electrodes (10) and the right anode (12) partially;
I) a mask is manufactured on the barrier layer (3), the passivation layer (8), the left source electrode (9), the right source electrode (10), the left anode (11), the right anode (12), the left electrode (13) and the right electrode (14) for the seventh time, the passivation layer (8) on the upper portions of the m left P-GaN islands (4) and the m right P-GaN islands (5) is etched by using the mask until the upper surfaces of the P-GaN islands are etched, and m left gate grooves and m right gate grooves are formed;
J) and depositing a plurality of layers of metal in the m left and right gate grooves by using the mask manufactured for the seventh time by using a metal deposition process to respectively form a left gate (15) and a right gate (16), thereby finishing the manufacture of the whole device.
9. The method of claim 8, wherein:
the epitaxial process comprises the following steps: metal organic chemical vapor deposition, hydride vapor phase epitaxy and molecular beam epitaxy;
the metal deposition process comprises the following steps: electron beam evaporation process and sputtering process.
CN202111439008.4A 2021-11-26 2021-11-26 Enhanced GaN-based composite switch device and manufacturing method thereof Pending CN114141872A (en)

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