CN115000183A - Hybrid array terminal power device and manufacturing method thereof - Google Patents
Hybrid array terminal power device and manufacturing method thereof Download PDFInfo
- Publication number
- CN115000183A CN115000183A CN202210583543.5A CN202210583543A CN115000183A CN 115000183 A CN115000183 A CN 115000183A CN 202210583543 A CN202210583543 A CN 202210583543A CN 115000183 A CN115000183 A CN 115000183A
- Authority
- CN
- China
- Prior art keywords
- block
- ohmic
- schottky
- anode
- type array
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 36
- 238000002161 passivation Methods 0.000 claims abstract description 70
- 230000004888 barrier function Effects 0.000 claims abstract description 63
- 229910052751 metal Inorganic materials 0.000 claims abstract description 38
- 239000002184 metal Substances 0.000 claims abstract description 38
- 230000007704 transition Effects 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 238000000034 method Methods 0.000 claims description 42
- 238000005530 etching Methods 0.000 claims description 33
- 230000008569 process Effects 0.000 claims description 24
- 238000000151 deposition Methods 0.000 claims description 19
- 238000005516 engineering process Methods 0.000 claims description 18
- 239000000463 material Substances 0.000 claims description 15
- 238000005566 electron beam evaporation Methods 0.000 claims description 7
- 230000008020 evaporation Effects 0.000 claims description 7
- 238000001704 evaporation Methods 0.000 claims description 7
- 238000005229 chemical vapour deposition Methods 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 238000004151 rapid thermal annealing Methods 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims description 4
- 238000001451 molecular beam epitaxy Methods 0.000 claims description 4
- 229910052594 sapphire Inorganic materials 0.000 claims description 4
- 239000010980 sapphire Substances 0.000 claims description 4
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 4
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 4
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 3
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 3
- 229910010413 TiO 2 Inorganic materials 0.000 claims description 3
- 229910021389 graphene Inorganic materials 0.000 claims description 3
- 238000000231 atomic layer deposition Methods 0.000 claims description 2
- 239000012212 insulator Substances 0.000 claims description 2
- 238000001465 metallisation Methods 0.000 claims description 2
- 238000005546 reactive sputtering Methods 0.000 claims description 2
- 229910002704 AlGaN Inorganic materials 0.000 description 13
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 8
- 238000001020 plasma etching Methods 0.000 description 8
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 4
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 4
- 229910021529 ammonia Inorganic materials 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 4
- 229910052733 gallium Inorganic materials 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 239000001257 hydrogen Substances 0.000 description 4
- 229910052739 hydrogen Inorganic materials 0.000 description 4
- 150000002739 metals Chemical class 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- 229910052719 titanium Inorganic materials 0.000 description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 239000000969 carrier Substances 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000001755 magnetron sputter deposition Methods 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 239000000376 reactant Substances 0.000 description 3
- 238000004088 simulation Methods 0.000 description 3
- 229910052786 argon Inorganic materials 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 239000012159 carrier gas Substances 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- GNFTZDOKVXKIBK-UHFFFAOYSA-N 3-(2-methoxyethoxy)benzohydrazide Chemical compound COCCOC1=CC=CC(C(=O)NN)=C1 GNFTZDOKVXKIBK-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 229910001882 dioxygen Inorganic materials 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 125000004435 hydrogen atom Chemical group [H]* 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000013077 target material Substances 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/66196—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices with an active layer made of a group 13/15 material
- H01L29/66204—Diodes
- H01L29/66212—Schottky diodes
Abstract
The invention discloses a hybrid array terminal power device and a manufacturing method thereof, which mainly solve the problems of high turn-on voltage, small output current and large reverse leakage of the conventional Schottky diode and comprise the following steps: the device comprises a substrate, a transition layer, a barrier layer and a passivation layer; a cathode slot is arranged on the left side of the passivation layer, and a cathode is arranged above the cathode slot; the right side of the passivation layer is provided with an ohmic block, and the bottom of the ohmic block is in contact with the upper surface of the barrier layer; the left side of the ohmic block is sequentially provided with M anode blocks, N Schottky terminals and K P-type array blocks from right to left, and the lower parts of the anode blocks and the Schottky terminals are positioned in the transition layer; the lower surface of the P-type array block is contacted with the upper surface of the barrier layer; the upper surfaces of the anode block, the schottky terminal, the P-type array block and the ohmic block are provided with interconnection metal for simultaneously applying voltages to the anode block, the schottky terminal, the P-type array block and the ohmic block. The invention has small starting voltage, large conduction current and small reverse leakage, and can be used as a basic device of a power electronic system.
Description
Technical Field
The invention belongs to the technical field of microelectronics, and particularly relates to a power device adopting a hybrid array terminal structure, which can be used for a power electronic system.
Technical Field
Because only most carriers participate in the conduction of the Schottky barrier diode, the reverse recovery time is very short, and the Schottky barrier diode is very suitable for switching power supplies and high-frequency occasions. As the operating frequency of the circuit increases, the performance of the schottky barrier diode must also increase to maintain high power conversion efficiency. Due to the excellent material properties of GaN, such as high breakdown field strength, good thermal properties, and high electron mobility, GaN-based schottky barrier diodes have received much attention from researchers in high power and high frequency applications. In recent years, a great deal of constructive research work has been carried out at home and abroad on high-performance GaN schottky barrier diodes, and particularly, the lateral AlGaN/GaN schottky barrier diode is widely researched due to the advantage that the lateral AlGaN/GaN schottky barrier diode is compatible with the plane process of the AlGaN/GaN high electron mobility transistor. The lateral AlGaN/GaN Schottky barrier diode is beneficial to realizing the monolithic integration of the Schottky barrier diode device and the high electron mobility transistor device, thereby reducing parasitic elements and increasing the flexibility of design.
The conventional AlGaN/GaN Schottky barrier diode has high turn-on voltage and small output current, and the efficiency and the output power of a power electronic circuit and a system are seriously limited. In order to improve the above-mentioned problems of the conventional lateral AlGaN/GaN Schottky Barrier diode, the references AlGaN/GaN Schottky Barrier Diodes With Selective Si Diffusion for Low on set Voltage and High Reverse Blocking, IEEE Electron devices Letters, vol.34, No.8, 2013, propose a lateral AlGaN/GaN Schottky Barrier diode With a recessed anode structure, as shown in fig. 1, which includes: the structure comprises a substrate 1, a transition layer 2, a barrier layer 3, a passivation layer 4, a cathode 5 and an anode 6; a passivation layer 4 is deposited above the barrier layer 3, a cathode 5 is deposited on the left side of the upper surface of the barrier layer 3, and a groove anode 6 is deposited on the right sides of the barrier layer 3 and the passivation layer 4, so that although the diode can reduce the large turn-on voltage of the traditional AlGaN/GaN Schottky barrier diode to a certain extent, the turn-on voltage of the structure is still large, and the groove anode 6 can cause the reduction of output current and the increase of reverse leakage current.
Disclosure of Invention
The present invention is directed to overcome the above-mentioned deficiencies in the prior art, and an object of the present invention is to provide a hybrid array terminal power device and a method for manufacturing the same, so as to increase the output current of the device while significantly reducing the turn-on voltage, reduce the reverse leakage of the device, and improve the device performance.
In order to achieve the purpose, the technical scheme of the invention is as follows:
1. a hybrid array termination power device comprising, from bottom to top: substrate 1, transition layer 2, barrier layer 3, passivation layer 4, the left side of passivation layer 4 above the barrier layer 3 is provided with cathode slot 5, is provided with negative pole 7, its characterized in that above the cathode slot 5:
the right side of the passivation layer 4 is provided with an ohmic block 8, and the bottom of the ohmic block is in contact with the upper surface of the barrier layer 3;
the left side of the ohmic block 8 is sequentially provided with M anode blocks 14, N Schottky terminals 13 and K P-type array blocks 10 from right to left, the lower parts of the anode blocks 14 and the Schottky terminals 13 are positioned in the transition layer 2, and the lower surfaces of the P-type array blocks 10 are in contact with the upper surface of the barrier layer 3;
the upper surfaces of the anode block 14, the schottky terminal 13, the P-type array block 10 and the ohmic block 8 are provided with interconnection metal 15 for simultaneously applying voltages to the anode block 14, the schottky terminal 13, the P-type array block 10 and the ohmic block 8.
Further, the substrate 1 is made of sapphire, silicon carbide, silicon or graphene; the passivation layer 4 is made of SiO 2 、SiN、Al 2 O 3 、Sc 2 O 3 、HfO 2 、TiO 2 Any one of them.
Further, the thickness a of the barrier layer 3 is 3nm to 100 nm; the thickness b of the passivation layer 4 is 5 nm-1000 nm; the anode block 14 and the schottky terminal 13 have the same height c, c > a + b.
Further, the minimum lateral distance d between the P-type array block 10 and the schottky terminal 13 is greater than 0; the minimum lateral spacing e between the schottky terminal 13 and the anode block 14 is greater than 0; the minimum lateral spacing f between the anode block 14 and the ohmic block 8 is greater than 0.
Further, the minimum longitudinal spacing g between the K P-type array blocks 10 is greater than 0; the minimum longitudinal spacing h between the N schottky terminals 13 is greater than 0.
Further, the M anode blocks 14 are distributed at equal intervals, the longitudinal interval i between the anode blocks is greater than 0, when the device is in a balanced state, depletion regions are generated between the anode blocks 14, and current paths are pinched off by the depletion regions; the N Schottky terminals 13 and the K P-type array blocks 10 are distributed in a staggered manner; k is more than or equal to 2, N is more than or equal to 1, and M is more than or equal to 2.
2. The invention discloses a method for manufacturing a hybrid array terminal power device, which comprises the following steps:
A) extending GaN semiconductor material on a substrate 1 to form a transition layer 2;
B) extending GaN-based wide bandgap semiconductor material on the transition layer 2to form a barrier layer 3;
C) depositing an insulator on the barrier layer 3 to form a passivation layer 4;
D) manufacturing a mask on the passivation layer 4 for the first time, simultaneously etching the left side and the right side of the passivation layer 4 by using the mask until the upper surface of the barrier layer 3 is etched to form a cathode slot 5 and an ohmic slot 6;
E) making masks on the passivation layer 4, the ohmic groove 6 and the cathode groove 5 for the second time, depositing metal above the cathode groove 5 and the ohmic groove 6 by using the masks, and performing rapid thermal annealing to form a cathode 7 and an ohmic block 8;
F) a mask is manufactured on the passivation layer 4, the cathode 7 and the ohmic block 8 for the third time, the mask is used for etching at the position, which is slightly to the right, in the middle of the passivation layer 4 until the upper surface of the barrier layer 3 is etched, and a P-type array block groove 9 is formed;
G) making masks on the passivation layer 4, the cathode 7, the ohmic block 8 and the P-type array block groove 9 for the fourth time, and depositing a P-type material above the P-type array block groove 9 by using the masks to form K P-type array blocks 10;
H) manufacturing a mask on the passivation layer 4, the cathode 7, the ohmic block 8 and the P-type array block 10 for the fifth time, etching the right side of the P-type array block 10 by using the mask until the etching is below the lower surface of the barrier layer 3, and forming N Schottky terminal grooves 11 and M anode grooves 12;
I) and manufacturing a mask on the passivation layer 4, the cathode 7, the P-type array block 10, the Schottky terminal groove 11 and the anode slot 12 for the sixth time, and depositing metal on the ohmic block 8, the Schottky terminal groove 11, the anode slot 12 and the P-type array block 10 by using the mask to form N Schottky terminals 13, M anode blocks 14 and interconnection metal 15 to complete the manufacture of the whole device.
Compared with the prior art, the device of the invention has the following advantages:
1. because the device adopts the structure of the P-type array block 10, when the device is in a reverse turn-off state, a depletion region generated by the P-type array block 10 can pinch off a channel, and the reverse leakage current of the device is reduced.
2. Because the device adopts the structure of the Schottky terminal 13 and the plurality of anode blocks 14, when the device is in a conducting state, current carriers can flow in from the edges of the Schottky terminal 13 and the plurality of anode blocks 14, the contact area between the anode of the Schottky barrier diode and current is increased, the efficiency of tunneling the Schottky barrier by the current carriers is improved, and therefore the starting voltage is obviously reduced and the conducting current is increased.
3. The ohmic block 8 is arranged on the right side of the passivation layer of the device and is connected with the Schottky anode through the interconnection metal 15, so that the turn-on voltage of the device can be greatly reduced; meanwhile, as the plurality of schottky terminals 13 and the anode block 14 are connected in parallel through the interconnection metal 15, the voltage drop of the anode terminal in the on state of the schottky diode device is reduced, and thus the turn-on voltage is reduced.
Drawings
FIG. 1 is a diagram of a prior art trench anode AlGaN/GaN Schottky barrier diode;
fig. 2 is a top view of a hybrid array termination power device of the present invention;
FIG. 3 is a cross-sectional view taken along line AA' of FIG. 2;
FIG. 4 is a cross-sectional view taken along line BB' of FIG. 2;
FIG. 5 is a sectional view taken along line CC' of FIG. 2;
FIG. 6 is a cross-sectional view taken along line DD' of FIG. 2;
FIG. 7 is a schematic flow chart of an implementation of the present invention for manufacturing a hybrid array terminal power device;
FIG. 8 is a graph of the output characteristics of a device of the present invention and a prior art recessed anode AlGaN/GaN SBD.
Detailed Description
Embodiments and effects of the present invention will be described in further detail below with reference to the accompanying drawings.
Referring to fig. 2, 3, 4, 5, and 6, the hybrid array termination power device of the present example includes: the device comprises a substrate 1, a transition layer 2, a barrier layer 3, a passivation layer 4, a cathode slot 5, an ohmic slot 6, a cathode 7, an ohmic block 8, a P-type array block groove 9, a P-type array block 10, a Schottky groove 11, an anode slot 12, a Schottky terminal 13, an anode block 14 and interconnection metal 15. Wherein:
the substrate 1 is made of sapphire, silicon carbide, silicon or graphene materials;
the transition layer 2 is positioned on the upper part of the substrate 1, the thickness of the transition layer is 3-100 mu m, and the doping concentration is 1 multiplied by 10 15 ～1×10 18 cm -3 ；
The barrier layer 3 is positioned on the upper part of the transition layer 2 and is composed of a plurality of layers of same or different GaN-based wide bandgap semiconductor materials, and the thickness a is 3 nm-100 nm;
the passivation layer 4 is arranged on the barrier layer 3 and is made of SiO 2 、SiN、Al 2 O 3 、Sc 2 O 3 、HfO 2 、TiO 2 Any one of them, the thickness b is 5 nm-1000 nm;
the cathode slot 5 is positioned on the left side of the passivation layer 4, the ohmic slot 6 is positioned on the right side of the passivation layer 4, and the lower surfaces of the cathode slot 5 and the ohmic slot 6 are both in contact with the barrier layer 3;
the cathode 7 is positioned on the upper part of the cathode slot 5, the ohmic block 8 is positioned on the upper part of the ohmic slot 6, and the cathode 7 and the ohmic block 8 form good ohmic contact with a semiconductor below;
the P-type array block groove 9, the Schottky groove 11 and the anode slot 12 are sequentially distributed on the left side of the ohmic block 8 from left to right;
the K P-type array blocks 10 are positioned at the upper parts of the P-type array block grooves 9, the lower surfaces of the P-type array blocks 10 are in contact with the upper surface of the barrier layer 3, and the minimum longitudinal distance g between the K P-type array blocks 10 is larger than 0;
the N Schottky terminals 13 are positioned at the upper part of the Schottky groove 11, the M anode blocks 14 are positioned at the upper part of the anode slot 12, the heights c of the Schottky terminals 13 and the anode blocks 14 are the same, and c is greater than a + b; the minimum transverse distance d between the P-type array block 10 and the Schottky terminal 13 is greater than 0, and the minimum transverse distance e between the Schottky terminal 13 and the anode block 14 is greater than 0; the minimum lateral spacing f between the anode block 14 and the ohmic block 8 is greater than 0; the M anode blocks 14 are distributed at equal intervals, the longitudinal interval i between the anode blocks is larger than 0, when the device is in a balanced state, depletion regions are generated between the anode blocks 14, and a current path is pinched off by the depletion regions.
The interconnection metal 15 is located on the upper surfaces of the P-type array block 10, the schottky terminal 13, the anode block 14 and the ohmic block 8, so that the P-type array block 10, the schottky terminal 13, the anode block 14 and the ohmic block 8 are connected in parallel.
Referring to fig. 7, the method for manufacturing a hybrid array termination power device of the present invention provides the following three embodiments.
The first embodiment is as follows: a hybrid array termination power device was made with two P-type blocks 10, one schottky termination 13, and a minimum longitudinal spacing i between anode blocks 14 of 0.1 μm.
Using metal organic chemical vapor deposition technology, setting the temperature at 950 ℃, the pressure at 40Torr and using SiH 4 Is a doping source, the hydrogen flow is 4000sccm, the ammonia flow is 4000sccm, and the gallium source flow is 100 mu mol/minOn a sapphire substrate 1, the epitaxial thickness is 1 μm and the doping concentration is 1 × 10 15 cm -3 The n-type GaN buffer layer 2.
Using molecular beam epitaxy technique, setting vacuum degree to be less than or equal to 1.0 × 10 -10 mbar, radio frequency power of 400W, and N as reactant 2 High purity Ga source, high purity Al source, epitaxial growth of Al with thickness a of 3nm on GaN transition layer 2 0.5 Ga 0.5 N material forming the barrier layer 3.
Setting N using plasma enhanced chemical vapor deposition technique 2 O flow rate of 850sccm, SiH 4 Depositing SiO on the barrier layer 3 under the process conditions of the flow of 200sccm, the temperature of 250 ℃, the RF power of 25W and the pressure of 1100mTorr 2 To produce a passivation layer 4 having a thickness of 5 nm.
And 4, manufacturing a cathode groove 5 and an ohmic groove 6, as shown in fig. 7 d.
Making a mask on the upper part of the passivation layer 4 for the first time, setting Cl by using a reactive ion etching technology 2 Etching the left side and the right side of the passivation layer 4 by using the mask under the process conditions of 15sccm, 10mTorr of pressure and 100W of power until the upper surface of the barrier layer 3 to form the cathode slot 5 and the ohmic slot 6.
And 5, manufacturing a cathode 7 and an ohmic block 8, as shown in fig. 7 e.
Firstly, a mask is manufactured for the second time on the passivation layer 4, the cathode groove 5 and the ohmic groove 6 which are formed by etching, and the vacuum degree is set to be 1.8 multiplied by 10 -3 Pa, power 350W, evaporation rate
Depositing metals on the upper parts of a cathode groove 5 and an ohmic groove 6 which are formed by etching by utilizing an electron beam evaporation technology, wherein the deposited metals are Ti/Au/Ni metal combinations, namely Ti, Au and Ni from bottom to top, and the thicknesses of the metals are 0.02 mu m, 0.3 mu m and 0.05 mu m in sequence;
and then, setting the process conditions of 850 ℃ and 35s, and carrying out rapid thermal annealing on the deposited metal to finish the manufacture of the cathode 7 and the ohmic block 8.
And 6, manufacturing the P-type array block groove 9 as shown in fig. 7 f.
Making a mask on the cathode 7, the ohmic block 8 and the passivation layer 4 for the third time, and setting Cl 2 The flow is 15sccm, the pressure is 10mT, the power is 100W, the reactive ion etching technology is used, the position on the right side of the middle of the passivation layer 4 is etched by the mask, the etching depth is 5nm, and two P-type array block grooves 9 are formed through etching.
And 7, manufacturing a P-type array block 10, as shown in FIG. 7 g.
Making a mask on the cathode 7, the ohmic block 8, the passivation layer 4 and the upper part of the etched P-type array block groove 9 for the fourth time, and using a magnetron sputtering technology to epitaxially dope the P-type array block groove 9 with a doping concentration of 5 × 10 under the process conditions of a sputtering power of 110W, a temperature of 300 ℃, an Ar flow of 20sccm and an O2 flow of 30sccm 15 cm -3 NiO material with the thickness of 5nm forms two P-type array blocks 10, wherein the minimum longitudinal distance g between the P-type array blocks 10 is 4 mu m.
And 8, manufacturing a Schottky terminal groove 11 and an anode groove 12, as shown in figure 7 h.
Making a mask on the upper parts of the cathode 7, the ohmic block 8, the passivation layer 4 and the P-type array block 10 for the fifth time, and setting Cl 2 The process conditions of 15sccm flow, 10mT pressure and 150W power are adopted, the mask is utilized to etch the position on the right side of the P-type array block 10, the etching depth is 17nm, a plurality of anode grooves 12 and a Schottky terminal groove 11 are formed by etching, and the minimum longitudinal distance i between the anode grooves 12 is 0.1 mu m.
Making masks on the cathode 7, the ohmic block 8, the passivation layer 4, the P-type array block 10, the anode slot 12 formed by etching and the upper part of the Schottky terminal groove 11 for the sixth time, and setting the vacuum degree to be less than or equal to 1.6 multiplied by 10 -3 Pa, power set at 350W, evaporation rateIs composed of
Using the mask, depositing metal on the upper parts of the P-type array block 10, the ohmic block 8, the anode slot 12 and the schottky terminal groove 11 by using an electron beam evaporation technology, wherein the deposited metal is Ni, the thickness is 0.207 μm, making schottky contact, and forming 1 schottky terminal 13, a plurality of anode blocks 14 and interconnection metal 15, wherein the minimum longitudinal distance i between the anode blocks 14 is 0.1 μm, the transverse distance d between the schottky terminal 13 and the P-type array block 10 is 4 μm, the transverse distance e between the schottky terminal 13 and the anode block 14 is 5 μm, and the transverse distance f between the anode block 14 and the ohmic block 8 is 2 μm, thus completing the manufacture of the whole device.
Example two: a hybrid array termination power device was made with three P-type blocks 10, two schottky terminations 13, and a minimum longitudinal spacing i between anode blocks 14 of 0.5 μm.
Step one, a transition layer 2 is manufactured, as shown in fig. 7 a.
A metal organic chemical vapor deposition technology is used for forming a transition layer 2 by extending GaN material with the thickness of 4.9 mu m on a silicon carbide substrate 1 under the process conditions that the temperature is 1000 ℃, the pressure is 45Torr, the hydrogen flow is 4600sccm, the ammonia flow is 4600sccm, and the gallium source flow is 120 mu mol/min.
Step two, epitaxial Al 0.1 Ga 0.9 N, the barrier layer 3 is produced, as shown in fig. 7 b.
Using molecular beam epitaxy technique under vacuum degree of 1.0 × 10 -11 mbar, radio frequency power of 420W, and N as reactant 2 Al with the thickness of 50nm is epitaxially grown on the GaN transition layer 2 under the process conditions of high-purity Ga source and high-purity Al source 0.1 Ga 0.9 N material forming the barrier layer 3.
Step three, depositing Al 2 O 3 And a passivation layer 4 is fabricated, as shown in fig. 7 c.
Using atomic layer deposition techniques at TMA and H 2 O is a reaction source, and the carrier gas is N 2 Depositing Al above the barrier layer 3 under the process conditions of carrier gas flow of 200sccm, substrate temperature of 300 ℃ and air pressure of 700Pa 2 O 3 To produce a passivation layer 4 having a thickness of 500 nm.
Step four, manufacturing the cathode slot 5 and the ohmic slot 6, as shown in fig. 7 d.
First making a mask on the passivation layer 4, using Reactive Ion Etching (RIE) technique, in Cl 2 Etching the left side and the right side of the passivation layer 4 by using the mask under the process conditions of the flow of 15sccm, the pressure of 10mTorr and the power of 110W until the upper surface of the barrier layer 3 is etched to form the cathode slot 5 and the ohmic slot 6.
Step five, manufacturing the cathode 7 and the ohmic block 8, as shown in fig. 7 e.
Firstly, a mask is manufactured on the passivation layer 4 and the upper parts of the cathode groove 5 and the ohmic groove 6 formed by etching for the second time, metal is deposited on the upper parts of the cathode groove 5 and the ohmic groove 6 formed by etching by utilizing an electron beam evaporation technology, and the vacuum degree is less than 1.8 multiplied by 10 -3 Pa, power 400W, evaporation rate
Under the process conditions of (1), depositing Ti/Al/Ni/Au metal combinations, namely Ti, Al, Ni and Au from bottom to top, wherein the thicknesses of the Ti, Al, Ni and Au are 0.02 mu m, 0.14 mu m, 0.055 mu m and 0.045 mu m in sequence;
then, rapid thermal annealing was performed at 860 ℃ for 30 seconds to complete the fabrication of the cathode 7 and the ohmic block 8.
And sixthly, manufacturing the P-type array block groove 9 as shown in fig. 7 f.
A third mask is formed on the cathode 7, the ohmic block 8 and the passivation layer 4, and a reactive ion etching technique is used to etch the surface of the substrate in Cl 2 And under the process conditions of 15sccm flow, 10mTorr pressure and 110W power, etching the right position of the middle part of the passivation layer 4 by using the mask to the depth of 500nm to form three P-type array block grooves 9.
Step seven, manufacturing the P-type array block 10, as shown in FIG. 7 g.
Making a mask on the cathode 7, the ohmic block 8, the passivation layer 4 and the upper part of the etched P-type array block groove 9 for the fourth time, and then making a high-purity Mg source at 950 ℃, 42Torr and 4100sccm in hydrogen flowUnder the process conditions of ammonia flow of 4100sccm and gallium source flow of 100 mu mol/min as dopant, the epitaxial thickness of 500nm and the doping concentration of 1 × 10 are formed on the groove 9 of the P-type array block by using the metal organic chemical vapor deposition technology 22 cm -3 Three P-type array blocks 10 are formed, wherein the minimum longitudinal spacing g between the P-type array blocks 10 is 2 μm.
And step eight, manufacturing the Schottky terminal groove 11 and the anode groove 12, as shown in figure 7 h.
Making a mask on the cathode 7, the ohmic block 8, the passivation layer 4 and the P-type array block 10 for the fifth time, and adding Cl 2 And etching the position on the right side of the P-type array block 10 by using the mask under the process conditions of 15sccm flow, 10mT pressure and 180W power, wherein the etching depth is 700nm, a plurality of anode grooves 12 and two Schottky terminal grooves 11 are formed, and the minimum longitudinal distance i between the anode grooves 12 is 1 mu m.
Step nine, the schottky terminal 13, anode block 14 and interconnect metal 15 are fabricated as shown in fig. 7 i.
Making masks on the cathode 7, the ohmic block 8, the passivation layer 4, the P-type array block 10, the anode slot 12 formed by etching and the upper part of the Schottky terminal groove 11 for the sixth time, and making masks under the vacuum degree of 1.6 multiplied by 10 -3 Pa, power of 350W, evaporation rate of
Under the process conditions, using an electron beam evaporation technology to deposit metal Wu on the upper parts of the P-type array block 10, the ohmic block 8, the anode slot 12 and the Schottky terminal groove 11 by using the mask to make Schottky contact, and forming two Schottky terminals 13, a plurality of anode blocks 14 and interconnection metal 15, wherein the minimum longitudinal distance i between the anode blocks 14 is 0.5 μm, the transverse distance d between the Schottky terminal 13 and the P-type array block 10 is 2 μm, the transverse distance e between the Schottky terminal 13 and the anode block 14 is 3 μm, the transverse distance f between the anode block 14 and the ohmic block 8 is 1 μm, and the longitudinal distance h between the Schottky terminal 13 is 3 μm, thereby completing the manufacture of the whole device.
Example three: a hybrid array termination power device was fabricated with four P-type blocks 10, three schottky terminations 13, and a minimum vertical spacing i of 1 μm between anode blocks 14.
Step a. make the transition layer 2, as in fig. 7 a.
On a silicon substrate 1, a Metal Organic Chemical Vapor Deposition (MOCVD) technique is used to epitaxially grow a silicon substrate with a thickness of 3 μm and a doping concentration of 1 × 10 18 cm -3 N of (A) to (B) - And a type GaN transition layer 2. The process conditions are as follows: the temperature was 950 ℃ and the pressure was 40Torr, as SiH 4 The doping source is hydrogen flow of 4000sccm, ammonia flow of 4000sccm, and gallium source flow of 100 μmol/min.
Step B, epitaxial Al 0.01 Ga 0.99 N, barrier layer 3 is fabricated, as shown in fig. 7 b.
Epitaxial growth of 100nm thick Al on the GaN transition layer 2 using molecular beam epitaxy 0.01 Ga 0.99 N material forming the barrier layer 3. The process conditions are as follows: vacuum degree of 1.0 × 10 or less -10 mbar, radio frequency power of 400W, and N as reactant 2 A high purity Ga source and a high purity Al source.
Step C, depositing HfO 2 And the passivation layer 4 is fabricated as shown in fig. 7 c.
Deposition of HfO over barrier layer 3 using RF magnetron reactive sputtering technique 2 A passivation layer 4 having a thickness of 1000 nm. The deposition process conditions are as follows: the sputtering pressure of the reaction chamber is kept at 0.1Pa, O 2 And Ar flow rates are respectively 1sccm and 8sccm, the substrate temperature is fixed at 200 ℃, and the Hf target radio frequency power is 150W.
Step d. make cathode trench 5 and ohmic trench 6 as shown in fig. 7 d.
And (3) manufacturing a mask on the upper part of the passivation layer 4 for the first time, etching the left side and the right side of the passivation layer 4 by using a reactive ion etching technology until the upper surface of the barrier layer 3 is etched to form a cathode slot 5 and an ohmic slot 6. The etching process conditions are as follows: cl 2 The flow rate is 15sccm, the pressure is 10mTorr, and the power is 100W.
Step e. make cathode 7 and ohmic block 8, as in fig. 7 e.
E1) And (3) making a mask on the passivation layer 4 and the upper parts of the cathode groove 5 and the ohmic groove 6 formed by etching for the second time, and depositing metal on the upper parts of the cathode groove 5 and the ohmic groove 6 formed by etching by using an electron beam evaporation technology.
The deposition process conditions are as follows: vacuum degree less than 1.8X 10 -3 Pa, power 500W, evaporation rate
The deposited metal is a Ti/Al/Mo/Au metal combination, namely Ti, Al, Mo and Au are respectively arranged from bottom to top, and the thicknesses of the metals are 0.02 mu m, 0.1 mu m, 0.03 mu m and 0.03 mu m in sequence;
E2) and (3) carrying out rapid thermal annealing on the sample after the metal deposition by adopting the process conditions of 860 ℃ and 30s to finish the manufacture of the cathode 7 and the ohmic block 8.
And F, manufacturing the P-type array block groove 9 as shown in figure 7 f.
And (3) making masks on the cathode 7, the ohmic block 8 and the upper part of the passivation layer 4 for the third time, and etching the right part of the middle part of the passivation layer 4 by using a reactive ion etching technology to form four P-type array block grooves 9 with the depth of 1000 nm. The etching process conditions are as follows: CF (compact flash) 4 The flow rate was 45sccm, O 2 The flow rate is 5sccm, the pressure is 15mTorr, and the power is 300W.
Step g, P-type array block 10 is fabricated as shown in fig. 7 g.
Making a mask on the cathode 7, the ohmic block 8, the passivation layer 4 and the upper part of the etched P-type array block groove 9 for the fourth time, and performing magnetron sputtering on the P-type array block groove 9 with the epitaxial thickness of 1000nm and the doping concentration of 3 multiplied by 10 20 cm -3 Forming four P-type array blocks 10, wherein the minimum longitudinal pitch g between the P-type array blocks 10 is 0.5 μm.
The technological conditions of magnetron sputtering are as follows: copper with the purity of 99.999 percent is selected as a target material, sputtering gas is high-purity argon, high-purity oxygen with the same purity is selected as reaction gas, and the vacuum degree of a reaction chamber before sputtering is set to be 2.0 multiplied by 10 -4 Pa, the flow rate of argon gas is kept at 20sccm, the flow rate of oxygen gas is kept at 10sccm, the pressure of the deposition chamber is 0.5Pa, the radio frequency power is 35W, and the temperature of the substrate is 200 ℃.
Step h. make schottky termination recess 11 and anode trench 12 as in fig. 7 h.
And making masks on the cathode 7, the ohmic block 8, the passivation layer 4 and the upper part of the P-type array block 10 for the fifth time, and etching to form a plurality of anode grooves 12 and three Schottky terminal grooves 11 at the positions on the right side of the P-type array block 10 by using a reactive ion etching technology, wherein the minimum longitudinal distance i between the anode grooves 12 is 1 mu m, and the etching depth is 1.5 mu m.
The etching process conditions are as follows: cl 2 The flow rate is 15sccm, the pressure is 10mT, and the power is 180W.
Step i. make schottky terminal 13, anode block 14 and interconnect metal 15 as in fig. 7 i.
Making masks on the cathode 7, the ohmic block 8, the passivation layer 4, the P-type array block 10, the anode slot 12 formed by etching and the upper part of the Schottky terminal groove 11 for the sixth time, adopting an electron beam evaporation technology, and setting the vacuum degree to be 1.6 multiplied by 10 -3 Pa, power 350W, evaporation rate
Using the mask to deposit Mo metal on the upper portions of the P-type array block 10, the ohmic block 8, the anode trench 12 and the schottky terminal groove 11 to form schottky contacts, and forming three schottky terminals 13, a plurality of anode blocks 14 and interconnection metal 15, wherein the minimum longitudinal distance i between the anode blocks 14 is 1 μm, the transverse distance d between the schottky terminal 13 and the P-type array block 10 is 1 μm, the transverse distance e between the schottky terminal 13 and the anode block 14 is 1 μm, the transverse distance f between the anode block 14 and the ohmic block 8 is 0.5 μm, and the longitudinal distance h between the schottky terminal 13 is 0.1 μm, thereby completing the manufacture of the whole device.
The effects of the present invention can be further illustrated by the following simulations.
Simulation: forward conduction output characteristic simulation was performed on the conventional trench anode AlGaN/GaN schottky barrier diode and the device according to the second embodiment of the present invention, and the results are shown in fig. 8.
As can be seen from fig. 8, the turn-on voltage of the device of the present invention is 0.26V, and the turn-on voltage of the conventional trench anode AlGaN/GaN schottky barrier diode is 1V. The turn-on voltage of the device of the invention is significantly lower than that of the prior art, and simultaneously, compared with the prior art, the output current of the device of the invention is significantly increased.
While the foregoing is directed to three specific embodiments of the present invention and is not intended to limit the invention, it will be apparent to those skilled in the art that various changes and modifications in form and detail may be made therein without departing from the spirit and scope of the invention, but that such changes and modifications are within the scope of the appended claims.
Claims (10)
1. A hybrid array termination power device comprising, from bottom to top: substrate (1), transition layer (2), barrier layer (3), passivation layer (4), the left side of passivation layer (4) above barrier layer (3) is equipped with negative pole groove (5), is equipped with negative pole (7) above the negative pole groove, its characterized in that:
an ohmic block (8) is arranged on the right side of the passivation layer (4), and the bottom of the ohmic block is in contact with the upper surface of the barrier layer (3);
the left side of the ohmic block (8) is sequentially provided with M anode blocks (14), N Schottky terminals (13) and K P-type array blocks (10) from right to left, the lower parts of the anode blocks (14) and the Schottky terminals (13) are positioned in the transition layer (2), and the lower surfaces of the P-type array blocks (10) are in contact with the upper surface of the barrier layer (3);
and the upper surfaces of the anode block (14), the Schottky terminal (13), the P-type array block (10) and the ohmic block (8) are provided with interconnection metal (15) which is used for applying voltage to the anode block (14), the Schottky terminal (13), the P-type array block (10) and the ohmic block (8) at the same time.
2. The device of claim 1, wherein:
the substrate (1) is made of sapphire or silicon carbide or silicon or graphene materials;
the passivation layer (4) adopts SiO 2 、SiN、Al 2 O 3 、Sc 2 O 3 、HfO 2 、TiO 2 Any one of them.
3. The device of claim 1, wherein:
the thickness a of the barrier layer (3) is 3 nm-100 nm;
the thickness b of the passivation layer (4) is 5 nm-1000 nm;
the anode block (14) and the Schottky terminal (13) have the same height c, and c is larger than a + b.
4. The device of claim 1, wherein:
the minimum transverse distance d between the P-type array block (10) and the Schottky terminal (13) is more than 0;
the minimum lateral spacing e between the Schottky terminal (13) and the anode block (14) is greater than 0;
the minimum lateral distance f between the anode block (14) and the ohmic block (8) is greater than 0.
5. The device of claim 1, wherein:
the minimum longitudinal spacing g between the K P-type array blocks (10) is greater than 0;
the minimum longitudinal spacing h between the N Schottky terminals (13) is greater than 0.
6. The device of claim 1, wherein:
the M anode blocks (14) are distributed at equal intervals, the longitudinal interval i between the anode blocks is larger than 0, when the device is in a balanced state, depletion regions are generated between the anode blocks (14), and a current path is pinched off by the depletion regions;
the N Schottky terminals (13) and the K P-type array blocks are distributed in a staggered manner;
K≥2，N≥1，M≥2。
7. a method for manufacturing a hybrid array terminal power device is characterized by comprising the following steps:
A) epitaxial growth of GaN semiconductor material on a substrate (1) to form a transition layer (2);
B) extending GaN-based wide bandgap semiconductor material on the transition layer (2) to form a barrier layer (3);
C) depositing an insulator on the barrier layer (3) to form a passivation layer (4);
D) manufacturing a mask on the passivation layer (4) for the first time, simultaneously etching the left side and the right side of the passivation layer (4) by using the mask until the upper surface of the barrier layer (3) is etched to form a cathode groove (5) and an ohmic groove (6);
E) manufacturing masks on the passivation layer (4), the ohmic groove (6) and the cathode groove (5) for the second time, depositing metal above the cathode groove (5) and the ohmic groove (6) by using the masks, and performing rapid thermal annealing to form a cathode (7) and an ohmic block (8);
F) a mask is manufactured on the passivation layer (4), the cathode (7) and the ohmic block (8) for the third time, the mask is used for etching at the position, which is slightly to the right, in the middle of the passivation layer (4) until the upper surface of the barrier layer (3) is etched, and a P-type array block groove (9) is formed;
G) making masks on the passivation layer (4), the cathode (7), the ohmic block (8) and the P-type array block groove (9) for the fourth time, and depositing a P-type material above the P-type array block groove (9) by using the masks to form K P-type array blocks (10);
H) making a mask on the passivation layer (4), the cathode (7), the ohmic block (8) and the P-type array block (10) for the fifth time, etching the right side of the P-type array block (10) by using the mask until the etching is below the lower surface of the barrier layer (3), and forming N Schottky terminal grooves (11) and M anode grooves (12);
I) and manufacturing a mask for the sixth time on the passivation layer (4), the cathode (7), the P-type array block (10), the Schottky terminal groove (11) and the anode slot (12), and depositing metal above the ohmic block (8), the Schottky terminal groove (11), the anode slot (12) and the P-type array block (10) by using the mask to form N Schottky terminals (13), M anode blocks (14) and interconnection metal (15) to complete the manufacture of the whole device.
8. The method of claim 7, wherein: the process for manufacturing the passivation layer (4) in the step C) comprises the following steps: chemical vapor deposition technology, atomic layer deposition technology and radio frequency magnetron reactive sputtering technology.
9. The method of claim 7, wherein: the epitaxial technique used in the steps A) and B) comprises the following steps: chemical vapor deposition method, molecular beam epitaxy method.
10. The method of claim 7, wherein: the metal deposition process used in the steps E) and I) is electron beam evaporation, and the process conditions are as follows: vacuum degree less than 1.8X 10 -3 Pa, power range of 200-1000W, evaporation rate less than
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210583543.5A CN115000183A (en) | 2022-05-25 | 2022-05-25 | Hybrid array terminal power device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210583543.5A CN115000183A (en) | 2022-05-25 | 2022-05-25 | Hybrid array terminal power device and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115000183A true CN115000183A (en) | 2022-09-02 |
Family
ID=83029876
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210583543.5A Pending CN115000183A (en) | 2022-05-25 | 2022-05-25 | Hybrid array terminal power device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115000183A (en) |
-
2022
- 2022-05-25 CN CN202210583543.5A patent/CN115000183A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN112768505B (en) | Heterojunction power device and manufacturing method thereof | |
| CN106024914A (en) | GaN-based schottky diode having hybrid anode electrode structure and preparation method thereof | |
| CN106876256B (en) | SiC double-groove UMOSFET device and preparation method thereof | |
| CN111863953B (en) | Power switch device and manufacturing method thereof | |
| CN111682064B (en) | High-performance MIS gate enhanced GaN-based high electron mobility transistor and preparation method thereof | |
| CN111863950A (en) | Junction gate-drain power device | |
| CN106876471B (en) | Dual trench UMOSFET device | |
| CN107170798B (en) | Vertical power device based on gate field plate and drain field plate and manufacturing method thereof | |
| CN114023808A (en) | AlGaN/GaN heterojunction multi-channel power diode with P-type terminal and manufacturing method | |
| CN115000183A (en) | Hybrid array terminal power device and manufacturing method thereof | |
| CN115020499A (en) | Junction Schottky diode based on p-type GaN structure and preparation method thereof | |
| CN112736130A (en) | Gallium nitride based high electron mobility transistor and manufacturing method thereof | |
| CN113903802A (en) | Array strip-based enhancement type switch transistor and manufacturing method thereof | |
| CN111863951A (en) | Enhanced composite gate transistor and manufacturing method thereof | |
| CN114121945B (en) | Composite modulation power switching device | |
| CN114937704A (en) | Distributed groove electrode power device and manufacturing method thereof | |
| CN115000167A (en) | Power switch device based on array Schottky leakage | |
| CN114883324A (en) | Staggered modulation type bidirectional blocking device and manufacturing method thereof | |
| CN114937698A (en) | Composite drain power transistor | |
| CN114975640A (en) | Staggered array Schottky type power device | |
| CN215896408U (en) | GaN enhanced high electron mobility transistor with MIS grid structure | |
| CN114944387A (en) | Common source type power device and manufacturing method thereof | |
| CN114141872A (en) | Enhanced GaN-based composite switch device and manufacturing method thereof | |
| CN114944389A (en) | Composite power switch device with embedded Schottky diode and manufacturing method thereof | |
| CN116207097A (en) | Composite graded gallium nitride power transistor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |