CN114944389A - Composite power switch device with embedded Schottky diode and manufacturing method thereof - Google Patents
Composite power switch device with embedded Schottky diode and manufacturing method thereof Download PDFInfo
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
- H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
- H01L27/0727—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with diodes, or capacitors or resistors
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/8252—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using III-V technology
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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Abstract
The invention discloses a composite power switch device embedded with a Schottky diode, which mainly solves the problem that the conventional power switch device can only be conducted in a single direction. It comprises the following steps: the device comprises a substrate, a transition layer, a first channel layer, a first barrier layer, a second channel layer and a second barrier layer; the upper part of the second barrier layer is sequentially provided with a P-type block and a grid; the left side and the right side of the first channel layer, the first barrier layer, the second channel layer and the second barrier layer are respectively provided with a first table board, the two first table boards are respectively provided with an anode and a drain, and the right side of the first table board on the left side is provided with a second table board and a source in sequence. The contact interface of the first channel layer and the first barrier layer forms an electronic channel, and the channel, the drain electrode and the anode form a Schottky diode structure; the second channel layer, the second barrier layer, the P-type block, the drain electrode, the source electrode and the grid electrode jointly form a power switch transistor. The invention can reduce loss, improve device integration level, realize bidirectional conduction characteristic, and be used as a switch device.
Description
Technical Field
The invention belongs to the technical field of microelectronics, and particularly relates to a composite power switch device which can be used as a basic device of a power electronic system.
Technical Field
The power electronic system is widely applied to the fields of aerospace, industrial equipment, electric automobiles, household appliances and the like, and the power switch device is an important element of the power electronic system and is an important tool for realizing energy conversion and control. Therefore, the performance and reliability of the power switch device have a decisive influence on various technical indexes and performances of the whole power electronic system. At present, the performance of Si-based power switching devices has approached their theoretical limit and cannot meet the requirements of next generation of power electronic systems for high temperature, high voltage, high frequency, high efficiency and high power density. The third generation wide bandgap semiconductor material represented by GaN has the characteristics of large bandgap width, high saturated electron drift velocity, large critical breakdown electric field and stable chemical properties, and has unique advantages in the aspect of preparing power switching devices with lower on resistance, higher switching speed and higher breakdown voltage. Particularly, the GaN-based high electron mobility power switch device based on the GaN-based heterojunction structure has wide and special application prospects in the fields of national economy and military due to the excellent power characteristics of the GaN-based high electron mobility power switch device.
The traditional gallium nitride-based enhanced power switch device is based on a GaN-based heterojunction structure and comprises: the device comprises a substrate, a transition layer, a channel layer, a barrier layer, a P-GaN gate, a drain electrode, a source electrode and gate metal; the left side of the upper part of the barrier layer is deposited with a drain electrode, the right side of the upper part of the barrier layer is deposited with a source electrode, the middle part of the upper part of the barrier layer is deposited with a P-GaN gate, and the upper part of the P-GaN gate is deposited with gate metal, as shown in figure 1. However, in the conventional GaN-based enhancement mode power switch device, the current in the device can only be conducted in one direction from the drain to the source in the on state, and the power can only be transmitted from the drain to the source, i.e., the conventional GaN-based enhancement mode power switch device can only achieve one-way conduction, see Gate and barrier layer design of E-mode GaN HEMT with p-GaN Gate structure, 201920 th International Conference on Electronic Packaging Technology (ICEPT),2019, 1-4. In many fields such as inverters, ac-ac frequency converters and the like, devices are often required to have bidirectional conduction capability, and when the bidirectional conduction is realized by using a traditional power switch device, PCB board level interconnection of a plurality of discrete devices is required, so that a monolithic integrated circuit cannot be realized, thereby resulting in significant parasitic effect, large power consumption and circuit volume. Therefore, there is an urgent need to develop a high-performance gan-based enhancement-mode power switch device with simple process and bidirectional conduction characteristics.
Disclosure of Invention
The invention aims to provide a composite power switch device embedded with a schottky diode and a manufacturing method thereof to realize the bidirectional conduction characteristic, reduce the parasitic effect, reduce the loss and improve the integration level of the composite power switch device aiming at the defects of the prior art.
In order to achieve the purpose, the technical scheme of the invention is realized as follows:
first, device structure
1. A composite power switch device with embedded Schottky diodes comprises from bottom to top: substrate 1, transition layer 2, second channel layer 5, second barrier layer 6, P type piece 7 and grid 13, characterized by:
a first channel layer 3 and a first barrier layer 4 are inserted between the transition layer 2 and the second channel layer 5, and the first barrier layer 4 is positioned on the first channel layer 3;
the left side and the right side of the first channel layer 3, the first barrier layer 4, the second channel layer 5 and the second barrier layer 6 are respectively provided with a first table top 8, the first table top on the left side is provided with an anode 12, the first table top on the right side is provided with a drain 10, and the lower ends of the two first table tops are respectively positioned at the upper part of the transition layer 2;
a second table top 9 is arranged on the right side of the first table top 8 on the left side, the lower end of the second table top is positioned in the second channel layer 5, and a source electrode 11 is arranged on the second table top;
the contact interface of the first channel layer 3 and the first barrier layer 4 forms an electronic channel, and the channel, the drain electrode 10 and the anode 12 together form a Schottky diode structure;
the second channel layer 5, the second barrier layer 6, the P-type block 7, the drain 10, the source 11 and the gate 13 together form a power switch transistor.
Further, the substrate 1 is made of sapphire, silicon carbide, silicon, graphene or other materials.
Further, the thickness S of the first barrier layer 4 1 2-60 nm, and the thickness S of the second barrier layer 6 2 2to 60 nm.
Furthermore, the thickness h of the P-type block 7 is 10-500 nm, and the doping concentration is 1 multiplied by 10 16 ～5×10 20 cm -3 When determining the thickness of the P-type block 7, it is ensured that it has little depletion effect on the first barrier layer 4.
Further, the drain electrode 10 and the source electrode 11 are combined by multiple layers of metal, and both form ohmic contact with a contacted semiconductor.
Second, the manufacturing method
The invention discloses a method for manufacturing a composite power switch device with an embedded Schottky diode, which is characterized by comprising the following steps of:
A) extending a GaN-based wide bandgap semiconductor material on a substrate 1 to form a transition layer 2 with the thickness of 1-50 mu m;
B) manufacturing a channel layer and a barrier layer:
B1) extending a GaN material on the transition layer 2to form a first channel layer 3 with the thickness of 10-200 nm;
B2) epitaxial growth of GaN-based wide bandgap semiconductor on first channel layer 3Material formed to a thickness S 1 A first barrier layer 4 of 2to 60 nm;
B3) extending a GaN material on the first barrier layer 4 to form a second channel layer 5 with the thickness of 10-200 nm;
B4) a GaN-based wide bandgap semiconductor material is epitaxially formed on the second channel layer 5to a thickness S 2 A second barrier layer 6 of 2to 60 nm;
C) a P-type block 7 is fabricated on the second barrier layer 6:
C1) extending a P-type semiconductor material on the second barrier layer 6 to form a P-type layer;
C2) manufacturing a mask on the P-type layer for the first time, and etching the P-type layer by using the mask to form a P-type block 7;
D) etching to form a table top:
D1) making masks on the second barrier layer 6 and the P-type block 7 for the second time, respectively etching the two sides of the second barrier layer 6, the second channel layer 5, the first barrier layer 4 and the first channel layer 3 by using the masks until the masks reach the upper surface of the transition layer 2, and forming a left first table top 8 and a right first table top 8;
D2) a mask is manufactured on the second barrier layer 6, the P-type block 7 and the first table top 8 for the third time, the second barrier layer 6 and the second channel layer 5 on the right side of the first table top 8 on the left side are sequentially etched by the mask, the etching depth is larger than the thickness of the second barrier layer 6 and smaller than the total thickness of the second channel layer 5 and the second barrier layer 6, and a second table top 9 on the left side is formed;
E) making a mask on the second barrier layer 6, the P-type block 7, the first mesa 8 and the second mesa 9 for the fourth time, and respectively depositing a plurality of layers of metal on the first mesa 8 and the second mesa 9 on the right side by using the mask to form a drain electrode 10 and a source electrode 11;
F) making a mask on the second barrier layer 6, the P-type block 7, the first table 8, the drain electrode 10 and the source electrode 11 for the fifth time, depositing a plurality of layers of metal on the first table 8 on the left side by utilizing the mask to form an anode 12, wherein Schottky contact is formed between the anode 12 and the contacted semiconductor material;
G) and (4) making a mask on the second barrier layer 6, the P-type block 7, the drain electrode 10, the source electrode 11 and the anode 12 for the sixth time, and depositing a plurality of layers of metal on the P-type block 7 by using the mask to form a grid electrode 13, thereby completing the manufacture of the whole device.
Compared with the traditional gallium nitride-based enhanced power switch device, the device has the following advantages:
firstly, the device of the invention is inserted with the first channel layer and the first barrier layer, the contact interface of the two forms an electronic channel, and the channel, the drain electrode and the anode form a Schottky diode structure, so that electrons have a rightward current path in the channel; meanwhile, the second channel layer, the second barrier layer, the P-type block, the drain electrode, the source electrode and the grid electrode form a power switch transistor, so that electrons are conducted in an electron channel at a contact interface of the second channel layer and the second barrier layer and have a leftward current path, and therefore the device can achieve bidirectional conduction characteristics.
Second, the device of the present invention employs vertical stacking of the power switch transistor and the embedded schottky diode, which can reduce parasitic parameters caused by interconnection and significantly improve the integration of the composite power switch device, compared with the conventional method in which discrete components are placed on the same PCB for interconnection.
Thirdly, the active region between the drain electrode and the source electrode of the power switch transistor in the device is overlapped with the active region between the anode electrode and the drain electrode of the embedded Schottky diode in the vertical direction, and the drain electrode is used as the cathode of the diode and also used as the drain electrode of the power switch transistor, so that the external connection is reduced, and the area of the device in the horizontal direction is greatly reduced.
Fourthly, the manufacturing process of the device is compatible with the manufacturing process of the traditional gallium nitride-based enhanced power switch device, so that the process complexity is not improved.
Simulation results show that the device has good bidirectional conduction characteristics.
Drawings
Fig. 1 is a block diagram of a conventional gallium nitride-based enhancement mode power switch device;
fig. 2 is a block diagram of a composite power switching device with embedded schottky diodes in accordance with the present invention;
FIG. 3 is a top view of FIG. 2;
fig. 4 is a schematic overall flow chart of the present invention for fabricating a schottky diode embedded composite power switching device;
fig. 5 shows the result of the turn-on characteristic test of the device of the present invention.
Detailed Description
Embodiments and effects of the present invention will be described in further detail below with reference to the accompanying drawings.
Referring to fig. 2 and 3, the composite power switching device with embedded schottky diode in the present example includes: substrate 1, transition layer 2, first channel layer 3, first barrier layer 4, second channel layer 5, second barrier layer 6, P type piece 7, first mesa 8, second mesa 9, drain-source resistance 10, source electrode 11, positive pole 12, grid 13, wherein:
the substrate 1 is made of sapphire, silicon carbide, silicon, graphene or other materials;
the transition layer 2 is positioned on the upper part of the substrate 1 and is composed of a plurality of layers of same or different GaN-based wide bandgap semiconductor materials, and the thickness of the transition layer is 1-50 mu m;
the first channel layer 3 is located on the upper portion of the transition layer 2, is made of a GaN material, and is 10-200 nm thick;
the first barrier layer 4 is located on the first channel layer 3, and is made of GaN-based wide bandgap semiconductor material with a thickness S 1 2-60 nm;
the second channel layer 5 is positioned on the first barrier layer 4, is made of GaN materials, and has a thickness of 10-200 nm;
the second barrier layer 6 is arranged on the second channel layer 5 and is made of GaN-based wide bandgap semiconductor material with a thickness S 2 2-60 nm;
the P-type block 7 is arranged in the middle of the upper part of the second barrier layer 6, is made of P-type semiconductor material, has a thickness h of 10-500 nm and a doping concentration of 1 multiplied by 10 16 ～5×10 20 cm -3 ；
The two first table boards 8 are respectively positioned at the left side and the right side of the first channel layer 3, the first barrier layer 4, the second channel layer 5 and the second barrier layer 6, and the lower ends of the two first table boards are positioned at the upper part of the transition layer 2;
the second mesa 9 is positioned on the right side of the first mesa 8 on the left side, and the lower end of the second mesa is positioned in the second channel layer 5;
the drain electrode 10 is positioned on the upper part of the first table-board 8 at the right side, adopts a multi-layer metal combination and forms ohmic contact with a contacted semiconductor;
the source electrode 11 is positioned at the upper part of the second table-board 9, adopts the same metal combination with the drain electrode 10, and forms ohmic contact with a contacted semiconductor;
the anode 12 is positioned at the upper part of the first table top 8 at the left side, is composed of multiple layers of metal and forms Schottky contact with a contacted semiconductor;
the gate 13 is located at the upper part of the P-type block 7 and has a length smaller than that of the P-type block 7.
Referring to fig. 4, the composite power switch device with embedded schottky diode according to the present invention provides the following three embodiments.
The first embodiment is as follows: the first channel layer 3, the first barrier layer 4, the second channel layer 5 and the second barrier layer 6 are respectively manufactured with the thicknesses of 200nm, 60nm, 200nm and 60nm, the thickness h of the P-type block 7 is 500nm, and the doping concentration is 1 multiplied by 10 16 cm -3 And the source electrode 11 is 30nm away from the upper surface of the first barrier layer 4.
A GaN material with the thickness of 50 mu m is epitaxially grown on a sapphire substrate 1 by using a metal organic chemical vapor deposition technology, and the process conditions are as follows: the temperature was 980 ℃, the pressure was 47Torr, the hydrogen flow was 4400sccm, the ammonia flow was 4400sccm, and the gallium source flow was 120. mu. mol/min.
And 2, manufacturing a channel layer and a barrier layer, as shown in fig. 4 b.
(2a) Extending a GaN material on the GaN transition layer 2 by using a metal organic chemical vapor deposition technology to form a first channel layer 3 with the thickness of 200 nm; the process conditions are as follows: the temperature is 950 ℃, the pressure is 43Torr, the hydrogen flow is 4000sccm, the ammonia flow is 4000sccm, and the gallium source flow is 100 mu mol/min;
(2b) epitaxial thickness S on the first channel layer 3 using a metal-organic chemical vapor deposition technique 1 60nm and an aluminum component of 0.2 0.2 Ga 0.8 N, forming a first barrier layer 4; the process conditions are as follows: the temperature is 980 ℃, the pressure is 45Torr, the hydrogen flow is 4400sccm, the ammonia flow is 4400sccm, the gallium source flow is 35 mu mol/min, and the aluminum source flow is 7 mu mol/min;
(2c) extending GaN material on the first barrier layer 4 by using a metal organic chemical vapor deposition technology to form a second channel layer 5 with the thickness of 200 nm; the process conditions are as follows: the temperature is 950 ℃, the pressure is 43Torr, the hydrogen flow is 4000sccm, the ammonia flow is 4000sccm, and the gallium source flow is 100 mu mol/min;
(2d) epitaxial thickness S on the second channel layer 5 using a metal-organic chemical vapor deposition technique 2 60nm and an aluminum component of 0.1 0.1 Ga 0.9 N, forming a second barrier layer 6; the process conditions are as follows: the temperature was 960 deg.C, the pressure was 42Torr, the hydrogen flow rate was 4200sccm, the ammonia flow rate was 4200sccm, the gallium source flow rate was 31. mu. mol/min, and the aluminum source flow rate was 5. mu. mol/min.
And 3, manufacturing a P-type block 7 on the second barrier layer 6, as shown in fig. 4 c.
(3a) A molecular beam epitaxy technique is used to epitaxially form a second barrier layer 6 having a thickness of 500nm and a doping concentration of 1 × 10 16 cm -3 Forming a P-type layer of the P-type GaN semiconductor material;
the process conditions adopted by molecular beam epitaxy are as follows: vacuum degree of 1.0 × 10 or less -10 mbar, radio frequency power of 420W, and N as reactant 2 And the high-purity Ga source takes a high-purity Mg source as a doping agent.
(3b) Manufacturing a mask on the P-type layer for the first time, etching the P-type layer by using the mask until the upper surface of the second barrier layer 6 is etched to form a P-type block 7;
the etching adopts the following process conditions: cl 2 The flow rate is 15sccm, the pressure is 10mTorr, and the power is 50W.
And 4, etching to form a mesa as shown in FIG. 4 d.
(4a) Making masks on the second barrier layer 6 and the P-type block 7 for the second time, respectively etching the two sides of the second barrier layer 6, the second channel layer 5, the first barrier layer 4 and the first channel layer 3 by using the masks and using a reactive ion etching technology until the two sides are etched to the upper surface of the transition layer 2, and forming a left first table top 8 and a right first table top 8;
(4b) a mask is manufactured on the second barrier layer 6, the P-type block 7 and the first table top 8 for the third time, the mask is used for etching the second barrier layer 6 and the second channel layer 5 on the right side of the first table top 8 on the left side in sequence by using the reactive ion etching technology again, the total etching depth is 230nm, and a second table top 9 on the left side is formed;
the etching adopts the following process conditions: cl 2 The flow rate is 15sccm, the pressure is 10mTorr, and the power is 100W.
Making a mask on the second barrier layer 6, the P-type block 7, the first mesa 8 and the second mesa 9 for the fourth time, depositing a plurality of layers of metals on the first mesa 8 and the second mesa 9 on the right side by using an electron beam evaporation technology, wherein the plurality of layers of metals are respectively Ti, Al, Ni and Au from bottom to top, the thicknesses of the metals are respectively 0.128 mu m/0.185 mu m/0.266 mu m/0.112 mu m, and the metal is coated on the N layer 2 And performing rapid thermal annealing treatment in the atmosphere to form a drain electrode 10 and a source electrode 11 respectively.
The process conditions adopted for depositing the metal are as follows: vacuum degree less than 1.8X 10 -3 Pa, power of 400W, evaporation rate of less than
The process conditions adopted by the rapid thermal annealing are as follows: the temperature was 850 ℃ and the time was 35 s.
Step 6, manufacturing the anode 12, as shown in fig. 4 f.
Making a mask on the second barrier layer 6, the P-type block 7, the first mesa 8, the drain electrode 10 and the source electrode 11 for the fifth time, depositing a plurality of layers of metal combinations W/Au on the first mesa 8 on the left side by using the mask through an electron beam evaporation technology, wherein the lower layer is W, the upper layer is Au, the thicknesses of the lower layer and the upper layer are respectively 0.895 mu m/0.70 mu m, forming Schottky contact between the deposited metal and the contacted semiconductor material, and completing the making of the anode 12;
the electron beam evaporation adopts the following process conditions: vacuum degree of 1.7X 10 -3 Pa, power 380W, evaporation rate
And 7, manufacturing and forming a grid 13 on the P-type block 7, as shown in FIG. 4 g.
Making a mask on the second barrier layer 6, the P-type block 7, the drain electrode 10, the source electrode 11 and the anode electrode 12 for the sixth time, and making use of the mask to ensure that the vacuum degree is less than 1.8 multiplied by 10 -3 Pa, power of 1000W, evaporation rate less than
Under the process conditions of (1), depositing a metal combination Ta/Ni on the P-type block 7 by using an electron beam evaporation technology, namely, the lower layer is Ta, the upper layer is Ni, the thicknesses of the Ta and the Ni are respectively 0.25 mu m/0.38 mu m, forming a grid 13, and finishing the manufacture of the whole device.
Example two: the first channel layer 3, the first barrier layer 4, the second channel layer 5 and the second barrier layer 6 are respectively manufactured with the thickness of 10nm, 2nm, 10nm and 2nm, the thickness h of the P-type block 7 is 10nm, and the doping concentration is 3 multiplied by 10 19 cm -3 And the source 11 is 3nm away from the upper surface of the first barrier layer 4.
Step one, a transition layer 2 is made by extending AlN and GaN materials from bottom to top on a silicon carbide substrate 1, as shown in figure 4 a.
(1.1) extending an undoped AlN material with the thickness of 100nm on the silicon carbide substrate 1 by using a metal organic chemical vapor deposition technology under the process conditions that the temperature is 1000 ℃, the pressure is 45Torr, the hydrogen flow is 4600sccm, the ammonia flow is 4600sccm and the aluminum source flow is 5 mu mol/min;
(1.2) using a metal organic chemical vapor deposition technology to epitaxially grow a GaN material with the thickness of 0.9 mu m on the AlN material under the process conditions that the temperature is 1000 ℃, the pressure is 45Torr, the hydrogen flow is 4600sccm, the ammonia flow is 4600sccm and the gallium source flow is 120 mu mol/min, and thus the manufacturing of the transition layer 2 is completed.
Step two, manufacturing a channel layer and a barrier layer on the GaN transition layer 2, as shown in FIG. 4 b.
(2.1) extending a GaN material on the GaN transition layer 2 by using a metal organic chemical vapor deposition technology under the process conditions of the temperature of 900 ℃, the pressure of 40Torr, the hydrogen flow of 4000sccm, the ammonia flow of 4000sccm and the gallium source flow of 90 mu mol/min to form a first channel layer 3 with the thickness of 10 nm;
(2.2) performing epitaxial thickness S on the first channel layer 3 by using a metal organic chemical vapor deposition technology under the process conditions that the temperature is 980 ℃, the pressure is 45Torr, the hydrogen flow is 4300sccm, the ammonia flow is 4300sccm, the gallium source flow is 35 mu mol/min and the aluminum source flow is 7 mu mol/min 1 Undoped Al of 2nm and an aluminum component of 0.4 0.4 Ga 0.6 N, forming a first barrier layer 4;
(2.3) extending a GaN material on the first barrier layer 4 by using a metal organic chemical vapor deposition technology under the process conditions that the temperature is 900 ℃, the pressure is 40Torr, the hydrogen flow is 4000sccm, the ammonia flow is 4000sccm and the gallium source flow is 90 mu mol/min to form a second channel layer 5 with the thickness of 10 nm;
(2.4) epitaxial thickness S on the second channel layer 5 by using metal organic chemical vapor deposition technology under the process conditions of 980 ℃, 45Torr pressure, 4200sccm hydrogen flow, 4200sccm ammonia flow, 39 mu mol/min gallium source flow and 5 mu mol/min aluminum source flow 2 Undoped Al of 2nm and an aluminum component of 0.35 0.35 Ga 0.65 N, forming a second barrier layer 6;
and step three, manufacturing a P-type block 7 on the second barrier layer 6, as shown in FIG. 4 c.
(3.1) magnetron sputtering technique is used, the sputtering power is 110W, the temperature is 300 ℃, the Ar flow is 20sccm, and O 2 The epitaxial doping concentration on the second barrier layer 6 is 3 multiplied by 10 under the process condition of the flow rate of 30sccm 19 cm -3 Forming a P-type NiO layer by using a NiO material with the thickness of 10 nm;
(3.2) first making a mask on the P-type NiO layer, using the mask to perform a reactive ion etching process on Cl 2 And etching the P-type NiO layer to the upper surface of the second barrier layer 6 to form a P-type block 7 under the process conditions of the flow of 15sccm, the pressure of 10mTorr and the power of 120W.
Step four, forming a mesa by etching, as shown in fig. 4 d.
(4.1) second mask is made on the second barrier layer 6 and the P-type block 7, using the mask to perform a reactive ion etching on Cl 2 Under the process conditions of 15sccm flow, 10mTorr pressure and 100W power, respectively etching the two sides of the second barrier layer 6, the second channel layer 5, the first barrier layer 4 and the first channel layer 3 until the upper surface of the transition layer 2to form a left first table top 8 and a right first table top 8;
(4.2) making a mask on the second barrier layer 6, the P-type block 7 and the first mesa 8 for the third time, and using the mask to reuse the reactive ion etching technology to form Cl 2 And under the process conditions of 15sccm flow, 10mTorr pressure and 90W power, sequentially etching the second barrier layer 6 and the second channel layer 5 on the right side of the first mesa 8 on the left side to a total etching depth of 9nm to form a second mesa 9 on the left side.
Step five, manufacturing the drain 10 and the source 11, as shown in fig. 4 e.
Making a mask on the second barrier layer 6, the P-type block 7, the first mesa 8 and the second mesa 9 for the fourth time, and using the mask to make electron beam evaporation at vacuum degree lower than 1.8 × 10 -3 Pa, power of 380W, evaporation rate of less than
Under the process conditions of (1), depositing a plurality of layers of metals of Ta, Ni and Au with the thicknesses of 0.016 μm/0.177 μm/0.058 μm from bottom to top on the first mesa 8 and the second mesa 9 on the right side, respectively, and performing N deposition at 870 deg.C 2 And performing rapid thermal annealing for 30s in the atmosphere to form the drain electrode 10 and the source electrode 11 respectively.
Step six, manufacturing the anode 12, as shown in fig. 4 f.
A mask is formed on the second barrier layer 6, the P-type block 7, the first mesa 8, the drain electrode 10 and the source electrode 11 for the fifth time, and electron beam evaporation is performed using the maskThe technology is carried out under the condition that the vacuum degree is 1.7 multiplied by 10 -3 Pa, power 390W, evaporation rate
Under the process conditions of (1), depositing a plurality of layers of metal combination Ni/Au on the first table top 8 at the left side, namely a lower layer of Ni and an upper layer of Au, wherein the thicknesses of the lower layer of Ni and the upper layer of Au are respectively 0.15 mu m/0.10 mu m, so that Schottky contact is formed between the deposited metal and the contacted semiconductor material, and the manufacture of the anode 12 is completed;
and step seven, manufacturing and forming a grid 13 on the P-type block 7, as shown in fig. 4 g.
And manufacturing a mask on the second barrier layer 6, the P-type block 7, the drain electrode 10, the source electrode 11 and the anode 12 for the sixth time, and depositing a metal combination Ta/Au on the P-type block 7 by using the mask under the process conditions that the sputtering pressure is about 0.1Pa, the flow rate of Ar is 8sccm, the substrate temperature is fixed at 200 ℃ and the target radio frequency power is 150W, namely the lower layer is Ta, the upper layer is Au, the thicknesses of the lower layer and the upper layer are respectively 0.021μm/0.28μm, forming a grid electrode 13, and finishing the manufacturing of the whole device.
Example three: the first channel layer 3, the first barrier layer 4, the second channel layer 5 and the second barrier layer 6 are respectively manufactured to have the thicknesses of 140nm, 35nm, 130nm and 20nm, the thickness h of the P-type block 7 is 120nm, and the doping concentration is 5 multiplied by 10 20 cm -3 And the source 11 is 10nm away from the upper surface of the first barrier layer 4.
Step A. epitaxial growth of AlN and GaN materials on a silicon substrate 1 from bottom to top to form a transition layer 2, as shown in FIG. 4 a.
A1) Setting the process conditions of 810 ℃, 42Torr of pressure, 4000sccm of hydrogen flow, 4000sccm of ammonia flow and 27 mu mol/min of aluminum source flow, and extending an AlN material with the thickness of 400nm on the silicon substrate 1 by using a metal organic chemical vapor deposition technology;
A2) setting the technological conditions of 980 deg.c, 45Torr pressure, 4000sccm hydrogen flow, 4000sccm ammonia flow and 120 micromol/min gallium source flow, and epitaxial growing 5.6 micron thick GaN material on AlN material by means of metal organic chemical vapor deposition to complete the making of the transition layer 2.
And B, manufacturing a channel layer and a barrier layer, as shown in figure 4 b.
B1) Setting the process conditions of 900 ℃, 42Torr of pressure, 4100sccm of hydrogen flow, 4100sccm of ammonia flow and 95 mu mol/min of gallium source flow, and extending GaN material on the GaN transition layer 2 by using a metal organic chemical vapor deposition technology to form a first channel layer 3 with the thickness of 140 nm;
B2) setting the technological conditions of 980 deg.C, 45Torr, 4400sccm of hydrogen flow, 4400sccm of ammonia flow, 34 mu mol/min of gallium source flow and 6 mu mol/min of aluminum source flow, and using metal organic chemical vapor deposition to epitaxially form a thickness S on the first channel layer 3 1 35nm and an aluminum component of 0.25 0.25 Ga 0.75 N, forming a first barrier layer 4;
B3) setting the technological conditions of 900 ℃ of temperature, 42Torr of pressure, 4100sccm of hydrogen flow, 4100sccm of ammonia flow and 95 mu mol/min of gallium source flow, and extending GaN material on the first barrier layer 4 by using a metal organic chemical vapor deposition technology to form a second channel layer 5 with the thickness of 130 nm;
B4) setting the technological conditions of 980 deg.C, 45Torr pressure, 4400sccm hydrogen flow, 4400sccm ammonia flow, 35 mu mol/min gallium source flow and 7 mu mol/min aluminum source flow, and using metal organic chemical vapor deposition to epitaxially form a thickness S on the second channel layer 5 2 20nm, and an aluminum component of 0.3 0.3 Ga 0.7 N, forming a second barrier layer 6;
step c. make P-type block 7 on second barrier layer 6, as shown in fig. 4 c.
C1) Setting the target material as copper with the purity of 99.999 percent, high-purity argon as sputtering gas, high-purity oxygen with the same purity as reaction gas, and setting the vacuum degree of the reaction chamber before sputtering as 2.0 multiplied by 10 -4 Pa, keeping the flow rate of Ar at 20sccm and O in sputtering 2 The flow rate is 10sccm, the gas pressure of the deposition chamber is 0.5Pa, the radio frequency power is 35W, the substrate temperature is 200 ℃, and the magnetron sputtering technology is used to epitaxially form a second barrier layer 6 with the thickness of 120nm and the doping concentration of 5 multiplied by 10 20 cm -3 Forming a P-type layer.
C2) Setting up Cl 2 Etching process conditions of 15sccm flow, 10mTorr pressure and 50W power are adopted, a mask is manufactured on the P-type layer for the first time, the P-type layer is etched by the mask until the upper surface of the second barrier layer 6 is etched, and a P-type block 7 is formed;
and D, etching to form a mesa as shown in FIG. 4 d.
D1) Setting up Cl 2 Etching process conditions of 15sccm flow, 10mTorr pressure and 100W power, manufacturing a mask on the second barrier layer 6 and the P-type block 7 for the second time, respectively etching the two sides of the second barrier layer 6, the second channel layer 5, the first barrier layer 4 and the first channel layer 3 by utilizing the mask and using a reactive ion etching technology until the etching reaches the upper surface of the transition layer 2, and forming a left first table top 8 and a right first table top 8;
D1) setting up Cl 2 And under the etching process conditions of 15sccm flow, 10mTorr pressure and 90W power, making a mask on the second barrier layer 6, the P-type block 7 and the first table top 8 for the third time, and utilizing the mask to sequentially etch the second barrier layer 6 and the second channel layer 5 on the right side of the first table top 8 on the left side by using a reactive ion etching technology, wherein the total etching depth is 100nm, so that the second table top 9 on the left side is formed.
Step e, the drain 10 and the source 11 are fabricated, as shown in fig. 4 e.
Setting the vacuum degree to be less than 1.8 multiplied by 10 -3 Pa, power of 410W, evaporation rate of less than
The deposition process conditions of (1) making a mask on the second barrier layer 6, the P-type block 7, the first table-board 8 and the second table-board 9 for the fourth time, utilizing the mask to deposit a plurality of layers of metals on the first table-board 8 and the second table-board 9 on the right side by using an electron beam evaporation technology, wherein the plurality of layers of metals are respectively Al, Ni and Au from bottom to top, the thicknesses of the metals are respectively 0.116 mu m/0.177 mu m/0.068 mu m, and the N is N at the temperature of 820 DEG C 2 And performing rapid thermal annealing treatment in the atmosphere for 30s to form the drain electrode 10 and the source electrode 11 respectively.
Step f, anode 12 is fabricated as shown in fig. 4 f.
The vacuum degree was set to 1.7X 10 -3 Pa, power 380W, evaporation rate
The deposition process conditions of (1) manufacturing a mask on the second barrier layer 6, the P-type block 7, the first table 8, the drain electrode 10 and the source electrode 11 for the fifth time, and depositing a plurality of layers of metal combinations Ti/Au on the first table 8 on the left side by utilizing the mask by using an electron beam evaporation technology, namely the lower layer is Ti, the upper layer is Au, the thicknesses of the Ti and the Au are respectively 0.25 mu m/0.10 mu m, so that Schottky contact is formed between the deposited metal and the contacted semiconductor material, and the manufacturing of the anode 12 is completed;
step g, forming a gate 13 on the P-type block 7, as shown in fig. 4 g.
Setting the vacuum degree to be less than 1.8 multiplied by 10 -3 Pa, power of 1000W, evaporation rate of less than
The process conditions of (1) manufacturing a mask on the second barrier layer 6, the P-type block 7, the drain electrode 10, the source electrode 11 and the anode 12 for the sixth time, and depositing a metal combination Gd/Au on the P-type block 7 by utilizing the mask by using an electron beam evaporation technology, wherein the lower layer is Gd, the upper layer is Au, and the thicknesses of the Gd and the Au are respectively 0.25 mu m/0.18 mu m; and forming a grid 13 to finish the manufacture of the whole device.
The effects of the present invention can be further illustrated by the following experimental results.
The experimental contents are as follows: the device of the first embodiment of the present invention is subjected to a bidirectional conduction test, and the result is shown in fig. 5.
As can be seen from fig. 5, the device of the present invention can simultaneously realize forward and reverse conduction, and has excellent bidirectional conduction characteristics.
The foregoing description is only three specific embodiments of the present invention and is not intended to limit the present invention, and it will be apparent to those skilled in the art that various modifications and variations in form and detail can be made in the method according to the present invention without departing from the principle and scope of the invention, but these modifications and variations are within the scope of the invention as defined in the appended claims.
Claims (8)
1. A composite power switch device with embedded Schottky diodes comprises from bottom to top: substrate (1), transition layer (2), second channel layer (5), second barrier layer (6), P type piece (7) and grid (13), its characterized in that:
a first channel layer (3) and a first barrier layer (4) are inserted between the transition layer (2) and the second channel layer (5), and the first barrier layer (4) is positioned on the upper part of the first channel layer (3);
the left side and the right side of the first channel layer (3), the first barrier layer (4), the second channel layer (5) and the second barrier layer (6) are respectively provided with a first table top (8), the first table top on the left side is provided with an anode (12), the first table top on the right side is provided with a drain (10), and the lower ends of the two first table tops are respectively positioned at the upper part of the transition layer (2);
a second table top (9) is arranged on the right side of the first table top (8) on the left side, the lower end of the second table top is positioned in the second channel layer (5), and a source electrode (11) is arranged on the second table top;
the contact interface of the first channel layer (3) and the first barrier layer (4) forms an electronic channel, and the channel, the drain electrode (10) and the anode (12) jointly form a Schottky diode structure;
the second channel layer (5), the second barrier layer (6), the P-type block (7), the drain electrode (10), the source electrode (11) and the grid electrode (13) jointly form a power switch transistor.
2. Device according to claim 1, characterized in that the substrate (1) is made of sapphire or silicon carbide or silicon or graphene or other materials.
3. Device according to claim 1, characterized in that the thickness S of the first barrier layer (4) 1 2to 60nm, and the thickness S of the second barrier layer (6) 2 2to 60 nm.
4. The device according to claim 1, wherein the thickness h of the P-type block (7) is 10 to 500nm, and the doping concentration thereof is 1 x 10 16 ～5×10 20 cm -3 When determining the thickness of the P-type block (7), it is ensured that it has little depletion effect on the first barrier layer (4).
5. The device according to claim 1, characterized in that the drain (10) and source (11) are made of a multilayer metal combination and both form ohmic contacts with the contacting semiconductor.
6. A method for manufacturing a composite power switch device with an embedded Schottky diode is characterized by comprising the following steps:
A) a GaN-based wide bandgap semiconductor material is epitaxially grown on a substrate (1) to form a transition layer (2) with the thickness of 1-50 mu m;
B) manufacturing a channel layer and a barrier layer:
B1) extending a GaN material on the transition layer (2) to form a first channel layer (3) with the thickness of 10-200 nm;
B2) a GaN-based wide bandgap semiconductor material is epitaxially formed on the first channel layer (3) to a thickness S 1 A first barrier layer (4) of 2to 60 nm;
B3) extending a GaN material on the first barrier layer (4) to form a second channel layer (5) with the thickness of 10-200 nm;
B4) epitaxially growing a GaN-based wide bandgap semiconductor material on the second channel layer (5) to a thickness S 2 A second barrier layer (6) of 2to 60 nm;
C) and manufacturing a P-type block (7) on the second barrier layer (6):
C1) extending a P-type semiconductor material on the second barrier layer (6) to form a P-type layer;
C2) manufacturing a mask on the P-type layer for the first time, and etching the P-type layer by using the mask to form a P-type block (7);
D) etching to form a table top:
D1) manufacturing masks on the second barrier layer (6) and the P-type block (7) for the second time, respectively etching the two sides of the second barrier layer (6), the second channel layer (5), the first barrier layer (4) and the first channel layer (3) by using the masks until the upper surfaces of the transition layers (2) are etched, and forming a left first table top and a right first table top (8);
D2) a mask is made on the second barrier layer (6), the P-type block (7) and the first table top (8) for the third time, the mask is utilized to sequentially etch the second barrier layer (6) and the second channel layer (5) on the right side of the first table top (8) on the left side, the etching depth is larger than the thickness of the second barrier layer (6) and smaller than the total thickness of the second channel layer (5) and the second barrier layer (6), and a second table top (9) on the left side is formed;
E) making a mask on the second barrier layer (6), the P-type block (7), the first table top (8) and the second table top (9) for the fourth time, and respectively depositing a plurality of layers of metal on the first table top (8) and the second table top (9) on the right side by using the mask to form a drain electrode (10) and a source electrode (11);
F) making a mask on the second barrier layer (6), the P-type block (7), the first table top (8), the drain electrode (10) and the source electrode (11) for the fifth time, depositing a plurality of layers of metal on the first table top (8) on the left side by using the mask to form an anode (12), wherein Schottky contact is formed between the anode (12) and the contacted semiconductor material;
G) and (3) making a mask on the second barrier layer (6), the P-type block (7), the drain electrode (10), the source electrode (11) and the anode electrode (12) for the sixth time, and depositing a plurality of layers of metal on the P-type block (7) by using the mask to form a grid electrode (13) so as to finish the manufacture of the whole device.
7. Method according to claim 6, characterized in that the epitaxy technique used in steps A), B), C) comprises: metal organic chemical vapor deposition technology, molecular beam epitaxy technology, plasma enhanced atomic layer deposition technology and magnetron sputtering technology.
8. The method of claim 6, wherein the metal deposition process used in steps E), F), G) comprises: electron beam evaporation process, sputtering process.
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