JP4277381B2 - Silicon carbide semiconductor device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a silicon carbide semiconductor device and a method of manufacturing the same, and more particularly to an insulated gate field effect transistor, particularly a high power power MOSFET.
[0002]
[Prior art]
Conventionally, as a planar type MOSFET operating in the accumulation mode, one disclosed in Japanese Patent Application Laid-Open No. 11-308510 is known.
[0003]
A cross-sectional view of this planar MOSFET is shown in FIG. The structure of the planar MOSFET will be described with reference to this figure.
[0004]
n⁺Type silicon carbide semiconductor substrate (hereinafter n⁺The mold substrate 1) has an upper surface as a main surface 1a and a lower surface opposite to the main surface as a back surface 1b. This n⁺N having a lower dopant concentration than that of the substrate 1 on the main surface of the semiconductor substrate 1^-Type silicon carbide epitaxial layer (hereinafter n^-2) (referred to as a type epi layer).
[0005]
n^-The predetermined region in the surface layer portion of the type epi layer 2 has p having a predetermined depth.^-Type silicon carbide base regions 3a and p^-Type silicon carbide base region 3b (hereinafter, p^-Mold base regions 3a and 3b) are formed apart from each other. P^-The predetermined region in the surface layer portion of the mold base region 3a includes p^-Shallower than the mold base region 3a⁺The type source region 4a is also p^-The predetermined region in the surface layer portion of the mold base region 3b includes p^-Shallower than the mold base region 3b⁺Each of the mold source regions 4b is formed.
[0006]
N⁺Type source regions 4a and n⁺N with the source region 4b^-Type epi layer 2 and p^-N on the surface of the mold base regions 3a and 3b^-A type SiC layer 5 is extended. That is, p^-Source regions 4a, 4b and n on the surface of the mold base regions 3a, 3b^-N so as to connect to the epitaxial layer 2^-A type SiC layer 5 is arranged. This n^-The type SiC layer 5 is formed by epitaxial growth, and the epitaxial film crystal is 4H, 6H, or 3C. The epitaxial layer can form various crystals regardless of the underlying substrate. It functions as a channel formation layer on the device surface during device operation. N^-The type SiC layer 5 is referred to as a surface channel layer.
[0007]
The dopant concentration of the surface channel layer 5 is 1 × 10¹⁵cm^-3~ 1x10¹⁷cm^-3Low concentration, and n^-Type epi layer 2 and p^-It is below the dopant concentration of the mold base regions 3a and 3b. Thereby, low on-resistance is achieved.
[0008]
P^-Mold base regions 3a, 3b, n⁺Concave portions 6a and 6b are formed in the surface portions of the mold source regions 4a and 4b.
[0009]
The upper surface of the surface channel layer 5 and n⁺A gate insulating film (silicon oxide film) 7 is formed on the upper surfaces of the mold source regions 4a and 4b. Further, a gate electrode 8 is formed on the gate insulating film 7. The gate electrode 8 is covered with an insulating film 9. As the insulating film 9, an LTO (Low Temperature Oxide) film is used. A source electrode 10 is formed thereon, and the source electrode 10 is n⁺Type source regions 4a, 4b and p^-It is in contact with the mold base regions 3a and 3b. N⁺A drain electrode layer 11 is formed on the back surface of the mold substrate 1.
[0010]
[Problems to be solved by the invention]
In the above conventional MOSFET, the on-resistance is reduced by operating in the accumulation mode. However, further reduction of on-resistance is desired.
[0011]
The present invention has been made in view of the above points, and an object thereof is to further reduce the on-resistance in an accumulation mode MOSFET.
[0012]
[Means for Solving the Problems]
In order to achieve the above object, the present inventors have studied an accumulation mode MOSFET. As the surface channel layer is concentrated and the threshold voltage is lowered, the on-current increases, that is, the on-resistance is reduced. It has been found that it can be reduced. FIG. 17 shows the relationship between the concentration of the surface channel layer and the on-current.
[0013]
As shown in this figure, the lower the threshold voltage, the larger the on-current. In particular, it was found that the on-current was significantly increased by using a negative depletion type MOS. .
[0014]
However, the depletion type MOSFET is normally on, and is not preferable from the viewpoint of fail-safe. Accordingly, the present inventors have further studied to obtain a MOSFET having an on-current equivalent to that of a depletion type MOSFET and having normally-on characteristics.
[0015]
Since the depletion type MOSFET has normally-on characteristics, switching can be performed by applying a negative voltage on the surface channel layer.
[0016]
That is, if a negative voltage is applied to the surface channel layer when no voltage is applied to the gate electrode (zero gate voltage), the enhancement type is positive (normally off characteristics). MOSFET.
[0017]
  Therefore, in order to achieve the above object, the invention according to claim 1 or 2 has a mechanism capable of holding electric charge between the gate electrode (8) and the surface channel layer (5). Yes. In particular,The gate insulating film includes a first gate insulating film (7a, 57a) and a second gate insulating film (7b, 57b), and is electrically conductive between the first and second gate insulating films. The floating gates (12, 60) can be arranged to hold charges in the floating gate. Such a charge holding mechanism using a floating gate can hold charges with high reliability.
[0018]
In this way, by providing the charge holding mechanism, the charge holding mechanism can be a negative potential even when the gate potential is used at zero or more, so that the on-resistance equivalent to the depletion type is obtained while maintaining the normally-off characteristic. It can be set as the silicon carbide semiconductor device which has.
[0021]
  Also,Claim1 or 2In the invention described in (1), the semiconductor substrate has a MOS operation region in which a channel region is formed to perform a MOS operation, and a write region provided at a position different from the MOS operation region. The semiconductor device is characterized in that it extends from the MOS operation region to the writing region, and charges are injected into the writing region.
[0022]
  Thus, by limiting the area rather than performing writing using the entire MOSFET, the amount of writing can be easily controlled and a large amount of writing can be obtained. In addition, by providing a write terminal, even if the gate insulating film is damaged in the charge injection portion at the time of writing, the damaged region is located at a position different from the MOS operation region, so that the normal MOS is not affected by the damaged region. Operation is possible.
  In the writing region, a writing gate that is not electrically connected to the gate electrode in the MOS operation region may be formed on the floating gate, and a writing terminal may be connected to the gate.
  Further, in the first or second aspect of the invention, the surface channel layer includes the source electrode and the drain electrode even under a condition in which no voltage is applied to the gate electrode in a state where the charge is not held in a mechanism capable of holding the charge. It is characterized in that electrical conduction between the two is possible.
  Thus, if there is no offset of the gate voltage due to the charge holding mechanism, a particularly high current capability can be obtained in the case of a depletion type MOSFET, which is preferable.
[0023]
  For example, as described in claim 3, the gate insulating film is formed of a composite film of a silicon oxide film and a silicon nitride film, and charges can be held at the interface between the silicon oxide film and the silicon nitride film. In this case, it is possible to cope with the conventional manufacturing process only by changing the gate insulating film with a composite film of a silicon oxide film and a silicon nitride film, so that a charge holding mechanism can be realized with a slight process load. .
  Also,For example, claims4As shown in FIG. 2, in the writing region, a gate electrode extends from the MOS operation region to the writing region, and on the surface portion of the semiconductor substrate, both sides of the gate electrode and the floating gate in the writing region are provided.SeoSource and drain for writing,bookWhat is necessary is just to make it the structure which connected the terminal for writing to each of the drain for penetration.
[0024]
In such a configuration, charge injection can be performed using hot carriers. Thus, writing can be performed at high speed by using hot carrier injection.
[0026]
  Claims5As shown in FIG. 2, the write region is provided with a gate electrode extending from the MOS operation region to the write region, and is not electrically connected to a base region or a well region disposed below the floating gate. A two-conductivity type writing drain may be provided, and a writing terminal connected to the writing drain may be provided.
[0027]
In such a configuration, charge injection can be performed using the FN current. In this manner, by using the FN current, the writing region and the writing terminal can be simplified and the size can be reduced.
[0030]
  Claim6In the invention described in (1), the first gate insulating film or the second gate insulating film is partially thinned in the writing region.
[0031]
Thus, by partially thinning the first and second insulating films, a writing region can be set without providing a writing terminal. By limiting the area rather than performing writing using the entire MOSFET, the amount of writing can be easily controlled and a large amount of writing can be obtained. Further, since there is no writing terminal, the size can be reduced.
[0034]
In addition, the code | symbol in the bracket | parenthesis of each said means shows the correspondence with the specific means as described in embodiment mentioned later.
[0035]
DETAILED DESCRIPTION OF THE INVENTION
DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments shown in the drawings will be described below.
[0036]
FIG. 1 shows a cross-sectional configuration of the MOSFET in the present embodiment. Hereinafter, the configuration of the MOSFET of this embodiment will be described with reference to FIG. However, among the MOSFETs of the present embodiment, the same or equivalent configurations as those of the conventional MOSFET shown in FIG. 16 are denoted by the same reference numerals as those in FIG. 16, and only different portions will be described.
[0037]
As shown in FIG. 1, in the MOSFET according to the present embodiment, a floating gate 12 is formed on a surface channel layer 5 via a silicon oxide film 7 a as a first insulating film, and on the floating gate 12. A gate electrode 8 is formed through a silicon oxide film 7b as a second insulating film. That is, this MOSFET employs a two-layer gate structure. Electrons having negative charges are injected into the floating gate 12. Further, the surface channel layer 5 has a higher concentration than the conventional one, and for example, the dopant concentration is 1 × 10 10.¹⁶cm^-3~ 1x10¹⁸cm^-3It is about. A suitable dopant concentration depends on the thickness of the surface channel layer 5, and when the surface channel layer 5 is thin, it is preferable to set a higher dopant concentration than when it is thick.
[0038]
In the MOSFET configured as described above, by providing the floating gate 12 as a charge holding mechanism between the gate electrode 8 and the surface channel layer 5, the electric field on the surface of the surface channel layer 5 can be reduced via the floating gate 12. It is supposed to change.
[0039]
That is, since the floating gate 12 is provided on the surface channel layer 5, the channel between the source and drain is formed at the floating gate potential. Therefore, this is different from the conventional one shown in FIG. 16 in which the channel is formed with the gate potential.
[0040]
The total thickness of the silicon oxide film 7a and the silicon oxide film 7b corresponds to the film thickness of the oxide film 7 of the conventional MOSFET shown in FIG. 16, and the MOS of this embodiment and the conventional MOSFET When the gate potential is the same, the operation state is the same as that of the conventional MOSFET, that is, the same electric field is applied.
[0041]
Electrons are injected into the floating gate 12. As a result, the floating gate potential is set to a desired value, and an offset is applied to the relationship between the gate voltage and the electric field on the semiconductor surface.
[0042]
The offset of this electric field is set as follows.
[0043]
If the potential on the surface channel layer 5 side is zero, the floating gate potential is expressed by the following equation.
[0044]
[Expression 1]
Vfg = (C2 · Vg + Q) / (C1 + C2)
Where Vfg is the floating gate potential, Vg is the gate potential, C1 is the capacitance between the floating gate 12 and the semiconductor, C2 is the capacitance between the floating gate 12 and the gate electrode 8, and Q is the charge in the floating gate 12.
[0045]
Accordingly, by arbitrarily setting the charge Q in the floating gate 12, it is possible to offset the relationship between the floating gate potential Vfg and the gate potential Vg.
[0046]
Therefore, as described above, by injecting electrons as a negative charge into the floating gate 12, the floating gate 12 can take a negative potential when the gate potential is used at zero or more.
[0047]
FIG. 2 shows the relationship between the potential of the gate electrode 8 (hereinafter simply referred to as the gate potential) and the floating gate potential before and after electrons are injected into the floating gate 12, and the potential applied to the surface channel layer 5. The relationship with (that is, the floating gate potential) will be described.
[0048]
This figure shows a case where the film thicknesses of the silicon oxide films 7a and 7b are set so that the floating gate potential becomes 2/3 of the gate potential before the charge injection.
[0049]
As shown in this figure, when electrons are injected into the floating gate 12, the relationship between the floating gate potential and the gate potential is shifted. For this reason, even when the gate potential is used only as positive, the floating gate 12 can be set to a negative potential. Thus, even if the gate potential is positive, the floating gate potential can be made negative, and a negative voltage can be applied to the surface channel layer 5.
[0050]
FIG. 3 shows the relationship between the gate potential, the floating gate potential, and the drain current when the floating gate 12 is provided in this way.
[0051]
As shown in this figure, the surface channel layer 5 is highly concentrated so that a negative voltage is required to turn off the channel. If the floating gate potential does not become negative, the drain current is zero, that is, the channel is It is designed not to turn off. However, since the charge of Q <0 exists in the floating gate 12, even if the gate potential is zero or more, the floating gate potential can be made negative, and the channel is turned off at the gate potential Vg = 0V. Can do.
[0052]
Next, the operation (operation) of the MOSFET in this embodiment will be described.
[0053]
This MOSFET operates in a normally-off accumulation mode, and when no voltage is applied to the gate electrode 8, a negative potential is applied to the surface channel layer 5 by the floating gate 12. For this reason, in the surface channel layer 5, carriers are p.^-The channel is formed by a depletion layer formed by a difference in electrostatic potential between the mold base regions 3 a and 3 b and the surface channel layer 5 and a depletion layer formed on the surface of the surface channel layer 5 by the negative potential of the floating gate 12. Is turned off.
[0054]
Subsequently, the potential of the floating gate 12 is raised by applying a voltage to the gate electrode 8. As a result, the depletion layer on the surface channel layer 5 is reduced, and n at the interface between the silicon oxide film 7a and the surface channel layer 5 is reduced.⁺Type source regions 4a, 4b to n^-A channel region extending in the direction of the type drift region 2 is formed and switched to the on state.
[0055]
At this time, electrons are n⁺From the source channel regions 4a and 4b through the surface channel layer 5 to the surface channel layer 5^-It flows in the mold epi layer 2. And n^-When reaching the epitaxial layer 2 (drift region), the electrons are n⁺Mold substrate 1 (n⁺Flows vertically to the drain).
[0056]
As described above, a MOSFET operating as a depletion type without the floating gate 12 into which electrons are injected has a normally-off characteristic that allows the channel to be turned off when the gate potential is substantially zero due to the negative potential of the floating gate 12. Operates as an enhancement type MOSFET.
[0057]
As a result, as shown in FIG. 17, when the floating gate 12 is not provided, the on-resistance is equivalent to that of a depletion type MOSFET, and the on-resistance can be further reduced. In addition, this makes it possible to increase the power of the device and reduce the size of the chip. In addition, by holding charges in the floating gate 12 in this way, it is possible to hold charges with high reliability.
[0058]
Next, the manufacturing process of the MOSFET in this embodiment will be described with reference to FIGS. Since the semiconductor region is the same as that of the conventional publication (Japanese Patent Laid-Open No. 11-308510), only different parts will be described.
[0059]
[Step shown in FIG. 4 (a)]
First, 4H or 6H SiC substrate, that is, n⁺A mold substrate 1 is prepared. Where n⁺The mold substrate 1 has a thickness of 400 μm, and the main surface 1a is a (0001) Si plane or a (112-0) a plane. The main surface 1a of the substrate 1 has an n thickness of 5 μm.^-The epitaxial epitaxial layer 2 is epitaxially grown. In this example, n^-The type epi layer 2 has the same crystal as the underlying substrate 1 and becomes an n-type 4H, 6H, or 3C—SiC layer.
[0060]
[Step shown in FIG. 4B]
n^-An LTO film 20 is arranged in a predetermined region on the type epi layer 2 and is used as a mask for B⁺(Or aluminum) ion implantation, p^-Mold base regions 3a and 3b are formed. The ion implantation conditions at this time are a temperature of 700 ° C. and a dose of 1 × 10 6.¹⁶cm^-2It is said.
[0061]
[Step shown in FIG. 4 (c)]
After removing the LTO film 20, p^-N including mold base regions 3a and 3b^-A surface channel layer 5 is epitaxially grown on the epitaxial layer 2 by chemical vapor deposition (CVD). The source gas at this time is SiH_Four, C_ThreeH₈, H₂, N₂Is used. Where N₂Is used to make the surface channel layer 5 n-type.
[0062]
[Step shown in FIG. 5A]
An LTO film 21 is arranged in a predetermined region on the surface channel layer 5, and this is used as a mask.⁺Ion implantation, and n⁺Mold source regions 4a and 4b are formed. The ion implantation conditions at this time are 700 ° C., and the dose is 1 × 10.¹⁵cm^-2It is said.
[0063]
[Step shown in FIG. 5B]
Then, after removing the LTO film 21, an LTO film 22 is disposed in a predetermined region on the surface channel layer 5 using a photoresist method, and this is used as a mask to perform p^-The surface channel layer 5 on the mold base regions 3a and 3b is partially etched away.
[0064]
[Step shown in FIG. 5 (c)]
After removing the LTO film 22, a gate oxide film 7a is formed on the substrate by wet oxidation. At this time, the ambient temperature is set to 1080 ° C.
[0065]
Next, in order to form the floating gate 12 on the gate oxide film 7a, 1st-polySi 20 is deposited by LPCVD.
[0066]
Subsequently, after the 1st-polySi 20 is oxidized to form a gate oxide film 7b, 2nd-polySi 21 is deposited by LPCVD in order to form the gate electrode 8 on the gate oxide film 7b.
[0067]
[Step shown in FIG. 6A]
Then, 2nd-polySi21, silicon oxide film 7b, and 1st-polySi20 are patterned through a photolithography process. Thereby, the gate electrode 8 and the floating gate 12 are formed.
[0068]
Subsequently, the surfaces of the gate electrode 8 and the floating gate 12 are covered with an oxide film by thermal oxidation. Thereafter, an interlayer insulating film 9 made of LTO is formed to cover the gate insulating film 7.
[0069]
  [Fig. 6 (bProcess shown in
  Then, after forming contact holes in the interlayer insulating film 9 and the oxide film, the source electrode 10 and the drain electrode 11 are disposed by metal sputtering at room temperature. Further, annealing at 1000 ° C. is performed after film formation.
[0070]
Thereafter, charge is injected into the floating gate 12. The schematic diagram of the charge injection is shown in FIG. 7, and the charge injection will be described with reference to FIG.
[0071]
In charge injection, a potential sufficient to cause charge transfer between the floating gate 12 and the semiconductor (the surface channel layer 5 and the source regions 4a and 4b) or between the floating gate 12 and the gate electrode 8 is applied to the gate electrode 8. By doing. This is selected depending on which of the floating gate 12 and the semiconductor, or between the floating gate 12 and the gate electrode 8 is more likely to pass current. That is, since the ease of current flow is determined by the film quality (thickness distribution, defects, etc.) of the silicon oxide films 7a and 7b, the film quality of the silicon oxide films 7a and 7b should be set in advance so as to facilitate charge injection. Is also possible.
[0072]
When current flows more easily between the floating gate 12 and the semiconductor than between the floating gate 12 and the gate electrode 8, as shown in FIG. 7A, the source electrode 10 and the drain electrode 11. Is grounded, and a positive voltage is applied to the gate electrode 8. As a result, electrons are injected into the floating gate 12 as negative charges. Further, when current flows more easily between the floating gate 12 and the gate electrode 8 than between the floating gate 12 and the semiconductor, as shown in FIG. Is grounded, and a negative voltage is applied to the gate electrode 12. As a result, electrons are injected into the floating gate 12 as negative charges.
[0073]
In this way, the MOSFET shown in FIG. 1 is completed.
[0074]
(Second Embodiment)
FIG. 8 shows a cross-sectional configuration of the MOSFET in this embodiment. In this embodiment, since the gate structure of the MOSFET of the first embodiment is changed, only the changed portion will be described.
[0075]
As shown in FIG. 8, in the MOSFET of this embodiment, a silicon nitride film 13 is formed on the surface channel layer 5 via a silicon oxide film 7a as a first insulating film. A gate electrode 8 is formed on the silicon nitride film 13. Thus, a composite film composed of the silicon oxide film 7 a and the silicon nitride film 13 is arranged between the gate electrode 8 and the surface channel layer 5.
[0076]
In such a configuration, charges can be trapped at the interface between the silicon nitride film 13 and the silicon oxide film 7a. For this reason, the charge trapped at this interface plays a role similar to that of the floating gate 12 of the first embodiment, and the voltage of the gate electrode 8 can be offset. Thereby, the effect similar to 1st Embodiment is acquired.
[0077]
Note that the MOSFET in this embodiment only increases the number of steps of forming the silicon nitride film 13 compared to the conventional MOSFET shown in FIG. 16, so that a charge holding mechanism can be realized with a slight process load. Can do.
[0078]
(Third embodiment)
FIG. 9 shows a cross-sectional configuration of the MOSFET in this embodiment. This embodiment defines a region where charge injection is performed when injecting charges into the floating gate, as compared to the first embodiment.
[0079]
As shown in FIG. 9, the MOSFET of the present embodiment forms a write region for injecting charges in addition to the MOS operating region. The writing area is provided in a cross section other than the MOS operating area. For example, if the MOS operating area is formed by laying a plurality of MOSFETs, the writing area is separately provided at a position away from the laid area. Yes.
[0080]
The writing region has the same structure as a so-called EPROM, and a source region 4c and a drain region 14 are provided on both sides of a two-layer structure of a floating gate 12a and a gate electrode (control gate) 8a. A surface channel layer 5 c serving as a channel region is provided between the region 14 and the region 14. The source region 4 c is an extension of the source region 4 b and is connected to the source electrode 10. In this way, the size of the device is reduced by sharing the source region 4c and the source region 4b. The drain region 14 is connected to the drain electrode 15.
[0081]
In addition, the gate electrodes 8 and 8a in the MOS operation region and the writing region are connected, and the floating gates 12 and 12a in the MOS operation region and the writing region are connected (dotted line portion in the figure). reference).
[0082]
In such a configuration, charge injection is performed in the write region as shown in FIG. That is, the source electrode 10 and the drain electrode 11 are grounded, and a positive potential V1 is applied to the gate electrode 8a and a positive potential V2 is applied to the drain electrode. As a result, hot carriers can be generated and hot electrons can be injected into the floating gate 12a.
[0083]
Thus, when negative charges are injected into the floating gate 12a, the floating gate 12 is connected to the floating gate 12a, so that the potential of the floating gate 12 becomes negative even if the potential of the gate electrode 8 is zero. As a result, the MOS operation region can be operated in the same manner as in the first embodiment, and the same effect as in the first embodiment can be obtained.
[0084]
By using hot carriers, writing can be performed at high speed. In addition, since writing is performed in a region other than the MOS operation region, even if the silicon oxide film 7a under the floating gate 12a is damaged at the time of writing, it is a portion unrelated to the MOS operation region. There is no impact. Since the drain electrode 15 is in an open state during the MOS operation, the influence of the electric field in the drain region 14 can be ignored.
[0085]
Note that the manufacture of the MOSFET in this embodiment is omitted because it is only necessary to change the mask of the photolithography step in the step of FIG. 6A in the first embodiment.
[0086]
(Fourth embodiment)
FIG. 11 shows a cross-sectional configuration of the MOSFET in the present embodiment. This embodiment defines a region where charge injection is performed when injecting charges into the floating gate, as compared to the first embodiment.
[0087]
As shown in FIG. 11, the MOSFET according to the present embodiment forms a write area for charge injection in addition to the MOS operating area. The writing area is provided in a cross section other than the MOS operating area. For example, if the MOS operating area is formed by laying a plurality of MOSFETs, the writing area is separately provided at a position away from the laid area. Yes.
[0088]
The writing region has a two-layer structure of a floating gate 12a and a gate electrode (control gate) 8a, and a two-layer structure is formed on the source region 4c extending from the source region 4b. Yes.
[0089]
Further, the floating gates 12 and 12a in the MOS operation region and the writing region are connected (see the dotted line portion in the figure). However, the gate electrodes 8 and 8a in the MOS operation region and the writing region are not connected.
[0090]
In such a configuration, charge injection is performed in the write region as shown in FIG. That is, the gate electrode 8, the source electrode 10, and the drain electrode 11 are grounded, and a negative potential −V is applied to the gate electrode 8a.
[0091]
Usually, the capacitance between the gate electrode 8a in the writing region and the floating gate 12a is the capacitance between the gate electrode 8 in the MOS operation region and the floating gate 12, or the floating gate 12 and the semiconductor (in this embodiment, the surface channel layer). 5 and the capacitance between the source regions 4a and 4b), the potential of the floating gate 12 is hardly affected by the potential of the gate electrode 8a in the writing region, that is, the potential of the gate electrode 8 and the semiconductor, It becomes ground (however, the potential fluctuates by the written charge). For this reason, the electric field between the gate electrode 8a in the writing region and the floating gate 12a is maximized, so that charge injection can be performed only in the writing region, and a large amount of writing can be performed by the FN current.
[0092]
As described above, with the above configuration, a large amount of data can be written, and, similarly to the third embodiment, data can be written in an area other than the MOS operation area. Even if the silicon oxide film 7b is damaged, the MOS operation is not affected. In addition, since the FN current is used, the writing region and the writing terminal as a contact with each region can be simplified, and the device can be miniaturized.
[0093]
In the manufacture of the MOSFET in the present embodiment, a mask in which the gate electrode 8 and the gate electrode 8a are divided during the etching of 2nd-polySi is used as a mask for the photolithography process of the process of FIG. 6A in the first embodiment. The other uses are the same as those of the third embodiment, and the description thereof is omitted.
[0094]
In the present embodiment, the lower portion of the floating gate 12 in the write region is the source region 4c, that is, n.⁺Although it is composed of a mold layer, n is provided by extending the surface channel layer 5 or the like.^-It may be composed of a mold layer, or may be composed of a p-type layer by extending the base region 3b.
[0095]
(Fifth embodiment)
FIG. 13 shows a cross-sectional configuration of the MOSFET in the present embodiment. This embodiment defines a region where charge injection is performed when injecting charges into the floating gate, as compared to the first embodiment.
[0096]
As shown in FIG. 13, in the MOSFET of this embodiment, the gate electrode 8 and the floating gate 12 are extended to a region away from the surface channel layer 5, and charge is injected into the extended portion. In this region, a tunnel film 16 thinner than the silicon oxide film 7a is provided below the floating gate 12.
[0097]
As described above, by providing the tunnel film 16 in which the silicon oxide film 7a is partially thinned as the writing window, it is possible to easily inject charges from the tunnel film 16 and to define a region where charges are injected. be able to. Further, by defining the place where writing is performed in this way, the amount of writing can be easily controlled, and a large amount of writing can be obtained. Further, in such a configuration, it is not necessary to provide a separate write terminal, so that the apparatus can be simplified and the size can be reduced.
[0098]
In the MOSFET according to the present embodiment, after forming the silicon oxide film 7a in FIG. 6A in the first embodiment, the tunnel film forming region in the silicon oxide film 7a is temporarily removed by etching and then thermally oxidized again. Thus, if the tunnel film 16 is formed, it is manufactured by performing the same process as in the first embodiment.
[0099]
In this embodiment, the silicon oxide film 7a is thinned. However, the silicon oxide film 7b may be thinned depending on the charge injection method.
[0100]
(Sixth embodiment)
FIG. 14 shows a cross-sectional configuration of the MOSFET in the present embodiment. This embodiment defines a region where charge injection is performed when injecting charges into the floating gate, as compared to the first embodiment.
[0101]
As shown in FIG. 14, the MOSFET of the present embodiment forms a write region for injecting charges in addition to the MOS operating region. The writing area is provided in a cross section other than the MOS operating area. For example, if the MOS operating area is formed by laying a plurality of MOSFETs, the writing area is separately provided at a position away from the laid area. Yes.
[0102]
The writing region has a two-layer structure of a floating gate 12a and a gate electrode (control gate) 8a, and is formed with the base regions 3a and 3b.^-Mold layer 3c and this p^-P as a drain for writing formed in the surface layer portion of the mold layer 3c⁺A two-layer structure is formed on the mold layer 17. P⁺A drain electrode 18 is connected to the mold layer 17.
[0103]
Also, the floating gates 12 and 12a in the MOS operating region and the writing region are connected, and the gate electrodes 8 and 8a in the MOS operating region and the writing region are connected (see the dotted line in the figure). ).
[0104]
In such a configuration, the gate electrode 8, the source electrode 10, and the drain electrode 11 are grounded, and a negative potential is applied to the drain electrode 18.
[0105]
As a result, p⁺Charge can be injected into the floating gate 12a from the mold layer 17 side. Thus, the same effect as that of the fourth embodiment can be obtained by the configuration of the present embodiment.
[0106]
The MOSFET in this embodiment is p^-The mold layer 3c is formed at the same time when the base regions 3a and 3b are formed. Although not shown in the drawing, the base regions 3a and 3b are formed on the surface layers of the base regions 3a and 3b in order to make contact with the source electrode 10. P⁺P when forming the contact layer of the mold⁺If the mold layer 17 is formed at the same time, it is manufactured without increasing the number of manufacturing steps compared to the first embodiment. Note that the two-layer gate structure in the writing region is formed simultaneously with the MOS operation region by changing the mask in the photolithography step of the step shown in FIG. 6A, as in the fourth embodiment.
(Seventh embodiment)
FIG. 15 shows a cross-sectional configuration of the MOSFET in this embodiment. In the present embodiment, one embodiment of the present invention is applied to a lateral type MOS transistor.
[0107]
As shown in FIG.^-P on the surface layer of the semiconductor substrate 51^-A mold layer 53 is formed, and n on the surface layer portion of the p-type layer 53⁺A type source region 54a and a drain region 54b are formed apart from each other, and a surface channel layer 55 is formed so as to connect between the source region 54a and the drain region 54b.
[0108]
A floating gate 60 is formed on the surface channel layer 55 via a silicon oxide film 57a as a first insulating film, and further on the floating gate 60 via a silicon oxide film 57b as a second insulating film. Thus, a gate electrode 58 is formed.
[0109]
An interlayer insulating film 59 is formed on the entire surface of the substrate including the gate electrode 58 and the floating gate 60, and the source region 54 a, the drain region 54 b, the gate electrode 58, and the like are formed through the contact holes formed in the interlayer insulating film 59. And p^-A mold layer 53 is connected to each electrode.
[0110]
Also in the MOS transistor configured as described above, the electric field on the surface of the surface channel layer 5 is changed through the floating gate 12 by injecting charges into the floating gate 60 by the same method as in the first embodiment. On-resistance can be reduced, current capability can be improved, and high-speed operation can be achieved.
[0111]
(Other embodiments)
In the above embodiment, the case where the surface channel layer 5 has a higher concentration than in the conventional case has been described. However, even when the surface channel layer 5 is formed with a thicker layer than in the conventional case, the MOSFET performs the same operation as in the above embodiment. Similarly, the on-resistance can be reduced.
[0112]
In the seventh embodiment, an example in which a lateral MOS transistor adopts the same structure as that of the first embodiment is shown. However, the same structure as that of the second to sixth embodiments can also be adopted. .
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a vertical power MOSFET according to a first embodiment of the present invention.
FIG. 2 is a diagram showing the relationship between the gate potential and the floating gate potential before and after the charge is injected into the floating gate 12;
FIG. 3 is a diagram showing a relationship between a gate potential, a floating gate potential, and a drain current.
4 is a diagram showing a manufacturing process of the vertical power MOSFET shown in FIG. 1; FIG.
5 is a diagram showing the manufacturing process of the vertical power MOSFET subsequent to FIG. 4. FIG.
6 is a diagram showing the manufacturing process of the vertical power MOSFET subsequent to FIG. 5. FIG.
FIG. 7 is a diagram showing a method for injecting a MOSFET charge in the first embodiment.
FIG. 8 is a cross-sectional view of a MOSFET according to a second embodiment of the present invention.
FIG. 9 is a cross-sectional view of a MOSFET in a third embodiment of the present invention.
FIG. 10 is a diagram illustrating a method for injecting a MOSFET charge according to a third embodiment.
FIG. 11 is a cross-sectional view of a MOSFET in a fourth embodiment of the present invention.
FIG. 12 is a diagram showing a method for injecting a MOSFET charge according to the fourth embodiment.
FIG. 13 is a cross-sectional view of a MOSFET in a fifth embodiment of the present invention.
FIG. 14 is a cross-sectional view of a MOSFET according to a sixth embodiment of the present invention.
FIG. 15 is a cross-sectional view of a MOSFET in a seventh embodiment of the invention.
FIG. 16 is a cross-sectional view of a conventional MOSFET.
17 is a diagram showing the relationship between the gate potential and drain current of a MOSFET having a surface channel layer 5. FIG.
[Explanation of symbols]
1 ... n⁺Mold substrate, 2 ... n^-Type epitaxial layer,
3a, 3b ... p^-Mold base region, 4a, 4b ... n⁺Type source area,
5 ... surface channel layer (n^-Type SiC layer), 7 ... gate insulating film, 8 ... gate electrode,
9 ... Insulating film, 10 ... Source electrode, 11 ... Drain electrode layer,
12 ... Floating gate.

Claims (6)

A first conductivity type semiconductor substrate (1) having a main surface and a back surface opposite to the main surface and made of silicon carbide;
A first conductivity type semiconductor layer (2) made of silicon carbide formed on the main surface of the semiconductor substrate and having a higher resistance than the semiconductor substrate;
A second conductivity type base region (3a, 3b) formed in a predetermined region of the surface layer portion of the semiconductor layer and having a predetermined depth;
A first conductivity type source region (4a, 4b) formed in a predetermined region of a surface layer portion of the base region and shallower than a depth of the base region;
A first conductivity type surface channel layer (5) made of silicon carbide, which is formed so as to connect the source region and the semiconductor layer at the surface portion of the base region and the surface portion of the semiconductor layer, and forms a channel region. When,
A gate insulating film (7a, 7b) formed on the surface of the surface channel layer;
A gate electrode (8) formed on the gate insulating film;
A source electrode (10) formed in contact with the base region and the source region;
A drain electrode (11) formed on the back surface of the semiconductor substrate;
The gate insulating film includes a first gate insulating film (7a, 57a) and a second gate insulating film (7b, 57b), and the first and second gate insulating films are formed. A conductive floating gate (12, 60) is disposed between them, and by holding the charge in the floating gate, a mechanism is formed that can hold the charge between the gate electrode and the surface channel layer ,
The semiconductor substrate has a MOS operation region that performs the MOS operation by forming the channel region, and a writing region provided at a position different from the MOS operation region,
The floating gate extends from the MOS operation region to the write region, and the charge is injected into the write region,
Furthermore, the writing area includes
A write gate formed on the floating gate and not electrically connected to the gate electrode in the MOS operation region;
A write terminal connected to the write gate, and
The surface channel layer is capable of electrical conduction between the source electrode and the drain electrode even when no voltage is applied to the gate electrode in a state where no charge is held in the mechanism capable of holding the charge. It is in silicon carbide semiconductor device, characterized in that are. A semiconductor substrate (51) having a main surface and a back surface opposite to the main surface and made of silicon carbide;
A second conductivity type well region (53) formed in a predetermined region of the surface layer portion of the semiconductor substrate and having a predetermined depth;
A first conductivity type source region (54a) and a drain region (54b) formed in a predetermined region of a surface layer portion of the well region and shallower than a depth of the well region;
A surface channel layer (55) of the first conductivity type made of silicon carbide forming a channel region, which is formed so as to connect the source region (54a) and the drain region (54b) at the surface portion of the well region. When,
A gate insulating film (57a, 57b) formed on the surface of the surface channel layer; and a gate electrode (58) formed on the gate insulating film;
A source electrode formed in the source region (54a);
A drain electrode formed in the drain region;
A substrate electrode formed in the well region,
The gate insulating film includes a first gate insulating film (7a, 57a) and a second gate insulating film ( 7b, 57b). The first and second gate insulating films A conductive floating gate (12, 60) is disposed between the gate electrodes, and a mechanism for holding charges between the gate electrode and the surface channel layer by holding the charges in the floating gate is configured. ,
The semiconductor substrate has a MOS operation region that performs the MOS operation by forming the channel region, and a writing region provided at a position different from the MOS operation region,
The floating gate extends from the MOS operation region to the write region, and the charge is injected into the write region,
Furthermore, the writing area includes
A write gate formed on the floating gate and not electrically connected to the gate electrode in the MOS operation region;
A write terminal connected to the write gate, and
The surface channel layer is capable of electrical conduction between the source electrode and the drain electrode even when no voltage is applied to the gate electrode in a state where no charge is held in the mechanism capable of holding the charge. It is in silicon carbide semiconductor device, characterized in that are. The said gate insulating film is comprised with the composite film of the silicon oxide film and the silicon nitride film, The said electric charge can be hold | maintained at the interface of this silicon oxide film and a silicon nitride film, The said claim 1 characterized by the above-mentioned. Or the silicon carbide semiconductor device of 2. In the writing area,
The gate electrode extending from the MOS operating region to the writing region;
Wherein formed on the surface portion of the semiconductor substrate, and the gate electrode and the floating gate source over scan and write drain arranged on either side of the said writing area,
The silicon carbide semiconductor device according to any one of claims 1 to 3, characterized in that the write terminal connected before Symbol drain for writing, are provided. In the write region, the gate electrode extending from the MOS operation region to the write region and a second region not electrically connected to the base region or the well region disposed below the floating gate conductivity type and write for the drain of the silicon carbide semiconductor device according to any one of claims 1 to 4, characterized in that the write terminal connected to the write drain, is provided. In the writing area, the silicon carbide semiconductor according to any one of claims 1 to 5, characterized in that said first gate insulating film or the second gate insulating film is partially thinned apparatus.

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