JP2004111772A - Insulated gate field effect semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an insulated gate field effect semiconductor device, wherein contact can be surely made even if a mask is misaligned when contact is made with a source electrode. <P>SOLUTION: Source deformed regions 15a formed by protruding a source region 15 partially toward a body contact region 14 are provided. Even if contact gets out position due to the misalignment of the mask, contact can be surely made with the protruding source deformed regions 15a. The source deformed regions 15a may be partially provided at a regular interval, so that the source deformed regions 15a can be provided without decreasing the body contact region in area so much. The insulated gate field effect semiconductor device can be prevented from increasing its ON-resistance and from decreasing its avalanche resistance. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an insulated gate type field effect semiconductor device, and more particularly to an insulated gate type field effect semiconductor device which improves contact failure of a source region.
[0002]
[Prior art]
In an insulated gate field effect semiconductor device in which a gate electrode is buried in a trench having a stripe structure, a source region is also formed with a uniform width along the trench (for example, see Patent Document 1).
[0003]
Referring to FIG. 7, a trench power MOSFET is shown as an example of a conventional insulated gate field effect semiconductor device.
[0004]
FIG. 7A is a top view of the MOSFET. Note that an interlayer insulating film and a source electrode are omitted.
[0005]
The trench 7 is provided in a stripe shape on the semiconductor substrate, and the inner wall is covered with the gate oxide film 11. The gate electrode 13 is formed by burying polysilicon in the trench 7 and introducing impurities to reduce the resistance. The source region 15 is provided with a uniform width along the trench 7. The body contact region 14 is provided on the surface of the substrate between adjacent source regions 15 for stabilizing the potential of the substrate. Since trench 7 has a stripe shape, source region 15 and body contact region 14 each have a stripe shape having a uniform width. In this case, the unit cell is a region indicated by a broken line, and the source region 15 is continuous between a plurality of cells.
[0006]
FIG. 7B shows a cross-sectional structure of a conventional power MOSFET having a trench structure by taking an N-channel type as an example.
[0007]
A drain region 2 made of an N ⁻ type epitaxial layer is provided on an N ⁺ type silicon semiconductor substrate 1, and a P type channel layer 4 is provided on the surface thereof. A trench 7 penetrating through the channel layer 4 and reaching the drain region 2 is provided, an inner wall of the trench 7 is coated with a gate oxide film 11, and a gate electrode 13 made of polysilicon filled in the trench 7 is provided.
[0008]
An N ⁺ type source region 15 is formed on the surface of the channel layer 4 adjacent to the trench 7, and a P ⁺ type body contact region 14 is provided on the surface of the channel layer 4 between the source regions 15 of two adjacent cells. When a gate voltage is applied to the gate electrode 13, a channel region (not shown) is formed in the channel layer 4 from the source region 15 along the trench 7.
[0009]
The gate electrode 13 is covered with an interlayer insulating film 16, and a source electrode 17 that contacts the source region 15 and the body contact region 14 is provided.
[0010]
[Patent Document 1]
U.S. Pat. No. 6,060,747 FIG. 1
[0011]
[Problems to be solved by the invention]
For example, in a MOSFET for a DC-DC converter having a large chip size, the trench 7 and the gate electrode 13 are provided in a stripe shape as shown in FIG. In this structure, since the area of the gate oxide film 11 per unit cell area can be reduced as compared with the structure in which the trenches 7 are provided in a lattice shape, the parasitic capacitance between the gate and the drain can be reduced. That is, even if the chip size is large, no charge is accumulated at the time of switching, and the switching speed can be improved. Therefore, it is generally adopted for a switching element having a large chip size.
[0012]
FIG. 8 is an enlarged view of a portion of a pair of adjacent source regions 15 in FIG. In this conventional structure, the source region 15 is also formed with a stripe-shaped mask from the gate insulating film 11 because the source region 15 is formed adjacent to the trench 7 with a stripe-shaped mask.
[0013]
Also, if the resistance under the body contact region 14 is high, the current distribution becomes non-uniform at the time of turn-off. For this reason, current concentration occurs in the cell whose turn-off is delayed, resulting in avalanche breakdown in which the cell is destroyed by the operation of the parasitic bipolar transistor. For this reason, the body contact region 14 must be provided with a certain width, and the concentration of impurities must be increased to ensure avalanche resistance. For example, it is known that when the body contact region 14 is smaller than 0.4 μm, the avalanche withstand capability is rapidly deteriorated, and the current rule is designed to be at least 0.6 μm. On the other hand, the miniaturization of cells is in the direction of progress in order to reduce the on-resistance, and the area of the source region 15 is inevitably narrow in order to reduce the cell pitch, that is, the distance between the trenches 7.
[0014]
In this conventional structure, the source electrode 17 opens a contact C indicated by a broken line in the interlayer insulating film 16 and makes contact with the source region 15 and the body contact region 14 (FIG. 8A). Since the source region 15 is provided with a narrow width as described above, if the opening of the contact C is shifted to the left or right on the drawing sheet as shown in FIG. 8B due to misalignment of the mask (FIG. 8B), the contact with the source region 15 is lost. Thus, the region where the MOSFET is turned on is reduced. For this reason, there is a problem that the on-resistance of the device cannot be reduced.
[0015]
In addition, there is a problem that the source region 15 not contacted has a floating potential and stable characteristics cannot be obtained.
[0016]
[Means for Solving the Problems]
The present invention has been made in view of the above problems, and firstly, a drain region provided on a semiconductor substrate, a plurality of stripe-shaped trenches provided on the substrate surface, a gate insulating film provided on the trench surface, and the trench In an insulated gate type field effect semiconductor device having a gate electrode embedded in a trench and a source region provided on the substrate surface adjacent to the trench, a part of the source region formed along the trench is deformed. This problem can be solved by providing a source deformed region.
[0017]
Second, a drain region provided in a semiconductor substrate, a plurality of stripe-shaped trenches provided on the substrate surface, a gate insulating film provided on the trench surface, a gate electrode embedded in the trench, A source region provided adjacent to the substrate surface and a body contact region provided on the substrate surface between the adjacent source regions, wherein a part of the source region is This problem is solved by providing a source deformation region protruding in the body contact region direction.
[0018]
3. The insulated gate field effect semiconductor device according to claim 1, wherein said source deformation region is provided on both sides of said gate electrode.
[0019]
Further, the source deformation regions located on both sides of the gate electrode are alternately arranged in the major axis direction of the trench.
[0020]
The source deformation regions located on both sides of the gate electrode are arranged symmetrically with respect to the gate electrode.
[0021]
Further, a plurality of the source deformation regions are arranged in one of the source regions, and the plurality of the source deformation regions are spaced at equal intervals in a major axis direction of the trench.
[0022]
BEST MODE FOR CARRYING OUT THE INVENTION
An embodiment of the present invention will be described in detail with reference to FIGS. 1 to 6 taking an N-channel trench MOSFET as an example.
[0023]
FIG. 1 shows a top view of a MOSFET according to a first embodiment of the present invention. Note that the interlayer insulating film and the source electrode are omitted, and the same components as those in FIGS. 7 and 8 are denoted by the same reference numerals.
[0024]
The MOSFET of the present invention includes a drain region 2, a trench 7, a gate insulating film 11, a gate electrode 13, a source region 15, a source deformation region 15a, and a body contact region 14 provided on a semiconductor substrate 1. Is done.
[0025]
As shown in FIG. 1, the trench 7 is provided in the semiconductor substrate 1 in a stripe shape, and the inner wall is covered with the gate oxide film 11. The gate electrode 13 is formed by burying polysilicon in the trench 7 and introducing impurities to reduce the resistance.
[0026]
The source region 15 is provided along the trench 7 and has a source deformation region 15a.
[0027]
Body contact region 14 is provided on the surface of substrate 1 between adjacent source regions 15 for stabilizing the potential of the substrate. In this case, the unit cell 38 is a region indicated by a square, and the source region 15 is continuous between a plurality of cells. A large number of these cells 38 are arranged to form the MOSFET operation region 30.
[0028]
2A and 2B are enlarged views of the source region 15.
[0029]
The source deformation region 15a is a region in which a part of the stripe-shaped source region 15 provided along the trench 7 is protruded in the body contact region 14 direction.
[0030]
In order to secure a contact when a mask misalignment occurs in the left-right direction on the paper, the projection is made to protrude to both sides across the gate electrode.
[0031]
As described above, the width of the source region 15 is reduced to the limit in a semiconductor device that is becoming thinner. In the step of opening the contact C with the source electrode 17, the misalignment of the mask in the vertical direction on the paper is not a problem because it is a stripe structure. Since this misalignment extends over the entire chip, contact between the source region 15 on one side of the gate electrode 13 and the source electrode 17 cannot be obtained.
[0032]
Therefore, in the present invention, the body contact region 14 is provided in the source regions 15 on both sides of the gate electrode 13 so that the contact with the source region 15 can be secured even when the mask for opening the contact C is shifted in the horizontal direction of the drawing. Is provided with a source deformation region 15a having a part thereof protruding.
[0033]
In the first embodiment, the source deforming regions 15a between the adjacent gate electrodes 13 are alternately arranged so that their protruding portions are shifted by half a pitch in the unit cell 38, for example, so as to engage with each other in the long axis direction of the trench 7. I do. As shown in FIG. 2A, if the source deformation region 15a is displaced from the center of the gate electrode 13 as long as they are alternately arranged between the adjacent gate electrodes 13, that is, in the body contact region 14. Alternatively, they may be arranged line-symmetrically with respect to the gate electrode 13 as shown in FIG. The narrow width of the source region 15 is the same as the conventional width.
[0034]
Further, in one source region 15 arranged along the trench 7, a plurality of source deformation regions 15 a are arranged, and are separated at equal intervals in the long axis direction of the trench 7. In order not to deteriorate the avalanche resistance, it is preferable to increase the interval as much as possible.
[0035]
Although not shown in FIG. 2, a source electrode 17 is provided on the surface of the substrate 1 via an interlayer insulating film 16. The source electrode 17 is in contact with the source region 15, the source deformation region 15a and the body contact region 14 by a contact C indicated by a dotted line opening the interlayer insulating film 16.
[0036]
FIG. 3 shows an example of an N-channel type cross-sectional structure of the trench-structure power MOSFET of the present invention. FIG. 3A is a cross-sectional view taken along line AA of FIG. 1, and FIG. 3B is a cross-sectional view taken along line BB of FIG.
[0037]
A drain region 2 made of an N ⁻ type epitaxial layer is provided on an N ⁺ type silicon semiconductor substrate 1, and a P type channel layer 4 is provided on the surface thereof. A trench 7 penetrating through the channel layer 4 and reaching the drain region 2 is provided, an inner wall of the trench 7 is coated with a gate oxide film 11, and a gate electrode 13 made of polysilicon filled in the trench 7 is provided.
[0038]
An N ⁺ type source region 15 is formed on the surface of the channel layer 4 adjacent to the trench 7, and a P ⁺ type body contact region 14 is provided on the surface of the channel layer 4 between the adjacent source regions 15. When a gate voltage is applied to the gate electrode 13, a channel region (not shown) is formed in the channel layer 4 from the source region 15 along the trench 7.
[0039]
As described above, the source region 15 has the source deformation region 15 a part of which protrudes into the body contact region 14. Although the body contact region 14 is small in the portion where the source deformation region 15a is provided as shown in FIG. 3A, the portion without the source deformation region 15a has the conventional design dimensions as shown in FIG. 3B.
[0040]
The gate electrode 13 is covered with an interlayer insulating film 16, and a contact C is opened to provide a source electrode 17 that contacts the source region 15, the source deformation region 15 a, and the body contact region 14.
[0041]
The feature of the present invention resides in that a source deformation region 15 a is provided in which a part of the source region 15 is projected from the body contact region 14. In the source region 15 continuous in the stripe structure, a part is deformed in a convex shape in the direction of the body contact region 14 so that even if the contact C is shifted left and right on the paper due to misalignment of the mask when the contact C is opened, the source deformation region is formed. 15a ensures contact with the source electrode 17.
[0042]
If the contact between the source region 15 and the source electrode 17 is ensured, the size of the contact area does not significantly affect the on-resistance of the device. That is, even if misalignment of the mask occurs in the left-right direction on the paper, a contact can be secured in the source deformation region 15a, and a portion that does not turn on can be reduced as much as possible. Also, it is sufficient that the body contact region 14 can be secured as before, as shown in FIG. 3B, so that many portions remain as in the prior art, so that the avalanche resistance can be prevented from deteriorating.
[0043]
Further, by arranging the source deformation regions 15a so as to engage with each other alternately, the source deformation region 15a can be contacted even if the source region 15 cannot be contacted. It becomes easy to secure.
[0044]
Further, by alternately arranging the protrusions by a half pitch in the unit cell 38, adjacent protrusions do not come into contact with each other, and the degree of freedom of the shape of the source deformation region 15a increases.
[0045]
FIG. 4 shows a second embodiment of the present invention.
[0046]
In the second embodiment, the source deformation regions 15a arranged between the adjacent gate electrodes 13 are arranged line-symmetrically between the gate electrodes 13, that is, around the body contact region 14. In FIG. 4, source deformation region 15 a is arranged symmetrically with respect to gate electrode 13, and source deformation region 15 a is arranged symmetrically with respect to body contact region 14. Further, as long as they are arranged line-symmetrically with respect to the body contact region 14, they may not be line-symmetrical with respect to the gate electrode 13 as shown in FIG. Further, similarly to the first embodiment, the source deformation regions 15a are arranged at regular intervals in the major axis direction of the trench 7.
[0047]
In this case, since the positions where the source deformation regions 15a are arranged are the same, it is necessary to form a convex shape having a width smaller than 幅 of the width of the body contact region 14 so that the tip of the protruding portion does not come into contact. . In the present embodiment, since the body contact region 14 increases, the avalanche resistance can be more easily ensured than in the first embodiment.
[0048]
Here, if only a contact defect due to misalignment of the mask in the horizontal direction of the paper is considered, one source deformation region 15a is provided on each side of the gate electrode near the outer periphery of the operation region 30 as shown in FIG. It is sufficient to provide at least four places in the trench. In this case, since the body contact region 15 can secure the same area as the conventional one in most of the operation region 30, deterioration of the avalanche resistance can be further prevented.
[0049]
However, if the arrangement interval of the source deformation regions 15a is too wide, a potential difference is generated between the source region 15 in which a contact failure has occurred and the adjacent body contact region 14, and stable operation may not be performed. In addition, if contact failure due to dust or the like is taken into consideration, there may be cases where improvement cannot be achieved with one or two source deformation regions 15a. Therefore, a structure in which a large number of source deformation regions are provided inside the operation region 30 as shown in FIG. .
[0050]
Naturally, the source deformation region 15a only needs to secure a contact region with the source electrode 17, so that the source deformation region 15a is not limited to the comb-teeth shape shown in FIGS. Any pattern having a convex shape from the region 15 toward the body contact region 14 is effective. Further, one source deformation region 15a is not limited to one protruding portion, and may be composed of a plurality of protruding portions.
[0051]
In these cases, as in the first embodiment, by alternately arranging the source deformation regions 15a by a half pitch in the unit cell, adjacent protrusions do not contact each other, and the shape of the source deformation region 15a is reduced. Degree of freedom increases.
[0052]
Although the embodiment of the present invention has been described with reference to an N-channel MOSFET, similar effects can be obtained with a P-channel MOSFET or an IGBT in which a P-type or N-type substrate is arranged below the drain region of the MOSFET. .
[0053]
【The invention's effect】
A feature of the present invention is that a source deformation region in which a part of a source region protrudes from a body contact region is provided in an insulated gate semiconductor device having a stripe structure.
[0054]
In an insulated gate semiconductor device having a stripe structure, while miniaturization is progressing, a predetermined value must be secured in a body contact region in order to prevent deterioration of avalanche withstand capability. In other words, the source region tends to be miniaturized, and there has been a problem of poor contact with the source electrode due to misalignment of the contact mask.
[0055]
Therefore, in the present invention, by providing a source deformation region in which a part of the source region protrudes from the body contact region, even if contact misalignment occurs due to misalignment of the mask, the contact is secured by the protruding source deformation region. can do.
[0056]
A part of the source deformation region may be projected at regular intervals, and the body contact region has many parts that can be secured as before, so it is possible to secure contact with the source electrode without significantly degrading the avalanche resistance and increase the on-resistance Can be prevented.
[0057]
Further, by arranging the protruding portions of the source deformation region alternately by a half pitch in the unit cell, the adjacent protruding portions do not contact each other, and the degree of freedom of the shape of the source deformation region 15a is increased.
[Brief description of the drawings]
FIG. 1 is a plan view of a semiconductor device of the present invention.
FIG. 2 is a plan view of the semiconductor device of the present invention.
FIG. 3 is a cross-sectional view of the semiconductor device of the present invention.
FIG. 4 is a plan view of the semiconductor device of the present invention.
FIG. 5 is a plan view of the semiconductor device of the present invention.
FIG. 6 is a plan view of the semiconductor device of the present invention.
7A is a plan view and FIG. 7B is a cross-sectional view of a conventional semiconductor device.
FIG. 8 is a plan view of a conventional semiconductor device.

Claims (7)

A drain region provided in the semiconductor substrate, a plurality of stripe-shaped trenches provided on the surface of the substrate, a gate insulating film provided on the surface of the trench, a gate electrode embedded in the trench, An insulated gate field effect semiconductor device comprising: a source region provided on a substrate surface;
An insulated gate field effect semiconductor device, comprising: a source deformation region obtained by partially deforming the source region formed along the trench. A drain region provided in the semiconductor substrate, a plurality of stripe-shaped trenches provided on the surface of the substrate, a gate insulating film provided on the surface of the trench, a gate electrode embedded in the trench, An insulated gate field effect semiconductor device comprising: a source region provided on a substrate surface; and a body contact region provided on the substrate surface between the adjacent source regions.
An insulated gate field effect semiconductor device, comprising: a source deformation region in which a part of the source region protrudes toward the body contact region. 3. The insulated gate field effect semiconductor device according to claim 1, wherein the source deformation region is provided on both sides of the gate electrode. 3. The insulated gate electric field according to claim 1, wherein the source deformation regions arranged between the adjacent gate electrodes are alternately arranged in a longitudinal direction of the trench. Effect semiconductor device. The insulated gate electric field according to claim 1 or 2, wherein the source deformation regions located on both sides of the gate electrode are arranged symmetrically with respect to the gate electrode. Effect semiconductor device. 3. The insulated gate type according to claim 1, wherein the source deformation region disposed between the adjacent gate electrodes is disposed symmetrically with respect to a center between the gate electrodes. 4. Field effect semiconductor device. 3. The insulation according to claim 1, wherein a plurality of the source deformation regions are arranged in one of the source regions, and are separated at equal intervals in a longitudinal direction of the trench. 4. Gate type field effect semiconductor device.

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