JP2018061055A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of suppressing increase in on-resistance, reducing heat generation at a channel, and achieving an excellent active clamp resistance.SOLUTION: A semiconductor device 1 comprises: an epitaxial layer 3 on which a plurality of gate trenches 5 are formed in a stripe shape; gate electrodes 8 buried in the respective gate trenches 5 via a gate insulating film 7; a plurality of unit cells 6 each sectionalized between a pair of gate trenches 5 adjacent to each other; an ntype source region 10, in each unit cell 6, exposed from a surface of the semiconductor layer, and formed so as to be along only one side lateral face of one side gate trench 5 of the pair of gate trenches 5 adjacent to each other, and opposed to the gate electrode 8 while interposing the gate insulating film 7; and a ptype body region 4 formed in a region below the ntype source region 10 in the epitaxial layer 3, and opposed to the gate electrode 8 while interposing the gate insulating film 7.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a semiconductor device having a field effect transistor as a unipolar transistor and having a trench gate structure.

Patent Document 1 discloses a semiconductor substrate including an n ⁻ type drift layer and a p type body layer, and a plurality of grooves formed in a stripe shape so as to reach the n ⁻ type drift layer from the surface of the semiconductor substrate. A gate insulating film formed on the inner peripheral surface of the groove, a gate electrode formed inside the groove via the gate insulating film, and an n formed so as to be in contact with the side surface of the groove on the surface of the p-type body layer ^A trench gate power MOSFET is disclosed that includes a ⁺ type source region.

JP 2010-267677 A

  For example, as shown in FIG. 1 of Patent Document 1, in a structure in which two MOSFETs facing each other with one trench gate (gate electrode) interposed therebetween, heat is applied to both sides of the trench gate as each channel is energized. Occur. Since the heat generated in each channel interacts between the MOSFETs, there is a problem that transient and local heat is generated on both side surfaces of the trench gate. Such heat generation causes a narrowing of the safe operation area of the MOSFET.

In particular, MOSFETs for in-vehicle use require high-accuracy active clamping operation (function to absorb back electromotive force generated by driving a coil by the MOSFET), and therefore excellent active clamping tolerance (withstand of active clamping operation). And an extremely wide safe operating area must be realized.
Such a problem may be reduced by increasing the width of the trench gate and setting a certain distance between the channels facing each other across the trench gate. However, in this case, since the channel width per unit area is shortened, there arises a new problem that the on-resistance of the MOSFET increases.

Accordingly, an object of the present invention is to provide a semiconductor device capable of effectively reducing transient and local heat generation in a channel while suppressing an increase in on-resistance.
Another object of the present invention is to provide a semiconductor device capable of realizing an excellent active clamp tolerance.

  One aspect of the present invention is a semiconductor device including a field effect transistor as a unipolar transistor, and includes a first conductivity type semiconductor layer in which a plurality of gate trenches are formed in a stripe shape, and a gate insulating film interposed therebetween. A gate electrode embedded in the gate trench; a plurality of unit cells each partitioned between a pair of adjacent gate trenches and arranged in stripes; and a surface of the semiconductor layer in each unit cell And is formed so as to be along only one side surface of the gate trench on one side of the pair of gate trenches adjacent to each other in the lateral direction intersecting with the gate trench, and sandwiching the gate insulating film A source region of a first conductivity type facing the gate electrode, and a region below the source region in the semiconductor layer; And a second conductivity type body region that is formed in contact with the source region and faces the gate electrode with the gate insulating film interposed therebetween and forms a channel of the field effect transistor. To do.

  According to this configuration, since the source region is formed only on one side surface of the gate trench, the pitch of the gate trench can be reduced. Thereby, since the channel width per unit area can be secured, an increase in the on-resistance of the field effect transistor can be suppressed.

  In addition, since the source region is formed only on one side surface of the gate trench, it is possible to completely eliminate or reduce the channels facing each other across the gate trench. Thereby, the influence which the heat | fever in the channel of each unit cell has on an adjacent unit cell can be reduced. As a result, transient and local heat generation in the channel can be suppressed. Therefore, since an extremely wide safe operation area required for the active clamp operation can be obtained, an excellent active clamp tolerance can be ensured.

FIG. 1 is a schematic plan view of a semiconductor device according to an embodiment of the present invention. 2 is a cross-sectional view taken along the section line II-II in FIG. FIG. 3 is a graph for explaining the pitch of the gate trench of the semiconductor device. FIG. 4A is a cross-sectional view for explaining an example of the manufacturing process of the semiconductor device. FIG. 4B is a diagram showing a manufacturing process subsequent to FIG. 4A. FIG. 4C is a diagram showing the next manufacturing step after FIG. 4B. FIG. 4D is a diagram showing the next manufacturing step after FIG. 4C. FIG. 4E is a diagram showing the next manufacturing step after FIG. 4D. FIG. 4F is a view showing the next manufacturing step after FIG. 4E. FIG. 5 is a schematic plan view of a semiconductor device of a reference example. FIG. 6 is a schematic plan view of the semiconductor device of the present invention. FIG. 7 is a schematic plan view of a semiconductor device according to another embodiment of the present invention. FIG. 8 is a cross-sectional view taken along section line VIII-VIII in FIG.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a schematic plan view of a semiconductor device 1 according to an embodiment of the present invention. FIG. 2 is a cross-sectional view taken along the section line II-II in FIG.
The semiconductor device 1 includes an n ⁺ type semiconductor substrate 2 and an n ⁻ type epitaxial layer 3 formed on the semiconductor substrate 2. The impurity concentration of the semiconductor substrate 2 is, for example, 5.0 × 10 ¹⁹ cm ^{−3 to} 5.0 × 10 ²¹ cm ⁻³ , and the impurity concentration of the epitaxial layer 3 is, for example, 5.0 × 10 ¹⁴ cm ^{−. 3 to} 2.0 × 10 ¹⁶ cm ⁻³ . Examples of the n-type impurity include P (phosphorus), As (arsenic), and the like.

A p ⁻ type body region 4 is formed on the surface of the epitaxial layer 3. The p ⁻ type body region 4 is formed from the surface of the epitaxial layer 3 to the depth of 1.0 μm to 2.0 μm in the thickness direction. The impurity concentration of p ⁻ type body region 4 is, for example, 5.0 × 10 ¹⁶ cm ^{−3 to} 1.0 × 10 ¹⁸ cm ⁻³ . An example of the p-type impurity is B (boron).

The epitaxial layer 3 includes a plurality of gate trenches 5 formed in a stripe shape in a plan view as viewed from the normal direction of the surface of the epitaxial layer 3 and a stripe-like shape defined by a pair of gate trenches 5 adjacent to each other. A unit cell 6 is formed.
The gate trench 5 is formed by digging down the surface of the epitaxial layer 3 in the thickness direction. The side surface of the gate trench 5 is formed substantially perpendicular to the surface of the epitaxial layer 3. The bottom of the gate trench 5 penetrates the p ⁻ type body region 4 and reaches the epitaxial layer 3, and is formed so as to be rounded from the side surface of the gate trench 5.

As will be described later, the gate trench 5 is preferably formed such that the pitch D between the centers of a pair of adjacent gate trenches 5 is 2.0 μm to 5.0 μm, and the width W of the gate trench 5 is , And preferably 0.2 μm to 0.8 μm.
A gate electrode 8 is embedded in the gate trench 5 via a gate insulating film 7. The gate insulating film 7 is, for example, a silicon oxide film formed by oxidizing the epitaxial layer 3 on the side and bottom of the gate trench 5. The gate electrode 8 is made of, for example, an electrode material containing polysilicon. On the surface of the gate electrode 8, a silicon oxide film 9 having a surface substantially flush with the epitaxial layer 3 is formed.

In the unit cell 6, an n ⁺ type source region 10 and a p ⁺ type body contact region 11 are formed so as to be exposed from the surface of the epitaxial layer 3.
The n ⁺ -type source region 10 is formed only on one side in the lateral direction intersecting the gate trench 5 and is provided with continuity between the adjacent unit cells 6. That is, the n ⁺ -type source region 10 is formed so as to be in contact with one side surface in the lateral direction intersecting the gate trench 5 in all the unit cells 6, and the gate electrode 8 is sandwiched between the gate insulating films 7. Is facing.

The n ⁺ -type source region 10 is drawn from the side surface of the gate trench 5 on one side toward the gate trench 5 on the other side so as to reach the central portion between a pair of adjacent gate trenches 5.
The n ⁺ -type source region 10 is located on the side of one gate trench 5, and has one end facing the gate electrode 8 across the gate insulating film 7 and the other end located on the other gate trench 5 side. (The end on the opposite side of the interface between the gate insulating film 7 and the n ⁺ -type source region 10). The other end portion of the n ⁺ -type source region 10 may be located at the edge portion of the open end of the other gate trench 5. That is, the n ⁺ -type source region 10 may be formed so as to gradually become deeper from the other side end portion toward the one side end portion, starting from the edge portion of the opening end of the gate trench 5.

The other end portion of n ⁺ type source region 10 is formed so as to be selectively covered with p ⁺ type body contact region 11. The bottom of n ⁺ type source region 10 is formed from the surface of epitaxial layer 3 to a depth of 0.2 μm to 1.0 μm in the thickness direction. The impurity concentration of the n ⁺ -type source region 10 is, for example, 1.0 × 10 ¹⁹ cm ^{−3 to} 1.0 × 10 ²¹ cm ⁻³ .

Below the n ⁺ -type source region 10, the p ⁻ -type body region 4 that forms the side surface of the gate trench 5 is the channel region 20. The formation of the channel in the channel region 20 is controlled by the gate electrode 8.
The p ⁺ type body contact region 11 is formed only on the other side in the lateral direction intersecting with the gate trench 5 (the side opposite to the n ⁺ type source region 10). The p ⁺ type body contact region 11 is formed in contact with the side surface of the gate trench 5 and faces the gate electrode 8 with the gate insulating film 7 interposed therebetween.

The end of the p ⁺ type body contact region 11 on the side not facing the gate electrode 8 is formed so as to selectively cover the end of the n ⁺ type source region 10. That is, on the surface portion of the unit cell 6 sandwiched between adjacent gate trenches 5, a linear boundary that divides the unit cell 6 into two in the width direction in a plan view viewed from the normal direction of the surface of the epitaxial layer 3. N ⁺ -type source region 10 and p ⁺ -type body contact region 11 separated by ( ¹⁾ are formed adjacent to each other. These regions 10 and 11 are exposed at the side surfaces of the separate gate trenches 5.

The bottom portion of p ⁺ type body contact region 11 is formed deeper than the bottom portion of n ⁺ type source region 10 and has a depth of 0.4 μm to 2.0 μm from the surface of epitaxial layer 3 in the thickness direction. Is formed. Further, the impurity concentration of the p ⁺ type body contact region 11 is, for example, 1.0 × 10 ¹⁹ cm ^{−3 to} 5.0 × 10 ²⁰ cm ⁻³ .
On the epitaxial layer 3 in the unit cell 6, a source contact 12 connecting the n ⁺ type source region 10 and the p ⁺ type body contact region 11 is formed. The source contact 12 is formed so as to straddle the boundary (stripe-shaped boundary parallel to the gate trench 5) between the n ⁺ -type source region 10 and the p ⁺ -type body contact region 11 with a certain interval. The source contact 12 is formed with a width of 0.6 μm to 4.0 μm, for example. An external wiring (not shown) is connected to the source contact 12. Further, a back surface metal (not shown) is connected to the back surface of the semiconductor substrate 2.

As described above, in the semiconductor device 1, a MOSFET (field effect transistor) as a unipolar transistor is formed only on the side surface of the gate trench 5 on one lateral side intersecting the gate trench 5.
Next, the relationship between the pitch D and width W of the gate trench 5 in the semiconductor device 1 and the active clamp tolerance E will be described with reference to FIG.

FIG. 3 is a graph for explaining the relationship between the semiconductor device 1 and the pitch D of the gate trench 5. FIG. 3 is a graph G ₁ showing the relationship between the pitch D of the gate trench 5 and the on-resistance R _{on of the} MOSFET, and graphs G _{2 to} G showing the relationship between the pitch D of the gate trench 5 and the active clamp tolerance E. ₄ is added.
In FIG. 3, the horizontal axis represents the pitch D of the gate trench 5, the left vertical axis represents 1 / R _on , and the right vertical axis represents the active clamp tolerance E. The graph G ₂ shown in a solid line is a graph of when the width W of the gate trenches 5 is 0.6 .mu.m, the graph G _3, and graph G ₄ shown by a chain line, the width W of the gate trenches 5 0 It is a graph in the case of .8 μm and 0.2 μm.

Referring to the graph G _1, as the value of the pitch D of the gate trench 5 is increased, the value of 1 / R _on is reduced. In other words, the value of the on-resistance R _on of the MOSFET increases as the value of the pitch D of the gate trench 5 increases. Therefore, in order to obtain a good value of the on-resistance R _on , it is preferable that the value of the pitch D of the gate trench 5 is small.
On the other hand, referring to graph G _2, as the value of the pitch D of the gate trench 5 is increased, the value of the active clamp capability E is increasing. Therefore, in order to obtain a good value of the active clamp tolerance E, it is preferable that the value of the pitch D of the gate trench 5 is large.

From these relationships, in order to obtain a good value of the on-resistance R _{on and} a value of the active clamp tolerance E, the pitch D of the gate trench 5 at the point where the graph G ₁ and the graphs G _{2 to} G ₄ intersect can be obtained. I know it ’s good.
The value of the pitch D of the gate trench 5 at a point where the graph _{G 1} and Graph _G 2 ~G ₄ intersect, if _D 1, _{D 2} and _{D 3,} respectively, _{D 1} is 2.0 .mu.m, _{D 2} Was 3.0 μm and D ₃ was 5.0 μm.

In this manner, the pitch D and the width W of the gate trench 5 that can obtain a good value of the active clamp resistance E while suppressing an increase in the value of the on-resistance R _on based on the characteristics of each graph are determined. Can do. However, the trench width (the width W of the gate trench 5) is often determined due to restrictions on processing accuracy.
Next, a manufacturing process of the semiconductor device 1 will be described with reference to FIGS. 4A to 4F. 4A to 4F are cross-sectional views for explaining an example of the manufacturing process of the semiconductor device 1 of the present invention.

In order to manufacture the semiconductor device 1, as shown in FIG. 4A, for example, a semiconductor substrate 2 which is a silicon substrate is prepared. Next, the silicon of the semiconductor substrate 2 is epitaxially grown to form the epitaxial layer 3. Next, an ion implantation mask (not shown) having an opening selectively in a region where p ⁻ type body region 4 is to be formed is formed. Then, p-type impurity ions are implanted through the ion implantation mask. Thereby, p ⁻ type body region 4 is formed on the surface of epitaxial layer 3. After the p ⁻ type body region 4 is formed, the ion implantation mask is removed.

  Next, as shown in FIG. 4B, a hard mask 13 having an opening selectively in a region where the stripe-shaped gate trench 5 is to be formed is formed on the epitaxial layer 3. Then, the epitaxial layer 3 is etched through the hard mask 13. As a result, a plurality of gate trenches 5 formed in a stripe shape and a stripe-shaped unit cell 6 defined by a pair of adjacent gate trenches 5 are formed. After the gate trench 5 is formed, the hard mask 13 is removed.

  Next, as shown in FIG. 4C, the surface of the epitaxial layer 3 including the side surface and the bottom of the gate trench 5 is subjected to a thermal oxidation process to form a gate insulating film 7 containing silicon oxide. Next, the gate trench 5 is refilled, and an electrode material for the gate electrode 8 is deposited so as to cover the epitaxial layer 3 to form an electrode material layer 14. The electrode material layer 14 can be formed by depositing polysilicon by a CVD method, for example.

  Next, as shown in FIG. 4D, unnecessary portions of the electrode material layer 14 and the gate insulating film 7 formed in the region outside the gate trench 5 are removed by, for example, an etching process. At this time, the surface of the gate electrode 8 is etched so as to be located deeper than the surface of the epitaxial layer 3. Thereafter, through a thermal oxidation process, a silicon oxide film 9 having a surface substantially flush with the epitaxial layer 3 is formed on the surface of the gate electrode 8.

Next, as shown in FIG. 4E, an ion implantation mask 15 having an opening selectively in a region where the p ⁺ -type body contact region 11 is to be formed is formed. Then, p type impurity ions are implanted into the epitaxial layer 3 through the ion implantation mask 15 to form the p ⁺ type body contact region 11. After the p ⁺ type body contact region 11 is formed, the ion implantation mask 15 is removed.

Next, as shown in FIG. 4F, an ion implantation mask 16 having an opening selectively in a region where the n ⁺ -type source region 10 is to be formed is formed. Then, n-type impurity ions are implanted into the epitaxial layer 3 through the ion implantation mask 16 to form the n ⁺ -type source region 10. After the n ⁺ type source region 10 is formed, the ion implantation mask 16 is removed.
Next, source contact 12 is formed on epitaxial layer 3 in unit cell 6 so as to straddle the boundary between n ⁺ type source region 10 and p ⁺ type body contact region 11. Next, external wiring and back surface metal (not shown) are connected to the source contact 12 and the back surface of the semiconductor substrate 2. Through the above steps, the semiconductor device 1 shown in FIGS. 1 and 2 is manufactured.

Next, the relationship between the pitch D of the gate trench 5 and the channel width per unit area will be described more specifically with reference to FIGS.
FIG. 5 is a schematic plan view of the semiconductor device 17 of the reference example. FIG. 6 is a schematic plan view of the semiconductor device 1 of the present invention. 5 and 6 are diagrams showing MOSFETs per unit area formed in the semiconductor devices 1 and 17 using circuit symbols.

Referring to FIG. 5, in the semiconductor device 17 of the reference example, five gate trenches 18 are formed per unit area, and opposing channel regions 19 (MOSFETs) are formed with the gate trench 18 interposed therebetween. That is, in the semiconductor device 17 of the reference example, a total of ten channel regions 19 are formed per unit area.
Pitch _{D 5} of the gate trench 18 is, for example, 4.0 .mu.m. The channel width _{W 2} in per one channel region 19 is, for example, 1000 .mu.m. Accordingly, in the semiconductor device 17 of the reference example, since ten channel regions 19 are formed in total, the channel width per unit area is 10000 μm.

  In contrast, in the semiconductor device 1 of the present invention, as shown in FIG. 6, eight gate trenches 5 are formed per unit area, and one side surface of each gate trench 5 (in the unit cell 6). A channel region 20 (MOSFET) is formed on the same side in the horizontal direction. That is, in the semiconductor device 1 of the present invention, a total of eight channel regions 20 are formed per unit area.

According to the semiconductor device 1 of the present invention, unlike the semiconductor device 17 of the reference example, the n ⁺ -type source region 10 may be formed on one side surface of the gate trench 5, and the n side surface on the other side surface of the gate trench 5 is n. since ⁺ is not necessary to form a source region 10, it can be narrowed by an amount pitch D of the gate trench 5 in the area not forming the n ⁺ -type source region 10.
Thereby, the pitch D of the gate trench 5 in the semiconductor device 1 can be set to, for example, 2.5 μm, which is about 60% of the pitch D ₅ of the gate trench 18 in the semiconductor device 17 of the reference example. The number of the gate trenches 5 can be increased to eight, which is larger than that of the semiconductor device 17 of the reference example. The channel width W ₃ per channel region 20 is 1000 μm, like the semiconductor device 17 of the reference example. Therefore, since a total of eight channel regions 20 are formed in the semiconductor device 1 of the present invention, the channel width per unit area is about 80% of the channel width of the gate trench 18 in the semiconductor device 17 of the reference example. It becomes a certain 8000 μm.

  As described above, according to the semiconductor device 1, the channel region 20 is formed only on one side in the lateral direction intersecting with the gate trench 5, and therefore, unlike the semiconductor device 17 of the reference example, The channel region 20 (MOSFET) to be formed is not formed. Thereby, it can suppress effectively that the heat_generation | fever in the channel area | region 20 of each unit cell 6 influences the adjacent unit cell 6. FIG. As a result, transient and local heat generation on one side surface and the other side surface of the gate trench 5 can be effectively suppressed.

  Further, according to the configuration of the semiconductor device 1, the channel width per unit area is about 80% as compared with the configuration of the semiconductor device 17 of the reference example, but the heat generation in the channel region 20 of each unit cell 6 is adjacent. Therefore, the active clamp tolerance E can be improved to about 2 to 5 times that of the semiconductor device 17 of the reference example. As a result, it is possible to obtain an extremely wide safe operation region required for the active clamp operation, and thus it is possible to ensure an excellent active clamp tolerance E.

Further, according to the configuration of the semiconductor device 1, since the channel region 20 can be formed by providing the n ⁺ type source region 10 in all the unit cells 6, it is possible to effectively utilize the limited MOSFET formation region. it can. As a result, the channel width per unit area can be effectively increased, and an increase in the on-resistance R _on of the MOSFET can be effectively suppressed.
Furthermore, by setting the width W of the gate trench 5 to 0.2 μm to 0.8 μm, the parasitic capacitance at the bottom of the gate trench 5 is increased as compared with the case where the trench width is simply expanded to increase the active clamp tolerance. Can also be effectively suppressed.

Next, a semiconductor device 21 according to another embodiment of the present invention will be described with reference to FIGS.
FIG. 7 is a schematic plan view of a semiconductor device 21 according to another embodiment of the present invention. FIG. 8 is a cross-sectional view taken along section line VIII-VIII in FIG. 7 and 8, parts corresponding to those shown in FIGS. 1 and 2 described above are denoted by the same reference numerals, and description thereof is omitted.

In the unit cell 6 of the semiconductor device 21, an n ⁺ type source region 22 and a p ⁺ type body contact region 23 are formed so as to be exposed from the surface of the epitaxial layer 3.
The n ⁺ type source region 22 is formed along a lateral direction in which a part of the boundary with the p ⁺ type body contact region 23 intersects with the gate trench 5 in a plan view of the surface of the epitaxial layer 3 viewed from the normal direction. As shown, the region 24 protruding in the lateral direction is selectively provided.

In other words, the p ⁺ -type body contact region 23 protrudes from the n ⁺ -type source region 22 so that a part of the boundary with the n ⁺ -type source region 22 is formed along the lateral direction intersecting the gate trench 5. A region 26 protruding in the lateral direction opposite to the region 24 is provided. The protruding region 24 of the n ⁺ -type source region 22 and the protruding region 26 of the p ⁺ -type body contact region 23 are formed so as to be sandwiched between each other.

The protruding region 26 of the p ⁺ -type body contact region 23 is formed longer than the protruding region 24 of the n ⁺ -type source region 22 in the direction orthogonal to the lateral direction.
On the epitaxial layer 3 in the unit cell 6, a source contact 25 that connects the n ⁺ type source region 22 and the p ⁺ type body contact region 23 is formed.
The source contact 25 is formed so as to cover the protruding region 24 of the n ⁺ -type source region 22 and straddle the protruding region 26 of the adjacent p ⁺ -type body contact regions 23. The source contact 25 is formed narrower than the source contact 12 of the semiconductor device 1 according to the above-described embodiment. The width of the source contact 25 is, for example, 0.15 μm to 0.6 μm.

Since other configurations are the same as the configuration of the semiconductor device 1 according to the above-described embodiment, the description thereof is omitted.
As described above, according to another embodiment of the present invention, the source contact 25 is biased toward the n ⁺ type source region 22 side or the p ⁺ type body contact region 23 side during the manufacturing process of the semiconductor device 21. The source contact 25 may be formed so as to cover the protruding region of the n ⁺ -type source region 22 and straddle the p ⁺ -type body contact region 23 even if a lateral misalignment such as the above occurs. it can. As a result, it is possible to provide the semiconductor device 21 that can ensure good connection between the n ⁺ -type source region 22 and the p ⁺ -type body contact region 23.

The semiconductor device 21 can be packed more gate pitch than that of the semiconductor device 1, which is useful if you want to adjust the direction of reducing R _on.
As mentioned above, although embodiment of this invention was described, this invention can also be implemented with another form.
For example, in one embodiment and other embodiments described above, although the p ⁺ -type body contact region 11, 23 has been described formed configuration so as to be adjacent to the n ⁺ -type source regions 10, 22, p ⁺ -type body A configuration in which the contact regions 11 and 23 are not formed may be employed. Even in such a configuration, the p ⁻ type body region 4 that forms the side surface of the gate trench 5 below the n ⁺ type source regions 10 and 22 becomes the channel region 20, so The channel region 20 (MOSFET) can be formed only on the side surface.

Incidentally, in this case, the end portion on the side not facing the gate electrode 8 of the n ⁺ -type source regions 10 and 22 (i.e., the interface between opposite end portions of the gate insulating film 7 and the n ⁺ -type source regions 10 and 22 ) May be located at the edge portion of the open end of the adjacent gate trench 5. That is, the n ⁺ -type source regions 10 and 22 may be formed so as to gradually become deeper from the edge portion of the opening end toward the side facing the gate electrode 8. Further, under such a configuration, p ⁺ type body contact regions 11 and 23 may be formed so as to be in contact with n ⁺ type source regions 10 and 22.

In the above-described embodiment and other embodiments, the ends of the n ⁺ type source regions 10 and 22 opposite to the side facing the gate electrode 8 are covered with the p ⁺ type body contact regions 11 and 23. However, the end portions of the n ⁺ type source regions 10 and 22 may be formed in contact with the p ⁺ type body contact regions 11 and 23. Further, the n ⁺ type source regions 10 and 22 and the p ⁺ type body contact regions 11 and 23 may be formed with the same depth.

In the above-described one embodiment and other embodiments, the striped gate trenches 5 are formed at substantially equal intervals when the pitch D of the gate trenches 5 is in the range of 2.0 μm to 5.0 μm. Also good. In this case, the channel width per unit area can be adjusted more accurately.
In the above-described embodiment and other embodiments, the configuration in which the bottom of the gate trench 5 is formed to be rounded from the side surface has been described. However, the bottom of the gate trench 5 is parallel to the surface of the epitaxial layer 3. The structure formed so that it may become.

In the above-described embodiment and other embodiments, the gate trench 5 having a side surface substantially perpendicular to the surface of the epitaxial layer 3 has been described. However, the opening width increases from the surface of the epitaxial layer 3 in the thickness direction. A taper type gate trench that gradually narrows may be formed.
In the above-described embodiment and other embodiments, the configuration in which the n ⁺ type semiconductor substrate 2 is formed has been described. However, the configuration in which the p ⁺ type semiconductor substrate 2 in which the conductivity type is inverted is formed. It may be. In this case, the conductivity type of other impurity regions is inverted.

In addition, various design changes can be made within the scope of matters described in the claims. Examples of features extracted from this specification and drawings are shown below.
[Item 1] A semiconductor device including a field effect transistor as a unipolar transistor, wherein a first conductive type semiconductor layer in which a plurality of gate trenches are formed in a stripe shape, and the gate trench via a gate insulating film A plurality of unit cells, which are partitioned between a pair of gate trenches adjacent to each other, and arranged in a stripe shape, and are exposed from the surface of the semiconductor layer in each of the unit cells; The gate insulating film is formed along only one side surface of the gate trench on one side of the pair of gate trenches adjacent to each other in the lateral direction intersecting the gate trench, and the gate insulating film in the gate trench on one side A source region of a first conductivity type facing the gate electrode across the substrate, and a front region in the semiconductor layer In the region below the source region is formed in contact with the source region, and a second conductivity type body region facing the gate electrode across the gate insulating film, the semiconductor device.

  According to this configuration, it is possible to completely eliminate or reduce the channels facing each other across the gate trench. Further, since the pitch of the gate trench, that is, the width of the unit cell is 2 μm to 5 μm, the influence of heat in the channel of each unit cell on the adjacent unit cell is relatively small. Therefore, transient and local heat generation in the channel can be suppressed. As a result, it is possible to obtain an extremely wide safe operation region required for the active clamp operation, and thus it is possible to ensure an excellent active clamp tolerance.

  Furthermore, according to this configuration, unlike the configuration of the conventional semiconductor device, it is not necessary to form source regions on both side surfaces of the gate trench, and the source region may be formed only on one side in the lateral direction intersecting the gate trench. . As a result, the pitch of the gate trenches can be reduced, so that the channel width per unit area can be ensured. As a result, an increase in the on-resistance of the MOSFET can be suppressed.

  Further, according to this configuration, even if a lateral alignment shift occurs such that the source contact is biased toward the source region side or the body region side during the manufacturing process of the semiconductor device, the source contact It can be formed so as to cover the protruding region and to straddle the body contact region. As a result, it is possible to provide a semiconductor device that can ensure good connection between the source region and the body contact region.

Note that the end of the source region that does not face the gate electrode (that is, the end opposite to the interface between the gate insulating film and the source region) is located at the edge of the opening end of the adjacent gate trench. Also good. That is, the source region may be formed so as to gradually deepen from the edge portion of the opening end toward the side facing the gate electrode.
According to this configuration, since no opposing channel is formed across the gate trench, transient and local heat generation in the channel can be effectively suppressed.

[Item 2] The semiconductor device according to Item 1, wherein the source region is provided with continuity between adjacent unit cells.
As a means for suppressing transient and local heat generation in the channel, in addition to the method of increasing the width of the gate trench as described above, for example, a method of forming source regions every other unit cell in a stripe shape is considered. It is done. That is, by completely decimating the source region from the selected unit cell, a channel is not formed in the unit cell, thereby eliminating the opposing channel region across the gate trench.

However, in this method, every other unit cell in which no channel is formed is present, and it cannot be said that the limited MOSFET formation region can be effectively utilized. In other respects, it is the same as simply increasing the width of the gate trench by one unit cell, and as a result, the same problem of increasing on-resistance as the method of increasing the width of the gate trench occurs. .
On the other hand, in the semiconductor device according to item 2, since transient and local heat generation in the channel can be suppressed, the source region can be provided with continuity in all unit cells. Thereby, since a channel can be formed in all the unit cells, the limited MOSFET formation region can be effectively utilized. As a result, the channel width per unit area can be effectively increased, and an increase in on-resistance of the MOSFET can be effectively suppressed.

[Item 3] The semiconductor device according to Item 1 or 2, wherein a width of the gate trench is 0.2 μm to 0.8 μm.
According to this configuration, an increase in the parasitic capacitance of the gate trench can be effectively suppressed.

DESCRIPTION OF SYMBOLS 1 Semiconductor device 3 Epitaxial layer 4 p ^- type body region 5 Gate trench 6 Unit cell 7 Gate insulating film 8 Gate electrode 10 n ⁺ type source region 11 p ⁺ type body contact region 12 Source contact 20 Channel region 21 Semiconductor device 22 n ⁺ Type source region 23 p ⁺ type body contact region 24 protruding region 25 source contact

Claims (10)

A semiconductor device including a field effect transistor as a unipolar transistor,
A semiconductor layer of a first conductivity type in which a plurality of gate trenches are formed in stripes;
A gate electrode embedded in each of the gate trenches via a gate insulating film;
A plurality of unit cells, each partitioned between a pair of adjacent gate trenches and arranged in a stripe pattern;
In each unit cell, it is exposed from the surface of the semiconductor layer and extends along only one side surface of the gate trench on one side of the pair of gate trenches adjacent to each other in the lateral direction intersecting the gate trench. A first conductivity type source region facing the gate electrode with the gate insulating film interposed therebetween,
A second conductivity type formed in a region below the source region in the semiconductor layer so as to be in contact with the source region, facing the gate electrode with the gate insulating film interposed therebetween, and forming a channel of the field effect transistor; A semiconductor device including a body region.   The source region is drawn from a side surface of the gate trench on one side toward the gate trench on the other side so as to reach a central portion between a pair of adjacent gate trenches. The semiconductor device described.   The semiconductor device according to claim 1, wherein the source region is provided with continuity between adjacent unit cells.   In each of the unit cells, it is exposed from the surface of the semiconductor layer, adjacent to the source region, and only on the other side surface of the gate trench on the other side of the pair of gate trenches adjacent to each other in the lateral direction. 4. The device according to claim 1, further comprising a second-conductivity-type body contact region that is formed along the other side and faces the gate electrode across the gate insulating film in the gate trench on the other side. Semiconductor device.   5. The semiconductor device according to claim 4, wherein the body region is formed in contact with the source region and the body contact region in a region below the source region and the body contact region in the semiconductor layer.   The source region protrudes in the lateral direction so that a part of the boundary with the body contact region is formed along the lateral direction in a plan view as viewed from the normal direction of the surface of the semiconductor layer. The semiconductor device according to claim 5, which selectively has a protruding region.   The boundary between the projecting region and the body contact region is formed on the semiconductor layer so as to cross a portion along the lateral direction and straddle the projecting region and the body contact region. The semiconductor device according to claim 6, further comprising a source contact connected to the body contact region.   The semiconductor device according to claim 7, wherein the source contact extends along a stripe direction of the unit cell so as to cross the protruding region of the source region.   The semiconductor device according to claim 1, wherein the plurality of gate trenches are formed in a stripe shape having a pitch of 2 μm to 5 μm.   The width | variety of the said gate trench is a semiconductor device as described in any one of Claims 1-9 which are 0.2 micrometer-0.8 micrometer.

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