JPS6355976A - Field effect semiconductor device - Google Patents
Field effect semiconductor deviceInfo
- Publication number
- JPS6355976A JPS6355976A JP61199745A JP19974586A JPS6355976A JP S6355976 A JPS6355976 A JP S6355976A JP 61199745 A JP61199745 A JP 61199745A JP 19974586 A JP19974586 A JP 19974586A JP S6355976 A JPS6355976 A JP S6355976A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- field effect
- electrode
- source electrode
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 230000005669 field effect Effects 0.000 title claims description 21
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 239000004020 conductor Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】 〔技術分野〕 この発明は電界効果半導体装置に関する。[Detailed description of the invention] 〔Technical field〕 The present invention relates to a field effect semiconductor device.
電界効果半導体装置のひとつに絶縁ゲート型電界効果ト
ランジスタがある。絶縁ゲート型電界効果トランジスタ
は、縦型構造のものが開発されてからは電力制御用等い
わゆるパワー用としての用途が拓けてきた。第２図は、
縦型構造の絶縁ゲート型電界効果トランジスタの断面構
造をあられしたものである。縦型構造の絶縁ゲート型電
界効果トランジスタ２１は、半導体基板２２の裏面にド
レイン電極２６を備えていて、表面にソース電極２７．
２７とゲート電極２８．２８を備えている、ゲート電極
２８は絶縁層３０の上に形成されている。チャンネルは
ゲート電極２８下の２層２５ ・の表面部ＣＨに形
成される。An insulated gate field effect transistor is one type of field effect semiconductor device. Since the development of insulated gate field effect transistors with a vertical structure, applications for so-called power applications such as power control have been expanded. Figure 2 shows
This is a cross-sectional view of a vertical insulated gate field effect transistor. The insulated gate field effect transistor 21 having a vertical structure includes a drain electrode 26 on the back surface of a semiconductor substrate 22, and a source electrode 27 on the front surface.
A gate electrode 28 is formed on the insulating layer 30, comprising a gate electrode 27 and a gate electrode 28.28. The channel is formed in the surface portion CH of the two layers 25.sub.2 under the gate electrode 28.
ただ、絶縁ゲート型電界効果トランジスタ２１は、他の
電力制御素子と比べると、導通状態の素子における順方
向電圧降が大きい（つまりオン抵抗が大きい）傾向にあ
る。絶縁ゲート型電界効果トランジスダ２１が導通状態
にあるとき、電流は、ドレイン電極２７から入りＮ層２
３内を２点矢印で示すように縦向きに流れ、表面付近で
横向きに流れを変えチャンネルを通ってドレイン電極２
６に達する。この場合、基板表面付近におけるＮ層（ド
レイン領域）２３で電流の集中化が起こる、つまり、ド
レイン領域が有効に導体として作用しきれないのである
。そのため、どうしても、オン抵抗が大きくなるのであ
る。オン抵抗が大きいと素子容量が小さくなるため、利
用範囲が制限されるなどの不都合がある。However, compared to other power control elements, the insulated gate field effect transistor 21 tends to have a large forward voltage drop (that is, a large on-resistance) in a conductive element. When the insulated gate field effect transistor 21 is in a conductive state, current enters from the drain electrode 27 and flows through the N layer 2.
3 flows vertically as shown by the two-pointed arrow, then changes horizontally near the surface and flows through the channel to the drain electrode 2.
Reach 6. In this case, current concentration occurs in the N layer (drain region) 23 near the substrate surface, that is, the drain region cannot function effectively as a conductor. Therefore, the on-resistance inevitably increases. If the on-resistance is large, the element capacitance becomes small, resulting in disadvantages such as a limited range of use.
上記の事情に鑑み、この発明は、ドレイン領域が有効に
作用しオン抵抗が小さく、大電流制御に適した電界効果
半導体装置を提供することを目的とする。In view of the above circumstances, it is an object of the present invention to provide a field effect semiconductor device in which the drain region functions effectively, has low on-resistance, and is suitable for large current control.
前記目的を達成するため、この発明は、半導体基板の一
側にドレイン電極を備えているとともに他側にソース電
極と絶縁ゲート電極を備えていて、前記基板の他側表面
に形成された逆導電型領域表面にチャンネルが形成され
るようになっている電界効果半導体装置において、前記
逆導電型領域の外側における前記他側表面に別のソース
電極を備えていることを特徴とする電界効果半導体装置
を要旨とする。To achieve the above object, the present invention includes a semiconductor substrate having a drain electrode on one side, a source electrode and an insulated gate electrode on the other side, and a reverse conductive electrode formed on the other side surface of the substrate. A field effect semiconductor device in which a channel is formed on the surface of a type region, characterized in that another source electrode is provided on the other side surface outside the opposite conductivity type region. The gist is:
以下、この発明にかかる電界効果半導体装置を、その−
例である縦型の電界効果トランジスタ（以下、ｒＦＦ、
ＴＪという）をあられした図面を参照しながら詳しく説
明する。Hereinafter, the field effect semiconductor device according to the present invention will be described.
An example of a vertical field effect transistor (rFF)
This will be explained in detail with reference to the drawings showing the TJ.
第１図は、この発明にかかる電界効果半導体装置の一実
施例であるＦＥＴの断面構造をあられしたものである。FIG. 1 shows a cross-sectional structure of an FET which is an embodiment of a field effect semiconductor device according to the present invention.
ＦＥＴＩのドレイン領域となるＮ＋層３ａとＮ−層３ｂ
を有する半導体基板２を備えている。半導体基板２表面
に互いに離れてＰ層（逆導電型領域）５・・・５が形成
されていて、各Ｐ層５の表面に互いに離れるようにして
Ｎ１層４．４が形成されている。２層５の外側における
Ｎ−層３ｂの表面にＮ゛層３Ｃが形成されている。Ｎ″
層３ａの上（半導体基板の他側表面）にはドレイン電極
６が形成されている。Ｐ層５表面とＮ゛層４４表面の両
方に渡るようにしてソース電極７・・・７が形成されて
いる。ゲート電極８・・・８は絶縁層１０の上に形成さ
れている。Ｎ“層３Ｃには別のソース電極９．９が形成
されている。N+ layer 3a and N- layer 3b which become the drain region of FETI
A semiconductor substrate 2 is provided. P layers (opposite conductivity type regions) 5 . An N layer 3C is formed on the surface of the N− layer 3b outside the second layer 5. N''
A drain electrode 6 is formed on the layer 3a (on the other surface of the semiconductor substrate). Source electrodes 7 . . . 7 are formed so as to span both the surface of the P layer 5 and the surface of the N layer 44 . Gate electrodes 8...8 are formed on the insulating layer 10. Another source electrode 9.9 is formed in the N'' layer 3C.
ＦＥ、Ｔ１は、ＭＯＳ （絶縁ゲート型）ＦＥＴとＪ（
接合型）ＦＥＴのふたつの型の縦型トランジスタを有し
ている。ＭＯＳＦＥＴは、Ｎ３層（ソースｆＪ域）４、
Ｐ層（ベース領域）５、ドレイン領域となるＮ−層３ａ
、Ｎ”層３ｂ、電極６．７．８で構成されていて、チャ
ンネルは２層５の表面部ＣＨに形成される。ＪＦＥＴは
、Ｎ０層（ソース領域）３ｃ、Ｐ層（ゲート領域）５、
ドレイン領域となるＮ−層３ａ、Ｎ“層３ｂ、電極６．
９で構成されていて、チャンネルはドレイン領域に形成
される。つまり、従来と違って、ＦＥＴＩには、ＪＦＥ
Ｔも形成されているのである。FE, T1 are MOS (insulated gate type) FET and J(
It has two types of vertical transistors: junction type) FET. The MOSFET has N3 layer (source fJ region) 4,
P layer (base region) 5, N- layer 3a which becomes the drain region
, an N'' layer 3b, and electrodes 6, 7, and 8, and a channel is formed in the surface portion CH of the second layer 5.The JFET consists of an N0 layer (source region) 3c, a P layer (gate region) ,
N- layer 3a, N'' layer 3b, electrode 6. which becomes a drain region.
9, and the channel is formed in the drain region. In other words, unlike before, FETI includes JFE
T is also formed.
ＦＥＴＩは、ゼロバイアス状態において空乏層が２点鎖
線Ａより上のＮ−層３ｂ内に横方向に連続して生ずるよ
うに、各領域（特にＮ−層など）における不純物濃度お
よびディメンジョン（特に２層５．５間の距離など）が
選定されている。そのため、ＦＥＴＩはエンハンストメ
ント型の動作をする。In the FETI, the impurity concentration and dimension (especially 2 (e.g., the distance between layers 5.5) is selected. Therefore, FETI operates as an enhancement type.
ゲート電圧（ゲート電極８に印加される電圧）がＭＯＳ
ＦＥＴのしきい値電圧より低いときは、ＭＯＳＦＥＴは
導通しない。さらに空乏層の作用により、ＪＦＥＴも遮
断状態にある。したがって、ドレイン電圧が一定の値以
下のときには、ＦＥＴＩには全く電流が流れないことに
なる。ゲート電圧がしきい値電圧を越えると、ＭＯＳＦ
ＥＴが導通ずるようになる。このとき、電極６．８間の
電圧を支えて、ＪＦＥＴを遮断状態に保たせていた空乏
層が、実効的に電圧を支えきれなくなる、そのため、Ｊ
ＦＥＴも導通することとなる。したがって、ＦＥＴＩが
導通状態にあるときには、従来のドレイン電極６とソー
ス電極７の間に形成される電流通路の他に、ドレイン電
極６と別のソース電極９の間にあらたな電流通路が形成
されることとなる。つまり、Ｎ−層３ｂは表面付近の個
所も十分電流通路として使われることとなるので、ＦＥ
ＴＩはオン抵抗が上昇を抑制され、かつ電流容量が増加
することとなるのである。もちろん、従来と同じ電流容
量であれば、オン抵抗が低くくなることになる。The gate voltage (voltage applied to the gate electrode 8) is MOS
When the voltage is lower than the threshold voltage of the FET, the MOSFET does not conduct. Furthermore, due to the effect of the depletion layer, the JFET is also in a cut-off state. Therefore, when the drain voltage is below a certain value, no current flows through the FETI. When the gate voltage exceeds the threshold voltage, the MOSF
ET becomes conductive. At this time, the depletion layer that supported the voltage between the electrodes 6 and 8 and kept the JFET in a cut-off state can no longer effectively support the voltage, so that the
The FET will also become conductive. Therefore, when the FETI is in a conductive state, in addition to the current path formed between the conventional drain electrode 6 and source electrode 7, a new current path is formed between the drain electrode 6 and another source electrode 9. The Rukoto. In other words, the parts near the surface of the N- layer 3b are also used as current paths, so the FE
In TI, the increase in on-resistance is suppressed and the current capacity increases. Of course, if the current capacity is the same as before, the on-resistance will be lower.
この発明は、上記実施例に限定されない。例えば、各半
導体層の導電型が全（逆である構成であってもよい、２
層５の数も３個であったが、これに限られない。This invention is not limited to the above embodiments. For example, the conductivity type of each semiconductor layer may be all (or vice versa).
Although the number of layers 5 was also three, it is not limited to this.
以上に述べたように、この発明にかかる電界効果半導体
装置は、半導体基板の一側にドレイン電極を備えている
とともに他側にソース電極と絶縁ゲート電極を備えてい
て、前記基板の他側表面に形成された逆導電型領域表面
にチャンネルが形成されるようになっている構成におい
て、前記逆導電型領域の外側における前記他側表面に別
のソース電極を備えている。そのため、電界効果半導体
装置は、ドレイン領域が有効に作用しオン抵抗が小さく
、大電流制御に適したものとなる。As described above, the field effect semiconductor device according to the present invention includes a drain electrode on one side of a semiconductor substrate, a source electrode and an insulated gate electrode on the other side, and a surface of the other side of the substrate. In the configuration in which a channel is formed on the surface of a region of opposite conductivity type formed in the semiconductor device, another source electrode is provided on the other side surface outside the region of opposite conductivity type. Therefore, in the field effect semiconductor device, the drain region functions effectively, the on-resistance is small, and the device is suitable for large current control.
第１図は、この発明にかかる電界効果半導体装置の一実
施例であるＦＥＴの構造をあられした断面図、第２図は
、従来のＦＥＴの構造をあられした断面図である。
１・・・ＦＥＴ（電界効果半導体装置） ２・・・半導
体基板 ５・・・Ｐ層（逆導電型領域） ６・・・ド
レイン電極 ７・・・ソース電極 ８・・・ゲート
電極９・・・別のソース電極
代理人 弁理士 松 本 武 彦
第２図FIG. 1 is a sectional view showing the structure of an FET which is an embodiment of the field effect semiconductor device according to the present invention, and FIG. 2 is a sectional view showing the structure of a conventional FET. 1...FET (field effect semiconductor device) 2...Semiconductor substrate 5...P layer (opposite conductivity type region) 6...Drain electrode 7...Source electrode 8...Gate electrode 9...・Another source electrode representative: Patent attorney Takehiko Matsumoto Figure 2
Claims (2)
ともに他側にソース電極と絶縁ゲート電極を備えていて
、前記基板の他側表面に形成された逆導電型領域表面に
チャンネルが形成されるようになっている電界効果半導
体装置において、前記逆導電型領域の外側における前記
他側表面に別のソース電極を備えていることを特徴とす
る電界効果半導体装置。(1) A semiconductor substrate has a drain electrode on one side, a source electrode and an insulated gate electrode on the other side, and a channel is formed on the surface of an opposite conductivity type region formed on the other side of the substrate. What is claimed is: 1. A field effect semiconductor device characterized in that the field effect semiconductor device is characterized in that another source electrode is provided on the other side surface outside the opposite conductivity type region.
形成されていて、別のソース電極が前記逆導電型領域の
間に位置している特許請求の範囲第１項記載の電界効果
半導体装置。(2) A field effect semiconductor according to claim 1, wherein a plurality of opposite conductivity type regions are formed so as to be spaced apart from each other, and another source electrode is located between the opposite conductivity type regions. Device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61199745A JPH0673381B2 (en) | 1986-08-26 | 1986-08-26 | Field effect semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61199745A JPH0673381B2 (en) | 1986-08-26 | 1986-08-26 | Field effect semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6355976A true JPS6355976A (en) | 1988-03-10 |
| JPH0673381B2 JPH0673381B2 (en) | 1994-09-14 |
Family
ID=16412924
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61199745A Expired - Lifetime JPH0673381B2 (en) | 1986-08-26 | 1986-08-26 | Field effect semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0673381B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0654827A1 (en) * | 1993-05-26 | 1995-05-24 | Texas Instruments Incorporated | Integrated power cascode |
| WO1995018465A1 (en) * | 1993-12-28 | 1995-07-06 | North Carolina State University | Three-terminal gate-controlled semiconductor switching device with rectifying-gate |
| US5488236A (en) * | 1994-05-26 | 1996-01-30 | North Carolina State University | Latch-up resistant bipolar transistor with trench IGFET and buried collector |
-
1986
- 1986-08-26 JP JP61199745A patent/JPH0673381B2/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0654827A1 (en) * | 1993-05-26 | 1995-05-24 | Texas Instruments Incorporated | Integrated power cascode |
| WO1995018465A1 (en) * | 1993-12-28 | 1995-07-06 | North Carolina State University | Three-terminal gate-controlled semiconductor switching device with rectifying-gate |
| US5488236A (en) * | 1994-05-26 | 1996-01-30 | North Carolina State University | Latch-up resistant bipolar transistor with trench IGFET and buried collector |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0673381B2 (en) | 1994-09-14 |
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