JPS6355976A - Field effect semiconductor device - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] 〔Technical field〕 The present invention relates to a field effect semiconductor device.

[Background technology]

An insulated gate field effect transistor is one type of field effect semiconductor device. Since the development of insulated gate field effect transistors with a vertical structure, applications for so-called power applications such as power control have been expanded. Figure 2 shows
This is a cross-sectional view of a vertical insulated gate field effect transistor. The insulated gate field effect transistor 21 having a vertical structure includes a drain electrode 26 on the back surface of a semiconductor substrate 22, and a source electrode 27 on the front surface.
A gate electrode 28 is formed on the insulating layer 30, comprising a gate electrode 27 and a gate electrode 28.28. The channel is formed in the surface portion CH of the two layers 25.sub.2 under the gate electrode 28.

However, compared to other power control elements, the insulated gate field effect transistor 21 tends to have a large forward voltage drop (that is, a large on-resistance) in a conductive element. When the insulated gate field effect transistor 21 is in a conductive state, current enters from the drain electrode 27 and flows through the N layer 2.
3 flows vertically as shown by the two-pointed arrow, then changes horizontally near the surface and flows through the channel to the drain electrode 2.
Reach 6. In this case, current concentration occurs in the N layer (drain region) 23 near the substrate surface, that is, the drain region cannot function effectively as a conductor. Therefore, the on-resistance inevitably increases. If the on-resistance is large, the element capacitance becomes small, resulting in disadvantages such as a limited range of use.

[Purpose of the invention]

In view of the above circumstances, it is an object of the present invention to provide a field effect semiconductor device in which the drain region functions effectively, has low on-resistance, and is suitable for large current control.

[Disclosure of the invention]

To achieve the above object, the present invention includes a semiconductor substrate having a drain electrode on one side, a source electrode and an insulated gate electrode on the other side, and a reverse conductive electrode formed on the other side surface of the substrate. A field effect semiconductor device in which a channel is formed on the surface of a type region, characterized in that another source electrode is provided on the other side surface outside the opposite conductivity type region. The gist is:

Hereinafter, the field effect semiconductor device according to the present invention will be described.
An example of a vertical field effect transistor (rFF)
This will be explained in detail with reference to the drawings showing the TJ.

FIG. 1 shows a cross-sectional structure of an FET which is an embodiment of a field effect semiconductor device according to the present invention.

N+ layer 3a and N- layer 3b which become the drain region of FETI
A semiconductor substrate 2 is provided. P layers (opposite conductivity type regions) 5 . An N layer 3C is formed on the surface of the N− layer 3b outside the second layer 5. N''
A drain electrode 6 is formed on the layer 3a (on the other surface of the semiconductor substrate). Source electrodes 7 . . . 7 are formed so as to span both the surface of the P layer 5 and the surface of the N layer 44 . Gate electrodes 8...8 are formed on the insulating layer 10. Another source electrode 9.9 is formed in the N'' layer 3C.

FE, T1 are MOS (insulated gate type) FET and J(
It has two types of vertical transistors: junction type) FET. The MOSFET has N3 layer (source fJ region) 4,
P layer (base region) 5, N- layer 3a which becomes the drain region
, an N'' layer 3b, and electrodes 6, 7, and 8, and a channel is formed in the surface portion CH of the second layer 5.The JFET consists of an N0 layer (source region) 3c, a P layer (gate region) ,
N- layer 3a, N'' layer 3b, electrode 6. which becomes a drain region.
9, and the channel is formed in the drain region. In other words, unlike before, FETI includes JFE
T is also formed.

In the FETI, the impurity concentration and dimension (especially 2 (e.g., the distance between layers 5.5) is selected. Therefore, FETI operates as an enhancement type.

The gate voltage (voltage applied to the gate electrode 8) is MOS
When the voltage is lower than the threshold voltage of the FET, the MOSFET does not conduct. Furthermore, due to the effect of the depletion layer, the JFET is also in a cut-off state. Therefore, when the drain voltage is below a certain value, no current flows through the FETI. When the gate voltage exceeds the threshold voltage, the MOSF
ET becomes conductive. At this time, the depletion layer that supported the voltage between the electrodes 6 and 8 and kept the JFET in a cut-off state can no longer effectively support the voltage, so that the
The FET will also become conductive. Therefore, when the FETI is in a conductive state, in addition to the current path formed between the conventional drain electrode 6 and source electrode 7, a new current path is formed between the drain electrode 6 and another source electrode 9. The Rukoto. In other words, the parts near the surface of the N- layer 3b are also used as current paths, so the FE
In TI, the increase in on-resistance is suppressed and the current capacity increases. Of course, if the current capacity is the same as before, the on-resistance will be lower.

This invention is not limited to the above embodiments. For example, the conductivity type of each semiconductor layer may be all (or vice versa).
Although the number of layers 5 was also three, it is not limited to this.

〔Effect of the invention〕

As described above, the field effect semiconductor device according to the present invention includes a drain electrode on one side of a semiconductor substrate, a source electrode and an insulated gate electrode on the other side, and a surface of the other side of the substrate. In the configuration in which a channel is formed on the surface of a region of opposite conductivity type formed in the semiconductor device, another source electrode is provided on the other side surface outside the region of opposite conductivity type. Therefore, in the field effect semiconductor device, the drain region functions effectively, the on-resistance is small, and the device is suitable for large current control.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing the structure of an FET which is an embodiment of the field effect semiconductor device according to the present invention, and FIG. 2 is a sectional view showing the structure of a conventional FET. 1...FET (field effect semiconductor device) 2...Semiconductor substrate 5...P layer (opposite conductivity type region) 6...Drain electrode 7...Source electrode 8...Gate electrode 9...・Another source electrode representative: Patent attorney Takehiko Matsumoto Figure 2

Claims (2)

[Claims] (1) A semiconductor substrate has a drain electrode on one side, a source electrode and an insulated gate electrode on the other side, and a channel is formed on the surface of an opposite conductivity type region formed on the other side of the substrate. What is claimed is: 1. A field effect semiconductor device characterized in that the field effect semiconductor device is characterized in that another source electrode is provided on the other side surface outside the opposite conductivity type region. (2) A field effect semiconductor according to claim 1, wherein a plurality of opposite conductivity type regions are formed so as to be spaced apart from each other, and another source electrode is located between the opposite conductivity type regions. Device.