JPS63252480A - Vertical mos field-effect transistor - Google Patents

Vertical mos field-effect transistor

Info

Publication number
JPS63252480A
JPS63252480A JP62089104A JP8910487A JPS63252480A JP S63252480 A JPS63252480 A JP S63252480A JP 62089104 A JP62089104 A JP 62089104A JP 8910487 A JP8910487 A JP 8910487A JP S63252480 A JPS63252480 A JP S63252480A
Authority
JP
Japan
Prior art keywords
regions
region
effect transistor
vertical mos
channel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62089104A
Other languages
Japanese (ja)
Inventor
Yoshiaki Hisamoto
好明 久本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP62089104A priority Critical patent/JPS63252480A/en
Publication of JPS63252480A publication Critical patent/JPS63252480A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

PURPOSE:To keep the extension of a depletion layer constant, and to increase breakdown strength by forming regions having the same conductivity type as channel regions into field concentration regions among the channel regions arranged to a matrix shape. CONSTITUTION:An n<+> drain region 2 is shaped onto one main surface of an n-type substrate 1, and matrix-shaped p channel regions 3 are formed to the other main surface. n source regions 4 are shaped into the channel regions 3, and oxide films 5 are formed so as to coat main surfaces among adjacent p channels 3 and one parts of the source regions. Gate electrodes 6 and insulating films are shaped onto the oxide films 5. p-type regions 10 are formed into field concentration regions at positions at equal distances from the channel regions 3. Accordingly, the extension of a depletion layer is kept approximately constant, thus increasing breakdown strength.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、縦形モス電界効果トランジスタ（縦形ＭＯ
Ｓ　ＦＥＴ　）に関するものである。[Detailed Description of the Invention] [Industrial Application Field] This invention relates to a vertical MOS field effect transistor (vertical MOSFET).
SFET).

〔従来の技術〕[Conventional technology]

第２図は従来の縦形ＭＯ５ＦＥＴを示す。図において、
１はｎ形（第１導電形）基板、２はｍｌ記基板１の一ノ
ｊの主面に形成したｎゝドレン領域、３は前記基板の他
方の主面に７トリクス状に形成したｐ（第２導電形）チ
ャンネル領域、４はこのＰチャンネル領域に形成された
ｎソース＠域、５は隣り合うｐチャンネルの間の主面と
ｎソース領域の一部を覆うように形成した酸化膜、６は
この酸化膜の上に形成したゲート電極、７はこのゲート
電極を覆うように形成した絶縁膜、８は前記ｎソース領
域５に取り付けたソース電極である。FIG. 2 shows a conventional vertical MO5FET. In the figure,
1 is an n-type (first conductivity type) substrate, 2 is an n drain region formed on one main surface of the substrate 1, and 3 is a p region formed in a 7-trix shape on the other main surface of the substrate. (Second conductivity type) channel region, 4 is an n source @ region formed in this P channel region, 5 is an oxide film formed to cover the main surface between adjacent p channels and a part of the n source region , 6 is a gate electrode formed on this oxide film, 7 is an insulating film formed to cover this gate electrode, and 8 is a source electrode attached to the n source region 5.

従来の縦形モス電界効果トランジスタは上記のように構
成したから、縦形モス電界効果トランジスタのしきい値
より高い正電位をゲート電極６に印加すると、Ｐチャン
ネル領域３の表面部分がｎチャンネルに反転し、電流は
第２図（ｈ）。Since the conventional vertical MOS field effect transistor is constructed as described above, when a positive potential higher than the threshold of the vertical MOS field effect transistor is applied to the gate electrode 6, the surface portion of the P channel region 3 is inverted to an n channel. , the current is shown in Figure 2 (h).

（Ｃ）の破線で示すように、ｎ＋ドレン領域２から、ま
ず、ゲート電極６に向って縦方向に流れ、ついで、隣り
合うｐチャンネル領域３間の領域で向きを変え、前記ｎ
チャンネルを通ってｎソース領域５に至る。As shown by the broken line in (C), the flow first flows vertically from the n+ drain region 2 toward the gate electrode 6, then changes direction in the region between adjacent p channel regions 3, and the n
It passes through the channel and reaches the n source region 5.

第２図（ｂ）に、ゲート電極に印加した電位がしきい値
に達しない時、すなわちＯＦＦ状憇に発生ずる空乏層を
一点鎖線で示す。In FIG. 2(b), a chain line indicates a depletion layer that occurs when the potential applied to the gate electrode does not reach the threshold value, that is, in the OFF state.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

従来の縦形モス電界効果トランジスタは、第２図（ａ）
に示すように、複数のＰチャンネル領域３をマトリクス
状に形成したから、第２図（ｂ）のＡ２〜Ａ２線断面図
に示す隣り合うｐチャンネル領域３間の距離と、第２図
（ｅ）の８２−８２線断面図に示す隣り合うｐチャンネ
ル領域３間の距離との比は、ｔ：ｆ了で、ｐチャンネル
領域３間の距離が異なるため、ＯＦＦ状憇におけるＰチ
ャンネル領域３間での空乏層の拡がりは、一定にならな
い。その結果、第２図（Ｃ）に一点鎖線で示すように、
各Ｐチャンネル領域３か゛ら等距離の位置に、電界が集
中し、その電界が集中する箇所では、なだれ降伏電圧か
低くなるという問題点があった。A conventional vertical MOS field effect transistor is shown in Fig. 2(a).
Since a plurality of P channel regions 3 are formed in a matrix as shown in FIG. ) is the ratio of the distance between adjacent p-channel regions 3 shown in the 82-82 line cross-sectional view. The spread of the depletion layer in the region is not constant. As a result, as shown by the dashed line in Fig. 2(C),
There is a problem in that the electric field is concentrated at a position equidistant from each P channel region 3, and the avalanche breakdown voltage is low at the location where the electric field is concentrated.

この発明は、上記のような問題点を解決するためになさ
れたもので、高耐圧の縦形モス電界効果トランジスタを
得ることを目的とする。The present invention was made to solve the above-mentioned problems, and an object of the present invention is to obtain a vertical MOS field effect transistor with high breakdown voltage.

（問題点を解決するための手段〕 この発明に係る縦形モス電界効果トランジスタは、第１
導電形基板の一方の１簡に第１導電形のドレンを、他方
の主１ｎ１にマトリックス状に配置したチャンネル領域
と、このチャンネル領域内に第１導電形のソースとを有
し、かつ、面記チャンネル間の基板表面にゲートを有す
る縦形モス電界効果トランジスタであって、電界が集中
する領域に、第２導電形の領域を設けたものである。(Means for Solving the Problems) The vertical MOS field effect transistor according to the present invention has a first
A conductive type substrate has a drain of the first conductive type in one main part thereof, a channel region arranged in a matrix in the other main part, and a source of the first conductive type in this channel region, and This vertical MOS field effect transistor has a gate on the substrate surface between the channels, and a region of the second conductivity type is provided in the region where the electric field is concentrated.

（作用） この発明によって形成した第２導電形の領域は、電界が
集中する領域に、前記電界と逆方向に所定の電界を形成
し、空乏層の拡がりをほぼ一定にする。(Function) The region of the second conductivity type formed according to the present invention forms a predetermined electric field in the opposite direction to the electric field in the region where the electric field is concentrated, thereby making the spread of the depletion layer almost constant.

（実施例） 第１図はこの発明の−・実施例を示す。図において、１
〜８は第２図と同一部分を示す。１０は第２導電形の領
域としての１層領域で、電界集中領域、すなわち、各ｐ
チャンネル領域３から等距離の位置に形成してあり、前
記電界と逆方向に所定の電界を発生するものである。(Embodiment) FIG. 1 shows an embodiment of the present invention. In the figure, 1
8 show the same parts as in FIG. 10 is a single-layer region as a region of the second conductivity type, which is an electric field concentration region, that is, each p
It is formed at a position equidistant from the channel region 3, and generates a predetermined electric field in the opposite direction to the electric field.

この実施例の縦形モス電界効果トランジスタは、各ｐチ
ャンネル領域３から等距離の位置に９層領域１０を形成
する構成にしたから、このｐＭＩＪ領域１０近傍の電界
は、９層領域１０が形成する電界により相殺され、第１
図（Ｃ）に一点鎖線で示すように、空乏層の拡がりはほ
ぼ一定になる。Since the vertical MOS field effect transistor of this embodiment has a structure in which the 9-layer region 10 is formed at a position equidistant from each p-channel region 3, the electric field near this pMIJ region 10 is generated by the 9-layer region 10. canceled by the electric field, the first
As shown by the dashed line in the figure (C), the spread of the depletion layer becomes almost constant.

（発明の効果〕 以上説明したように、この発明によれば、電界集中領域
に、前記電界と逆方向に所定の電界を発生する構成にし
たので、空乏層の拡がりがほぼ一定になり、高耐圧の縦
形モス電界効果トランジスタを得ることができるいう効
果がある。(Effects of the Invention) As explained above, according to the present invention, since a predetermined electric field is generated in the electric field concentration region in the opposite direction to the electric field, the spread of the depletion layer becomes almost constant and the This has the advantage that a vertical MOS field effect transistor with high breakdown voltage can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第１Ｍはこの発明の一実施例を示す図で、第１図（ａ）
は縦形モス電界効果トランジスタの一部破断乎面図、第
１図（ｂ）は第１図（ａ）に示すＡ、−Ａ、線断面図、
第１図（Ｃ）は第１図（ａ）に示すＢ、−Ｂ、線断面図
である。第２図は従来の縦形モス電界効果トランジスタ
を示す図で、第２図（ａ）は一部破断乎面図、第２図（
ｂ）は第２図（ａ）に示すＡ２−Ａ２線断面図、第２図
（Ｃ）は第２図（ａ）に示すＢ２−８２線断面図である
。 図において、１は口形基板、２はｎ“トレン領域、３は
Ｐチャンネル領域、４はｎソース領域、６はゲート電極
、１０はｐＨ領域である。 なお、図中、同一符号は同一または相当部分を示す。1M is a diagram showing an embodiment of the present invention, and FIG. 1(a)
is a partially cutaway view of a vertical MOS field effect transistor, FIG. 1(b) is a cross-sectional view taken along the line A, -A shown in FIG. 1(a),
FIG. 1(C) is a sectional view taken along the line B and -B shown in FIG. 1(a). Figure 2 shows a conventional vertical MOS field effect transistor; Figure 2(a) is a partially cutaway view;
b) is a sectional view taken along line A2-A2 shown in FIG. 2(a), and FIG. 2(C) is a sectional view taken along line B2-82 shown in FIG. 2(a). In the figure, 1 is a mouth-shaped substrate, 2 is an n-tren region, 3 is a P-channel region, 4 is an n-source region, 6 is a gate electrode, and 10 is a pH region. Show parts.

Claims (1)

【特許請求の範囲】[Claims] 第１導電形基板の一方の主面に第１導電形のドレンを、
他方の主面にマトリックス状に配置した第２導電形のチ
ャンネル領域と、このチャンネル領域内に第１導電形の
ソースとを有し、かつ、前記チャンネル間の基板表面に
ゲートを有する縦形モス電界効果トランジスタにおいて
、電界が集中する領域に、第２導電形の領域を備えたこ
とを特徴とする縦形モス電界効果トランジスタ。A drain of the first conductivity type is provided on one main surface of the first conductivity type substrate,
A vertical MOS electric field having a second conductivity type channel region arranged in a matrix on the other main surface, a first conductivity type source within the channel region, and a gate on the substrate surface between the channels. A vertical MOS field effect transistor characterized in that the effect transistor includes a region of a second conductivity type in a region where an electric field is concentrated.
JP62089104A 1987-04-09 1987-04-09 Vertical mos field-effect transistor Pending JPS63252480A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62089104A JPS63252480A (en) 1987-04-09 1987-04-09 Vertical mos field-effect transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62089104A JPS63252480A (en) 1987-04-09 1987-04-09 Vertical mos field-effect transistor

Publications (1)

Publication Number Publication Date
JPS63252480A true JPS63252480A (en) 1988-10-19

Family

ID=13961580

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62089104A Pending JPS63252480A (en) 1987-04-09 1987-04-09 Vertical mos field-effect transistor

Country Status (1)

Country Link
JP (1) JPS63252480A (en)

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02292868A (en) * 1989-05-01 1990-12-04 Nippon Inter Electronics Corp Field-effect transistor
JPH03230574A (en) * 1990-02-06 1991-10-14 Matsushita Electron Corp Semiconductor device
US5136349A (en) * 1989-08-30 1992-08-04 Siliconix Incorporated Closed cell transistor with built-in voltage clamp
US5155574A (en) * 1990-03-20 1992-10-13 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
US5420450A (en) * 1992-09-10 1995-05-30 Kabushiki Kaisha Toshiba Semiconductor device having stable breakdown voltage in wiring area
JP2005136166A (en) * 2003-10-30 2005-05-26 Matsushita Electric Ind Co Ltd Vertical mosfet
JP2006019553A (en) * 2004-07-02 2006-01-19 Matsushita Electric Ind Co Ltd Vertical semiconductor device
US7833863B1 (en) 2003-12-02 2010-11-16 Vishay-Siliconix Method of manufacturing a closed cell trench MOSFET
CN102244100A (en) * 2011-06-28 2011-11-16 上海宏力半导体制造有限公司 MOS (metal oxide semiconductor) power semiconductor device
US8183629B2 (en) 2004-05-13 2012-05-22 Vishay-Siliconix Stacked trench metal-oxide-semiconductor field effect transistor device
US8368126B2 (en) 2007-04-19 2013-02-05 Vishay-Siliconix Trench metal oxide semiconductor with recessed trench material and remote contacts
US8471390B2 (en) 2006-05-12 2013-06-25 Vishay-Siliconix Power MOSFET contact metallization
US9306056B2 (en) 2009-10-30 2016-04-05 Vishay-Siliconix Semiconductor device with trench-like feed-throughs

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS607764A (en) * 1983-06-13 1985-01-16 エヌ・ベ−・フイリツプス・フル−イランペンフアブリケン Semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS607764A (en) * 1983-06-13 1985-01-16 エヌ・ベ−・フイリツプス・フル−イランペンフアブリケン Semiconductor device

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02292868A (en) * 1989-05-01 1990-12-04 Nippon Inter Electronics Corp Field-effect transistor
US5136349A (en) * 1989-08-30 1992-08-04 Siliconix Incorporated Closed cell transistor with built-in voltage clamp
JPH03230574A (en) * 1990-02-06 1991-10-14 Matsushita Electron Corp Semiconductor device
US5155574A (en) * 1990-03-20 1992-10-13 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
US5420450A (en) * 1992-09-10 1995-05-30 Kabushiki Kaisha Toshiba Semiconductor device having stable breakdown voltage in wiring area
JP2005136166A (en) * 2003-10-30 2005-05-26 Matsushita Electric Ind Co Ltd Vertical mosfet
US7833863B1 (en) 2003-12-02 2010-11-16 Vishay-Siliconix Method of manufacturing a closed cell trench MOSFET
US8183629B2 (en) 2004-05-13 2012-05-22 Vishay-Siliconix Stacked trench metal-oxide-semiconductor field effect transistor device
JP2006019553A (en) * 2004-07-02 2006-01-19 Matsushita Electric Ind Co Ltd Vertical semiconductor device
US8697571B2 (en) 2006-05-12 2014-04-15 Vishay-Siliconix Power MOSFET contact metallization
US8471390B2 (en) 2006-05-12 2013-06-25 Vishay-Siliconix Power MOSFET contact metallization
US8368126B2 (en) 2007-04-19 2013-02-05 Vishay-Siliconix Trench metal oxide semiconductor with recessed trench material and remote contacts
US8883580B2 (en) 2007-04-19 2014-11-11 Vishay-Siliconix Trench metal oxide semiconductor with recessed trench material and remote contacts
US9306056B2 (en) 2009-10-30 2016-04-05 Vishay-Siliconix Semiconductor device with trench-like feed-throughs
US10032901B2 (en) 2009-10-30 2018-07-24 Vishay-Siliconix Semiconductor device with trench-like feed-throughs
CN102244100A (en) * 2011-06-28 2011-11-16 上海宏力半导体制造有限公司 MOS (metal oxide semiconductor) power semiconductor device

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