JPH05343691A - Vertical insulated-gate field-effect transistor - Google Patents
Vertical insulated-gate field-effect transistorInfo
- Publication number
- JPH05343691A JPH05343691A JP4147714A JP14771492A JPH05343691A JP H05343691 A JPH05343691 A JP H05343691A JP 4147714 A JP4147714 A JP 4147714A JP 14771492 A JP14771492 A JP 14771492A JP H05343691 A JPH05343691 A JP H05343691A
- Authority
- JP
- Japan
- Prior art keywords
- region
- groove
- type
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- regions
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 title claims description 8
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 239000004065 semiconductor Substances 0.000 claims abstract description 17
- 239000012535 impurity Substances 0.000 claims description 10
- 230000015556 catabolic process Effects 0.000 abstract description 19
- 230000000694 effects Effects 0.000 description 10
- 238000010586 diagram Methods 0.000 description 7
- 230000007423 decrease Effects 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 238000004364 calculation method Methods 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0878—Impurity concentration or distribution
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は、縦型絶縁ゲート電界
効果トランジスタ（縦型ＭＯＳＦＥＴ）に係り、特にそ
のオン抵抗低減に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vertical insulated gate field effect transistor (vertical MOSFET), and more particularly to reduction of on-resistance thereof.
【０００２】[0002]
【従来の技術】従来、電力用の縦型ＭＯＳＦＥＴについ
ては、図９に示す構造がとられる場合が多かった（例え
ば、特開昭６３−２５４７６９号公報）。この素子のド
レイン・ソース間耐圧はドリフト領域１の厚さ及び不純
物濃度によって決まり、所望の耐圧に見合うような厚さ
と濃度に設定される。ウエル領域２の上部に配置された
ゲート電極３に電圧が印加されるとウエル領域２内の半
導体基板表面にはｎ型反転層が形成されソースとドレイ
ンの間に電流が流れる。実際の縦型ＭＯＳＦＥＴでは図
９中にＡで示した部分（セル）が繰り返し配置されたひ
とつの縦型ＭＯＳＦＥＴを構成している。Ａの寸法Ｌ1
は製造プロセス上あるいは素子特性上許容される限り小
さく設定される。こうすることにより単位面積当たりに
含まれる電流通路の数を最大にすることができる。2. Description of the Related Art Conventionally, a vertical MOSFET for electric power often has the structure shown in FIG. 9 (for example, JP-A-63-254769). The drain-source breakdown voltage of this element is determined by the thickness of the drift region 1 and the impurity concentration, and is set to a thickness and concentration that meet the desired breakdown voltage. When a voltage is applied to the gate electrode 3 arranged above the well region 2, an n-type inversion layer is formed on the surface of the semiconductor substrate in the well region 2 and a current flows between the source and the drain. In an actual vertical MOSFET, one vertical MOSFET in which portions (cells) indicated by A in FIG. 9 are repeatedly arranged is configured. A dimension L1
Is set as small as possible due to the manufacturing process or device characteristics. By doing so, it is possible to maximize the number of current paths included per unit area.
【０００３】一方、電力用縦型ＭＯＳＦＥＴにおける重
要な特性のひとつとして単位面積当たりのオン抵抗（Ｒ
ONS と略称) がある。そして、この値が小さい程、電流
を流した時のソース・ドレイン間の電圧降下が小さく素
子で消費される電力を小さくすることができる。オン抵
抗ＲONS を下げるには素子自身の抵抗を下げるか、単位
素子面積を縮小する必要がある。On the other hand, as one of the important characteristics in the vertical power MOSFET, the on-resistance per unit area (R
ONS ). The smaller this value, the smaller the voltage drop between the source and the drain when a current flows, and the smaller the power consumed by the element. To reduce the on-resistance R ONS , it is necessary to reduce the resistance of the element itself or reduce the unit element area.
【０００４】図１０に示した斜線部はドリフト領域１内
の電流の通路を示している。ネックが形成されるのは半
導体基板の縦方向に寄生的にできる接合型電界効果トラ
ンジスタ（ＪＦＥＴと略称）の効果によるものである。
つまり、ドリフト領域１の抵抗成分により電流通路にそ
って電位差が生じ、接地電位に固定されたソース領域４
及びウエル領域２とドリフト領域１の間の電位差により
ウエル領域２とドリフト領域１の間の接合が逆バイアス
され比較的不純物濃度の低いドリフト領域１側に空乏層
が広がって電流通路がせばめられるものである。このＪ
ＦＥＴの効果が作用する領域の抵抗をＲJFETとする。１
個の縦型ＭＯＳＦＥＴセルにおけるソース端子Ｓとドレ
イン端子Ｄ間のオン抵抗ＲCELLは、ＲJFETの他にソース
領域４の抵抗ＲS 、チャネル抵抗ＲCH、ドリフト領域１
の抵抗ＲDRI 、及びドレイン領域５の抵抗ＲDRA によっ
て表すことができる。すなわち、 ＲCELL＝ＲS ＋ＲCH＋ＲJFET＋ＲDRI ＋ＲDRA …（１） 又、ＲCELLとＲONS の関係は次式で与えられる。The hatched portion shown in FIG. 10 indicates the passage of current in the drift region 1. The neck is formed due to the effect of a junction field effect transistor (abbreviated as JFET) which is parasitically formed in the vertical direction of the semiconductor substrate.
In other words, the resistance component of the drift region 1 causes a potential difference along the current path, and the source region 4 fixed at the ground potential.
And the junction between the well region 2 and the drift region 1 is reverse-biased due to the potential difference between the well region 2 and the drift region 1, and the depletion layer spreads to the side of the drift region 1 where the impurity concentration is relatively low so that the current path is confined. Is. This J
The resistance of the region where the effect of the FET acts is R JFET . 1
The ON resistance R CELL between the source terminal S and the drain terminal D in each vertical MOSFET cell is the resistance R S of the source region 4, the channel resistance R CH , and the drift region 1 in addition to R JFET.
Can be represented by the resistance R DRI of the drain region 5 and the resistance R DRA of the drain region 5. That is, R CELL = R S + R CH + R JFET + R DRI + R DRA (1) Further, the relationship between R CELL and R ONS is given by the following equation.
【０００５】ＲONS ＝ＲCELL／Ｎ…（２） ただし、Ｎは単位面積当たりのセル数。図１０に示した
隣接するゲート電極３の間の距離Ｌ2 は、ソース領域
４、及びウエル領域２の電位を与えるためのｐ+ 領域６
と配線の接触をとるためのスペースである。このＬ2 は
素子を形成するプロセスの加工精度に依存するもので、
製造装置やプロセスを特定すれば決まってしまい、減ら
すことには限界がある。図１１にウエル領域２の間隔Ｌ
3 に対する単位面積当たりのオン抵抗ＲONS の関係を示
す。Ｌ3 を小さくすると、図１０に示す電流通路のネッ
クが細くなりＲJFETが増大し、Ｎの増加よりもＲCELLの
増加が大きくなるためＲONS は増加する。逆にＬ3 を大
きくするとＪＦＥＴの効果は弱くなるが、面積が不必要
に増えてしまい、ＲONS はやはり増加する。結果として
耐圧の仕様とプロセスの加工精度が決まれば、図１１の
ようにＲONS が最小値をとるＬ3 の最適値が存在する。R ONS = R CELL / N (2) where N is the number of cells per unit area. The distance L2 between the adjacent gate electrodes 3 shown in FIG. 10 is equal to the p + region 6 for applying the potentials of the source region 4 and the well region 2.
This is a space for making contact with the wiring. This L2 depends on the processing accuracy of the process of forming the element,
It is decided once the manufacturing equipment and process are specified, and there is a limit to the reduction. The spacing L between the well regions 2 is shown in FIG.
The relationship of the ON resistance R ONS per unit area with respect to 3 is shown. When L3 is made smaller, the neck of the current path shown in FIG. 10 becomes narrower, R JFET increases, and R CELL increases more than N increases, so R ONS increases. On the contrary, if L3 is increased, the effect of JFET is weakened, but the area is unnecessarily increased and R ONS is also increased. As a result, if the specifications of withstand voltage and the processing accuracy of the process are determined, there exists an optimum value of L3 for which R ONS has the minimum value as shown in FIG.
【０００６】図１１に示すＲONS の最小値をさらに低下
させるために、特開昭６３−２５４７６９号公報には図
１２に示す構造が提案されている。この構造はウエル領
域２で挟まれた領域に溝７を堀り、この溝７の周辺に高
濃度不純物層８を形成して、この部分の抵抗を下げてい
る。従って、ウエル領域２とドリフト領域１との境界部
分からドリフト領域１に向かって空乏層が拡がってきて
も溝７の周辺の高濃度不純物層８は空乏化されず低抵抗
の状態を保つことができＲJFETを極めて小さくすること
ができる。従って、 ＲCELL＝ＲS ＋ＲCH＋ＲDRI ＋ＲDRA …（３） このように図１２の構造はＪＦＥＴ効果によるオン抵抗
の増大を抑えることができ、換言すると、同じＲJFETな
らば、ウエル領域２の間隔Ｌ3 を短くすることができ、
セル数Ｎを変えずにＲCELLを減少させることで、図９の
構造に比べてよりＲONS を低くできる。In order to further reduce the minimum value of R ONS shown in FIG. 11, Japanese Patent Laid-Open No. 63-254769 proposes a structure shown in FIG. In this structure, a groove 7 is dug in a region sandwiched by the well regions 2 and a high-concentration impurity layer 8 is formed around the groove 7 to reduce the resistance of this portion. Therefore, even if the depletion layer expands from the boundary between the well region 2 and the drift region 1 toward the drift region 1, the high-concentration impurity layer 8 around the groove 7 is not depleted and can maintain a low resistance state. It is possible to make R JFET extremely small. Therefore, the structure of R CELL = R S + R CH + R DRI + R DRA ... (3) Thus 12 can suppress an increase in on-resistance with JFET effect, in other words, if the same R JFET, the well region 2 The distance L3 can be shortened,
By reducing R CELL without changing the number of cells N, R ONS can be made lower than in the structure of FIG.
【０００７】[0007]
【発明が解決しようとする課題】ところが、図１２に示
す従来技術は図９に示す従来技術に比べるとＲONS を減
少する手段としてある程度は効果が期待できる。しか
し、近年、微細加工技術が進歩し、耐圧数十ボルトの低
耐圧仕様の縦型ＭＯＳＦＥＴについては、図１０に示す
ウエル領域２の間隔Ｌ3 は数μｍに縮小でき、また図９
中のＡの寸法Ｌ1 が２０μｍ以下にできるようになっ
た。この結果、図１２に示す従来技術では、ウエル領域
２と高濃度不純物層８との間のリーチスルー耐圧をウエ
ル領域２とドレイン領域５との間のリーチスルー耐圧よ
りも高く設定する必要性から逆にウエル領域２の間隔Ｌ
3 を大きくしなければならず面積が不必要に増えてしま
い（２）式から明らかなようにＲCELLを小さくしても、
それ以上にＮが小さくなるためＲ ONS がかえって増加す
る問題があった。又、図１２に示す従来技術はＲJFETを
減少させる効果だけであり、その他のＲDRI は減少しな
いためＲONS の減少率は少なかった。すなわち、素子の
耐圧を損なわずに必ずしもＲONS を低減することはでき
なかった。However, as shown in FIG.
Compared with the conventional technique shown in FIG.ONSReduced
As a means to reduce the number, some effects can be expected. Only
However, in recent years, microfabrication technology has advanced and the withstand voltage is as low as tens of volts.
Figure 10 shows the vertical MOSFET withstand voltage specifications.
The distance L3 between the well regions 2 can be reduced to several .mu.m.
The dimension L1 of the inside A can now be set to 20 μm or less.
It was As a result, in the conventional technique shown in FIG.
2 and the high-concentration impurity layer 8
The reach-through breakdown voltage between the drain region 2 and the drain region 5.
On the contrary, the interval L between the well regions 2 should be set higher.
3 must be increased and the area unnecessarily increases.
As is clear from equation (2), RCELLEven if you reduce
Since N becomes smaller than that, R ONSOn the contrary, it increases
There was a problem. Further, the conventional technique shown in FIG.JFETTo
Only the effect of reducing, other RDRIDoes not decrease
Because RONSThe rate of decrease was low. That is, the element
R is not always impairedONSCan be reduced
There wasn't.
【０００８】そこで、この発明の目的は、素子の耐圧を
損なわずに単位面積当たりのオン抵抗ＲONS をよりいっ
そう低減することができる縦型絶縁ゲート電界効果トラ
ンジスタを提供することにある。Therefore, an object of the present invention is to provide a vertical insulated gate field effect transistor capable of further reducing the on-resistance R ONS per unit area without impairing the breakdown voltage of the device.
【０００９】[0009]
【課題を解決するための手段】この発明は、半導体基板
の表面部に第１導電型のソース領域と第２導電型のウエ
ル領域とが形成され、半導体基板内に第１導電型のドレ
イン領域が形成されるとともに前記ウエル領域と前記ド
レイン領域との間にドレイン領域あるいはソース領域に
比較して低い不純物濃度の第１導電型のドリフト領域が
形成された縦型絶縁ゲート電界効果トランジスタにおい
て、隣接するウエル領域の間の半導体基板に両ウエル領
域とは離間して溝を形成し、この溝内に絶縁膜を介して
前記ドリフト領域の溝壁に沿った表面の多数キャリア濃
度を増加させる電位の電極を配置した縦型絶縁ゲート電
界効果トランジスタをその要旨とするものである。According to the present invention, a source region of a first conductivity type and a well region of a second conductivity type are formed in a surface portion of a semiconductor substrate, and a drain region of the first conductivity type is formed in the semiconductor substrate. And a drain region of the first conductivity type having an impurity concentration lower than that of the drain region or the source region is formed between the well region and the drain region. A groove is formed in the semiconductor substrate between the well regions to be separated from both well regions, and a potential for increasing the majority carrier concentration on the surface along the groove wall of the drift region is formed in the groove via an insulating film. The gist of the invention is a vertical insulated gate field effect transistor in which electrodes are arranged.
【００１０】[0010]
【作用】上述のように溝内の電極はドリフト領域の溝壁
に沿った表面の多数キャリア濃度を増加させる電位とさ
れている。例えば、第１導電型がｎ型の場合は高い電位
に設定されるもので、溝の外側の側壁に電子が誘起しキ
ャリア濃度が上がる。そして、トランジスタのオン状態
においては、溝の外側の側壁部分に低抵抗の電流経路が
できる。この電流経路はウエル領域とドリフト領域の境
界部分からドリフト領域に向かって空乏層が拡がってき
ても、それには影響されない。その結果、ＪＦＥＴの効
果が作用する領域の抵抗ＲJFETとドリフト領域の抵抗Ｒ
DRI とが減少する。一方、図１２に示す従来装置では高
濃度不純物層８の存在によりリーチスルー耐圧を考慮す
る必要があったが、本装置ではそれが不要となる。As described above, the electrode in the groove is set to a potential that increases the majority carrier concentration on the surface along the groove wall of the drift region. For example, when the first conductivity type is n-type, a high potential is set, and electrons are induced on the outer sidewall of the groove to increase the carrier concentration. Then, when the transistor is on, a low resistance current path is formed on the side wall portion outside the groove. This current path is not affected by the depletion layer extending from the boundary between the well region and the drift region toward the drift region. As a result, the resistance of the resistor R JFET and the drift region of a region where the effect of the JFET acts R
DRI and decreases. On the other hand, in the conventional device shown in FIG. 12, the reach-through breakdown voltage had to be taken into consideration due to the existence of the high-concentration impurity layer 8, but this device does not need it.
【００１１】[0011]
【実施例】以下、この発明を具体化した一実施例を図面
に従って説明する。図１に本実施例の縦型ＭＯＳＦＥＴ
の断面図を示す。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a vertical MOSFET of this embodiment.
FIG.
【００１２】半導体基板１０の表面部にｐ型ウエル領域
１１が形成され、そのｐ型ウエル領域１１内の一部にｎ
+ 型ソース領域１２及びｐ+ 型ウエルコンタクト領域１
３が形成されている。又、半導体基板１０内での裏面側
にはｎ+ 型ドレイン領域１４が形成されている。さら
に、ｐ型ウエル領域１１とｎ+ 型ドレイン領域１４との
間には、ｎ+ 型ドレイン領域１４あるいはｎ+ 型ソース
領域１２に比較して低い不純物濃度のｎ- 型ドリフト領
域１５が形成されている。A p-type well region 11 is formed on the surface of the semiconductor substrate 10, and n is formed in a part of the p-type well region 11.
+ Type source region 12 and p + type well contact region 1
3 is formed. Further, an n + type drain region 14 is formed on the back surface side in the semiconductor substrate 10. Further, an n − type drift region 15 having a lower impurity concentration than the n + type drain region 14 or the n + type source region 12 is formed between the p type well region 11 and the n + type drain region 14. ing.
【００１３】半導体基板１０の表面におけるｐ型ウエル
領域１１に挟まれた領域には、ｐ型ウエル領域１１と離
間して溝１６が形成され、この溝１６はｎ- 型ドリフト
領域１５を貫通してｎ+ 型ドレイン領域１４の表面に至
っている。半導体基板１０の表面、及び溝１６の内壁に
は絶縁膜としてのゲート酸化膜１７が形成され、このゲ
ート酸化膜１７を介して溝１６内に延びるゲート電極１
８が配置されている。A groove 16 is formed in a region sandwiched by the p-type well regions 11 on the surface of the semiconductor substrate 10 so as to be separated from the p-type well region 11, and the groove 16 penetrates the n -- type drift region 15. Reach the surface of the n + type drain region 14. A gate oxide film 17 as an insulating film is formed on the surface of the semiconductor substrate 10 and the inner wall of the groove 16, and the gate electrode 1 extending into the groove 16 through the gate oxide film 17.
8 are arranged.
【００１４】又、半導体基板１０の裏面には裏面電極１
９が形成されている。このトランジスタは次のように製
造される。つまり、ｎ+ 型半導体基板（ドレイン領域１
４）上にｎ- 型エピタキシャル層を形成し、そのエピタ
キシャル層に対しドレイン領域１４に至る溝１６を形成
する。そして、ゲート酸化膜１７を介してゲート電極１
８を配置する。さらに、このゲート電極１８をマスクと
してｐ型ウエル領域１１及びｎ+ 型ソース領域１２を二
重拡散にて形成する。その後に、所定のマスクパターン
を用いてｐ+ 型ウエルコンタクト領域１３を形成する。
一方、ｎ+ 型半導体基板（ドレイン領域１４）の裏面に
裏面電極１９を形成する。On the back surface of the semiconductor substrate 10, a back surface electrode 1 is provided.
9 is formed. This transistor is manufactured as follows. That is, the n + type semiconductor substrate (drain region 1
4) An n − type epitaxial layer is formed on the epitaxial layer, and a groove 16 reaching the drain region 14 is formed in the epitaxial layer. Then, the gate electrode 1 is formed through the gate oxide film 17.
Place 8 Further, using the gate electrode 18 as a mask, the p-type well region 11 and the n + type source region 12 are formed by double diffusion. After that, the p + type well contact region 13 is formed using a predetermined mask pattern.
On the other hand, the back surface electrode 19 is formed on the back surface of the n + type semiconductor substrate (drain region 14).
【００１５】そして、ｎ+ 型ソース領域１２及びｐ+ 型
ウエルコンタクト領域１３にはソース端子Ｓが接続さ
れ、ゲート電極１８にはゲート端子Ｇが接続され、さら
に、裏面電極１９にはドレイン端子Ｄが接続される。A source terminal S is connected to the n + type source region 12 and the p + type well contact region 13, a gate terminal G is connected to the gate electrode 18, and a drain terminal D is connected to the back surface electrode 19. Are connected.
【００１６】このような縦型絶縁ゲート電界効果トラン
ジスタをオン状態、即ち、ソース端子Ｓを接地、ドレイ
ン端子Ｄ及びゲート端子Ｇに正電圧を印加すると、図２
に示すように溝１６の外側の側壁に電子が誘起しキャリ
ア濃度が上がり、この部分に低抵抗の電流経路ができ
る。When such a vertical insulated gate field effect transistor is turned on, that is, when the source terminal S is grounded and a positive voltage is applied to the drain terminal D and the gate terminal G, FIG.
As shown in FIG. 5, electrons are induced on the outer side wall of the groove 16 to increase the carrier concentration, and a low resistance current path is formed in this portion.
【００１７】そして、この電流経路は、ｐ型ウエル領域
１１とｎ- 型ドリフト領域１５との境界部分からｎ- 型
ドリフト領域１５に向かって空乏層が拡がってきても、
それには影響されない。In this current path, even if the depletion layer expands from the boundary portion between the p type well region 11 and the n − type drift region 15 toward the n − type drift region 15,
Not affected by it.
【００１８】結果としてＪＦＥＴの効果が作用する領域
の抵抗ＲJFETとｎ- 型ドリフト領域１５の抵抗ＲDRI を
減少させることができる。その結果をシュミレーション
計算すると、図３のようになる。この図から、溝１６の
外側の側壁に電流経路が確認された。As a result, the resistance R JFET in the region where the effect of the JFET acts and the resistance R DRI of the n − type drift region 15 can be reduced. The result of simulation calculation is as shown in FIG. From this figure, a current path was confirmed on the outer sidewall of the groove 16.
【００１９】又、シュミレーション計算により、図９に
示す従来のセルにおけるソース・ドレイン間のオン抵抗
ＲCELLと比較したところ、Further, by comparison with the on-resistance R CELL between the source and drain in the conventional cell shown in FIG. 9 by simulation calculation,
【００２０】[0020]
【数１】 [Equation 1]
【００２１】という結果が得られた。この計算におい
て、セルサイズＬ1 ＝１６μｍ、Ｌ3 ＝８μｍ、溝幅＝
２μｍ、拡散層プロファイルは図９と図１で同じであ
る。The result was obtained. In this calculation, cell size L1 = 16 μm, L3 = 8 μm, groove width =
2 μm, the diffusion layer profile is the same in FIG. 9 and FIG.
【００２２】又、本実施例でのソース・ドレイン間耐圧
は、図４においてＢで示すように、溝側壁の電位等高線
が密となる高電界強度部分によって決まる（ここでブレ
ークダウンする）。つまり、耐圧はｐ型ウエル領域１１
と溝１６との距離には関係無くなる。故に、隣接するウ
エル領域１１との間隔Ｌ3 を溝１６の幅まで小さくでき
る。Further, the source-drain breakdown voltage in this embodiment is determined by a high electric field strength portion where the potential contour lines on the side wall of the groove are dense (breakdown here), as indicated by B in FIG. That is, the breakdown voltage is the p-type well region 11
The distance between the groove 16 and the groove 16 is irrelevant. Therefore, the distance L3 between the adjacent well regions 11 can be reduced to the width of the groove 16.
【００２３】さらに、より高耐圧の構造にするには図５
に示すように、溝１６内に配置した上下方向に延びる電
極２１と左右方向に延びるゲート電極２２とを、別部材
とし、電極２１とドレイン端子Ｄとを抵抗２３を介して
接続する。このように、ドレイン端子Ｄと溝内電極２１
との間の電位差を一定値内にする。この図５のようにす
ると、溝１６内の電極２１の電位は図１でのゲート電極
１８より高くなるので、耐圧は溝側壁の電界強度では決
まらず、ｐ型ウエル領域１１からｎ+ 型ドレイン領域１
４へのリーチスルー耐圧又は、溝１６内の酸化膜１７の
耐圧によって決まる。Further, in order to obtain a structure having a higher withstand voltage, FIG.
As shown in FIG. 3, the electrode 21 extending in the vertical direction and the gate electrode 22 extending in the horizontal direction arranged in the groove 16 are separate members, and the electrode 21 and the drain terminal D are connected via the resistor 23. In this way, the drain terminal D and the in-groove electrode 21
The potential difference between and is within a constant value. According to this FIG. 5, the potential of the electrode 21 in the groove 16 becomes higher than that of the gate electrode 18 in FIG. 1, so that the breakdown voltage is not determined by the electric field strength on the side wall of the groove, and the p + well region 11 to the n + -type drain Area 1
4 is determined by the reach-through breakdown voltage to 4 or the breakdown voltage of the oxide film 17 in the groove 16.
【００２４】尚、本実施例では、ＵＭＯＳのように溝１
６の側壁にチャネルは形成されず、あくまでもウエハ上
面にチャネルが形成される。こうすることにより、溝１
６の側壁の結晶欠陥部分にチャネルが無くｐｎ接合部で
のリーク電流を抑制することができるとともに、図５に
示すような耐圧設計をしやすい構造とすることができ
る。In this embodiment, the groove 1 is used like UMOS.
No channel is formed on the side wall of 6, and only a channel is formed on the upper surface of the wafer. By doing this, groove 1
Since there is no channel in the crystal defect portion on the side wall of No. 6, a leak current at the pn junction can be suppressed, and a withstand voltage design as shown in FIG. 5 can be easily made.
【００２５】このように本実施例では、隣接するｐ型ウ
エル領域１１の間の半導体基板１０に両ウエル領域１１
とは離間して溝１６を形成し、この溝１６内にゲート酸
化膜１７（絶縁膜）を介してドリフト領域１５より高い
電位のゲート電極１８を配置したので、トランジスタを
オン状態（ソース端子Ｓを接地、ドレイン端子Ｄ及びゲ
ート端子Ｇに正電圧）にすると、溝１６の外側の側壁に
電子が誘起しキャリア濃度が上がり、この部分に低抵抗
の電流経路ができる。そして、この電流経路はウエル領
域１１とドリフト領域１５の境界部分からドリフト領域
１５に向かって空乏層が拡がってきても、それには影響
されない。その結果、ＪＦＥＴの効果が作用する領域の
抵抗ＲJFETとドリフト領域の抵抗ＲDRI とが減少する。
一方、図１２に示す従来装置では高濃度不純物層８の存
在によりリーチスルー耐圧を考慮する必要があったが、
本装置ではそれが不要となり、素子の耐圧を損なわずに
単位面積当たりのオン抵抗ＲONS をよりいっそう低減す
ることができることとなる。As described above, in this embodiment, both well regions 11 are formed in the semiconductor substrate 10 between the adjacent p-type well regions 11.
Since the groove 16 is formed apart from the gate electrode 18 and the gate electrode 18 having a potential higher than that of the drift region 15 is arranged in the groove 16 via the gate oxide film 17 (insulating film), the transistor is turned on (source terminal S Is grounded and a positive voltage is applied to the drain terminal D and the gate terminal G, electrons are induced on the outer sidewall of the groove 16 to increase the carrier concentration, and a low resistance current path is formed in this portion. Even if the depletion layer expands from the boundary between the well region 11 and the drift region 15 toward the drift region 15, this current path is not affected by it. As a result, the resistance R JFET in the region where the JFET effect acts and the resistance R DRI in the drift region decrease.
On the other hand, in the conventional device shown in FIG. 12, it is necessary to consider the reach-through breakdown voltage due to the existence of the high-concentration impurity layer 8.
This device does not need it, and the ON resistance R ONS per unit area can be further reduced without impairing the breakdown voltage of the element.
【００２６】尚、この発明は上記実施例に限定されるも
のではなく、例えば、耐圧設計のやり方として、図６に
示すように溝１６の深さをウエル領域１１よりも浅く
し、ウエル領域１１からドリフト領域１５へ伸びる空乏
層を溝１６の下でピンチオフさせる。この場合のブレー
クダウン時のポテンシャル分布図を図７に示す。つま
り、溝１６の両側にあるウエル領域１１から伸びる空乏
層が溝１６の下でつながるようにする。そして、溝深さ
を調節することで溝底エッジ部（図７でのＢで示す）で
の電界強度を変えて、ここで耐圧を決める。この場合、
耐圧３０ボルト（図１の構造）から５０ボルト前後に向
上することができる。The present invention is not limited to the above-described embodiment. For example, as a method of withstanding voltage design, the depth of the groove 16 is made shallower than the well region 11 as shown in FIG. The depletion layer extending from the drift region 15 to the drift region 15 is pinched off under the groove 16. FIG. 7 shows a potential distribution diagram at the time of breakdown in this case. That is, the depletion layers extending from the well regions 11 on both sides of the groove 16 are connected under the groove 16. Then, by adjusting the groove depth, the electric field strength at the groove bottom edge portion (shown by B in FIG. 7) is changed, and the breakdown voltage is determined here. in this case,
The withstand voltage can be increased from 30 volts (structure of FIG. 1) to around 50 volts.
【００２７】又、オン抵抗に関してはRegarding the on-resistance,
【００２８】[0028]
【数２】 [Equation 2]
【００２９】となる。又、他の態様として図８に示すよ
うに溝１６の底部に高濃度ｎ+ 低抵抗領域２０を配置し
てもよい。この場合には、図６に示すトランジスタにお
けるＲDRI をも低減することができる。It becomes As another mode, as shown in FIG. 8, a high concentration n + low resistance region 20 may be arranged at the bottom of the groove 16. In this case, R DRI in the transistor shown in FIG. 6 can also be reduced.
【００３０】以上、本発明をｎチャネル型ＭＯＳＦＥＴ
に採用した場合を例にとって示したが、ｐチャネル型Ｍ
ＯＳＦＥＴに採用するようにしてもよい。その場合、ド
リフト領域（ｐ- 型）の溝壁には正孔を誘起するように
するもので、溝部の電極はドリフト領域より低い電位に
設定される。As described above, the present invention is applied to the n-channel MOSFET.
The case where it is adopted as an example is shown, but the p-channel type M
It may be adopted for the OSFET. In that case, holes are induced in the groove wall of the drift region (p − type), and the electrode of the groove portion is set to a potential lower than that of the drift region.
【００３１】[0031]
【発明の効果】以上詳述したようにこの発明によれば、
素子の耐圧を損なわずに単位面積当たりのオン抵抗Ｒ
ONS をよりいっそう低減することができる優れた効果を
発揮する。As described in detail above, according to the present invention,
On-resistance R per unit area without impairing the breakdown voltage of the element
Exhibits an excellent effect that can further reduce ONS .
【図１】実施例の縦型ＭＯＳＦＥＴの断面を示す図であ
る。FIG. 1 is a view showing a cross section of a vertical MOSFET of an example.
【図２】溝側壁付近のｎ- 領域のバンド図である。FIG. 2 is a band diagram of an n − region near a groove sidewall.
【図３】トランジスタ・オン時のポテンシャル分布及び
電流ベクトルを示す図である。FIG. 3 is a diagram showing a potential distribution and a current vector when a transistor is turned on.
【図４】ブレークダウン時のポテンシャル分布及び電流
ベクトルを示す図である。FIG. 4 is a diagram showing a potential distribution and a current vector at the time of breakdown.
【図５】実施例の縦型ＭＯＳＦＥＴの応用例を示す断面
図である。FIG. 5 is a cross-sectional view showing an application example of the vertical MOSFET of the embodiment.
【図６】別例の縦型ＭＯＳＦＥＴの断面を示す図であ
る。FIG. 6 is a view showing a cross section of another vertical MOSFET.
【図７】ブレークダウン時のポテンシャル分布及び電流
ベクトルを示す図である。FIG. 7 is a diagram showing a potential distribution and a current vector at the time of breakdown.
【図８】他の別例の縦型ＭＯＳＦＥＴの断面を示す図で
ある。FIG. 8 is a view showing a cross section of another vertical MOSFET of another example.
【図９】従来の縦型ＭＯＳＦＥＴの断面図である。FIG. 9 is a cross-sectional view of a conventional vertical MOSFET.
【図１０】従来の縦型ＭＯＳＦＥＴの電流通路と抵抗成
分を示す図である。FIG. 10 is a diagram showing a current path and a resistance component of a conventional vertical MOSFET.
【図１１】ウエル間隔とＲONS との関係を示す図であ
る。FIG. 11 is a diagram showing a relationship between well intervals and R ONS .
【図１２】従来の縦型ＭＯＳＦＥＴの断面図である。FIG. 12 is a cross-sectional view of a conventional vertical MOSFET.
１１ ｐ型ウエル領域 １２ ｎ+ 型ソース領域 １４ ｎ+ 型ドレイン領域 １５ ｎ- 型ドリフト領域 １６ 溝 １７ 絶縁膜としてのゲート酸化膜 １８ ゲート電極11 p-type well region 12 n + type source region 14 n + type drain region 15 n − type drift region 16 groove 17 gate oxide film as insulating film 18 gate electrode
Claims (1)
ス領域と第２導電型のウエル領域とが形成され、半導体
基板内に第１導電型のドレイン領域が形成されるととも
に前記ウエル領域と前記ドレイン領域との間にドレイン
領域あるいはソース領域に比較して低い不純物濃度の第
１導電型のドリフト領域が形成された縦型絶縁ゲート電
界効果トランジスタにおいて、 隣接するウエル領域の間の半導体基板に両ウエル領域と
は離間して溝を形成し、この溝内に絶縁膜を介して前記
ドリフト領域の溝壁に沿った表面の多数キャリア濃度を
増加させる電位の電極を配置したことを特徴とする縦型
絶縁ゲート電界効果トランジスタ。1. A source region of a first conductivity type and a well region of a second conductivity type are formed on the surface of a semiconductor substrate, a drain region of the first conductivity type is formed in the semiconductor substrate, and the well region is formed. A vertical insulated gate field effect transistor in which a drift region of the first conductivity type having a lower impurity concentration than the drain region or the source region is formed between the drain region and the drain region, and a semiconductor substrate between adjacent well regions. A groove is formed apart from both well regions, and an electrode having a potential for increasing the majority carrier concentration on the surface along the groove wall of the drift region is arranged in the groove via an insulating film. Vertical insulated gate field effect transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4147714A JPH05343691A (en) | 1992-06-08 | 1992-06-08 | Vertical insulated-gate field-effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4147714A JPH05343691A (en) | 1992-06-08 | 1992-06-08 | Vertical insulated-gate field-effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05343691A true JPH05343691A (en) | 1993-12-24 |
Family
ID=15436544
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4147714A Pending JPH05343691A (en) | 1992-06-08 | 1992-06-08 | Vertical insulated-gate field-effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05343691A (en) |
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| WO2004032243A1 (en) * | 2002-10-04 | 2004-04-15 | Koninklijke Philips Electronics N.V. | Power semiconductor devices |
| JP2005079173A (en) * | 2003-08-28 | 2005-03-24 | Nec Electronics Corp | Semiconductor device |
| WO2005045937A3 (en) * | 2003-11-06 | 2005-08-11 | Koninkl Philips Electronics Nv | Insulated gate field-effect transistor |
| JP2006156962A (en) * | 2004-11-08 | 2006-06-15 | Denso Corp | Silicon carbide semiconductor device and its manufacturing method |
| JP2007088010A (en) * | 2005-09-20 | 2007-04-05 | Denso Corp | Semiconductor device and its manufacturing method |
| JP2008235546A (en) * | 2007-03-20 | 2008-10-02 | Denso Corp | Silicon carbide semiconductor device and manufacturing method therefor |
| JP2010192691A (en) * | 2009-02-18 | 2010-09-02 | Rohm Co Ltd | Semiconductor device |
| JP2011124576A (en) * | 2009-12-09 | 2011-06-23 | Infineon Technologies Austria Ag | Semiconductor device with improved on-resistance value |
| JP2013214773A (en) * | 2008-09-30 | 2013-10-17 | Infineon Technologies Austria Ag | Semiconductor device structure having vertical dielectric layer |
| CN103545371A (en) * | 2012-07-11 | 2014-01-29 | 台湾积体电路制造股份有限公司 | Apparatus and method for power MOS transistor |
| JP2017118024A (en) * | 2015-12-25 | 2017-06-29 | 株式会社豊田中央研究所 | Silicon carbide semiconductor device |
| JPWO2016067374A1 (en) * | 2014-10-29 | 2017-08-17 | 株式会社日立製作所 | Semiconductor device, power module, and power conversion device |
| US11152502B2 (en) | 2019-05-17 | 2021-10-19 | Fuji Electric Co., Ltd. | Nitride semiconductor device |
-
1992
- 1992-06-08 JP JP4147714A patent/JPH05343691A/en active Pending
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|---|---|---|---|---|
| WO1998004004A1 (en) * | 1996-07-19 | 1998-01-29 | Siliconix Incorporated | High density trench dmos transistor with trench bottom implant |
| WO2004032243A1 (en) * | 2002-10-04 | 2004-04-15 | Koninklijke Philips Electronics N.V. | Power semiconductor devices |
| JP2005079173A (en) * | 2003-08-28 | 2005-03-24 | Nec Electronics Corp | Semiconductor device |
| WO2005045937A3 (en) * | 2003-11-06 | 2005-08-11 | Koninkl Philips Electronics Nv | Insulated gate field-effect transistor |
| US7642596B2 (en) | 2003-11-06 | 2010-01-05 | Nxp B.V. | Insulated gate field effect transistor |
| JP2006156962A (en) * | 2004-11-08 | 2006-06-15 | Denso Corp | Silicon carbide semiconductor device and its manufacturing method |
| JP2007088010A (en) * | 2005-09-20 | 2007-04-05 | Denso Corp | Semiconductor device and its manufacturing method |
| US8022414B2 (en) | 2007-03-20 | 2011-09-20 | Denso Corporation | Silicon carbide semiconductor device, and method of manufacturing the same |
| JP2008235546A (en) * | 2007-03-20 | 2008-10-02 | Denso Corp | Silicon carbide semiconductor device and manufacturing method therefor |
| JP2013214773A (en) * | 2008-09-30 | 2013-10-17 | Infineon Technologies Austria Ag | Semiconductor device structure having vertical dielectric layer |
| JP2010192691A (en) * | 2009-02-18 | 2010-09-02 | Rohm Co Ltd | Semiconductor device |
| JP2011124576A (en) * | 2009-12-09 | 2011-06-23 | Infineon Technologies Austria Ag | Semiconductor device with improved on-resistance value |
| CN103545371A (en) * | 2012-07-11 | 2014-01-29 | 台湾积体电路制造股份有限公司 | Apparatus and method for power MOS transistor |
| JPWO2016067374A1 (en) * | 2014-10-29 | 2017-08-17 | 株式会社日立製作所 | Semiconductor device, power module, and power conversion device |
| JP2017118024A (en) * | 2015-12-25 | 2017-06-29 | 株式会社豊田中央研究所 | Silicon carbide semiconductor device |
| US11152502B2 (en) | 2019-05-17 | 2021-10-19 | Fuji Electric Co., Ltd. | Nitride semiconductor device |
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