JPS63254769A - Vertical insulated-gate type field effect transistor - Google Patents
Vertical insulated-gate type field effect transistorInfo
- Publication number
- JPS63254769A JPS63254769A JP62088838A JP8883887A JPS63254769A JP S63254769 A JPS63254769 A JP S63254769A JP 62088838 A JP62088838 A JP 62088838A JP 8883887 A JP8883887 A JP 8883887A JP S63254769 A JPS63254769 A JP S63254769A
- Authority
- JP
- Japan
- Prior art keywords
- groove
- drift region
- region
- resistance
- semiconductor substrate
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- Pending
Links
- 230000005669 field effect Effects 0.000 title claims description 8
- 239000012535 impurity Substances 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 239000004065 semiconductor Substances 0.000 claims abstract description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 230000015556 catabolic process Effects 0.000 abstract description 8
- 238000009792 diffusion process Methods 0.000 abstract description 3
- 230000003247 decreasing effect Effects 0.000 abstract 2
- 210000000746 body region Anatomy 0.000 abstract 1
- 238000003754 machining Methods 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 10
- 239000010410 layer Substances 0.000 description 9
- 238000000034 method Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 239000003513 alkali Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0878—Impurity concentration or distribution
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は絶縁ゲート電界効果トランジスタに係り、特に
高耐圧化、低オン抵抗化、かつ高集積化に好適な絶縁ゲ
ート電界効果トランジスタに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an insulated gate field effect transistor, and particularly to an insulated gate field effect transistor that is suitable for high breakdown voltage, low on-resistance, and high integration.
従来電力用のＮ０５ＦＥＴについては、第２図に示す様
な縦型２重拡散ＭＯ５ＦＥＴ （以下ＶＤＭＯ３と呼ぶ
）の構造がとられる場合が多かった。この構造はチャネ
ル導電型がｎの場合、素子が形成される半導体基板の表
面にＰ型不純物がドープされたウェルがあり、ウェル内
には高濃度のｎ型不純物でドープされたソースが形成さ
れている。ｎ型不純物が高濃度にドープされたドレイン
領域は素子の耐圧に応じて一定の深さに形成される。ウ
ェルと高濃度のドレイン領域にはさまれた部分は比較的
低濃度のｎ型不純物が導入されておりドリフト領域と呼
ばれる。この素子のソース、ドレイン間耐圧はドリフト
領域の厚さおよび濃度によって決まり、所期の耐圧に見
合う様な厚さと濃度に設定される。Conventional power N05FETs have often had a vertical double diffusion MO5FET (hereinafter referred to as VDMO3) structure as shown in FIG. In this structure, when the channel conductivity type is n, there is a well doped with P-type impurities on the surface of the semiconductor substrate on which the device is formed, and a source doped with a high concentration of n-type impurities is formed inside the well. ing. The drain region heavily doped with n-type impurities is formed to a constant depth depending on the breakdown voltage of the device. A portion sandwiched between the well and the high concentration drain region is doped with a relatively low concentration of n-type impurity and is called a drift region. The breakdown voltage between the source and drain of this element is determined by the thickness and concentration of the drift region, and the thickness and concentration are set to match the desired breakdown voltage.
ウェルの上部に配置されたゲートに電圧が印加されると
ウェル内の半導体基板表面にはｎ型反転層が形成されソ
ースとドレインの間に電流が流れる。When a voltage is applied to the gate disposed above the well, an n-type inversion layer is formed on the surface of the semiconductor substrate within the well, and a current flows between the source and drain.
実際のＶＤＭＯＳでは第２図中にＡで示した部分（セル
）が繰り返し配置されひとつのＶＤＭＯＳを構成してい
る。Ａの寸法ａは製造プロセス上あるいは素子特性上許
容される限り小さく設計される。こうすることにより単
位面積当りに含まれる電流通路の数を最大にすることが
できる。In an actual VDMOS, the portions (cells) indicated by A in FIG. 2 are repeatedly arranged to constitute one VDMOS. The dimension a of A is designed to be as small as possible in terms of manufacturing process or device characteristics. By doing so, the number of current paths included per unit area can be maximized.
電力用ＭＯ５ＦＥＴにおける重要な特性のひとつとして
素子面積をオン抵抗の積（以下Ｒｏｎｓと呼ぶ）がある
。一定の素子面積で比較した場合この値が小さい程電流
を流したときのソース、ドレイン間の電圧降下が小さく
、素子で消費される電力を小さくすることができる。Ｒ
ｏｎｓを下げるには素子自身の抵抗を下げるか、素子面
積を縮小する必要がある。One of the important characteristics of a power MO5FET is the product of the element area and the on-resistance (hereinafter referred to as Rons). When compared for a fixed element area, the smaller this value is, the smaller the voltage drop between the source and drain will be when current flows, and the power consumed by the element can be reduced. R
In order to lower ons, it is necessary to lower the resistance of the element itself or reduce the element area.
第３図に示した斜線部はドリフト領域内の電流の通路を
示している。基板表面から深さ方向に見るとウェル１３
にはさまれた領域がせまくなってネックとなった後ドレ
ン１２に向かって広がっていることがわかる。ネックが
形成されるのは半導体基板の縦方向に寄生的にできる接
合型電界効果トランジスタ（以後Ｊ ＦＥＴと呼ぶ）の
効果によるものである。つまりドリフト領域に電流が流
れるとドリフト領域の抵抗成分により電流通路にそって
電位差が生じ、接地電位に固定されたソース１２および
ウェル１３とドリフト領域１１の間の電位差によりウェ
ルとドリフト領域の間の接合が逆バイアスされ、比較的
不純物濃度の低いドリフト領域側に空乏層が拡がって電
流通路がせばめられるものである。このＪ ＦＥＴの効
果はドレイン印加電圧が高い程、またドレイン電流が大
きい程顕著になる。このＪＦＥＴの効果が作用する領域
の抵抗をＲＪＦとする。ＶＤＭＯＳにおけるソース端子
Ｓとドレイン端子り間の抵抗はＲＪＦの他にソース領域
の抵抗Ｒｓ 、チャネル抵抗Ｒｃ 、ドリフト領域の抵
抗Ｒｏによって表わすことができる。The shaded area shown in FIG. 3 indicates the current path within the drift region. Well 13 when viewed from the substrate surface in the depth direction
It can be seen that the area sandwiched between the drains becomes narrow and becomes a neck, and then widens toward the drain 12. The neck is formed due to the effect of a junction field effect transistor (hereinafter referred to as JFET) that is parasitic formed in the vertical direction of the semiconductor substrate. In other words, when a current flows through the drift region, a potential difference is generated along the current path due to the resistance component of the drift region, and the potential difference between the source 12 and well 13 fixed at ground potential and the drift region 11 causes a voltage difference between the well and the drift region. The junction is reverse biased, the depletion layer expands toward the drift region side where the impurity concentration is relatively low, and the current path narrows. This effect of the J FET becomes more pronounced as the voltage applied to the drain becomes higher and as the drain current becomes larger. Let RJF be the resistance in the region where the effect of this JFET acts. The resistance between the source terminal S and the drain terminal in VDMOS can be expressed by the resistance Rs of the source region, the channel resistance Rc, and the resistance Ro of the drift region, in addition to RJF.
上記従来技術はソース、ドレイン間の耐圧を維持した上
でオン抵抗の増加を招かずに素子面積を減少させること
は困難であった。In the above-mentioned conventional technology, it is difficult to reduce the element area without increasing the on-resistance while maintaining the breakdown voltage between the source and drain.
第３図に示した隣接するゲートの間の距離Ｓはソース１
４およびウェル１３の電位を与えるためのｐ型窩濃度層
１５と配線の接触をとるためのスペースである。Ｓは素
子を形成するプロセスの加工精度に依存するもので製造
装置やプロセスを特定すれば決まってしまい、減らすこ
とはできない。The distance S between adjacent gates shown in FIG.
This is a space for making wiring contact with the p-type cavity concentration layer 15 for applying a potential to the well 4 and the well 13. S depends on the processing accuracy of the process for forming the element, and is determined by specifying the manufacturing equipment and process, and cannot be reduced.
次にウェル間隔Ｑを変化させた場合を考える。Ｑに対す
る素子面積とオン抵抗の褌の関係を第７図に示す。Ωの
小さい範囲では第４図に示す様にＪ ＦＥＴの効果によ
る電流通路のネックがさらに細くなりＲＪＦが増大して
Ｒｏｎｓは増加する。Ｑを大きくするとＪ ＦＥＴの効
果が弱くなるかわりに面積が不必要に増えてしまいＲｏ
ｎｓはやはり増加する。結果として第５図の様にＱの設
計値として最適値が存在し、この点に対するＲｏｎｓを
下げるには耐圧の仕様を下げるか、より微細なパターン
を加工できるプロセスを採用する必要があった。Next, consider the case where the well spacing Q is changed. The relationship between element area and on-resistance loincloth with respect to Q is shown in FIG. In a small range of Ω, as shown in FIG. 4, the neck of the current path due to the effect of the J FET becomes narrower, RJF increases, and Rons increases. When Q is increased, the effect of J FET becomes weaker, but the area increases unnecessarily and Ro
ns also increases. As a result, as shown in FIG. 5, there exists an optimum value as the design value of Q, and in order to lower Rons at this point, it was necessary to lower the breakdown voltage specifications or adopt a process that can process finer patterns.
本発明の目的は素子の耐圧を損なわずまた特に進んだ加
工精度を要求することなくＶＤＭＯＳのＲｏｎｓを低減
できる構造を提供することにある。An object of the present invention is to provide a structure that can reduce the Rons of VDMOS without impairing the withstand voltage of the device or requiring particularly advanced processing accuracy.
上記目的は第１図に示す様にウェル１３ではさまれた領
域に溝２０を掘り、この溝周辺の不純物濃度を高くして
この部分の抵抗を下げることにより達成される。The above object is achieved by digging a trench 20 in a region sandwiched by wells 13, as shown in FIG. 1, and increasing the impurity concentration around this trench to lower the resistance of this portion.
第１図においてドリフト領域１１の溝２０に接する部分
は他のドリフト領域に比較して高濃度の不純物が導入さ
れている。従ってウェル−ドリフト領域境界の部分から
ドリフト領域に向かって空乏層が拡がってきても溝周辺
の高濃度不純物層２１は空乏化されず低抵抗の状態を保
つことができる。この様に第１図の構造はＪＦＥＴ効果
によるオン抵抗の増大を抑えることができる。よってウ
ェルの間隔Ｑを短くすることができ、Ｒｏｎｓの低い高
集積可能なＶＤＭＯ５を実現することができる。In FIG. 1, the portion of the drift region 11 in contact with the trench 20 has a higher concentration of impurity introduced than other drift regions. Therefore, even if the depletion layer spreads from the well-drift region boundary toward the drift region, the high concentration impurity layer 21 around the trench is not depleted and can maintain a low resistance state. In this manner, the structure shown in FIG. 1 can suppress an increase in on-resistance due to the JFET effect. Therefore, the distance Q between the wells can be shortened, and a VDMO 5 with low Rons and which can be highly integrated can be realized.
以下、本発明の一実施例を第１図により説明する。 An embodiment of the present invention will be described below with reference to FIG.
半導体基板の第１の表面側から形成された第１導電型の
ドリフト領域１１上に第２の導電型不純物を導入してウ
ェル１３を形成し、ウェル１３内に第１導電型不純物を
高濃度に導入してソース１４を形成する。ウェル端部と
ウェル内に形成されたソースの余裕部分は表面反転チャ
ネルが形成される部分である。ウェル１３から基板深さ
方向に一定深さ離れたところに第１導電型不純物を高濃
度に導入したドレイン１２を形成する。このときウェル
１３とドレイン１２にはさまれたドリフト領域の厚さと
濃度は所期の耐圧を満足する値に設定されねばならない
。チャネルを形成すべきウェル領域にはゲート酸化膜１
６を介してゲート電極１７を形成する。ゲートにしきい
値電圧を越える電圧を印加すると、ウェル表面には反転
チャネルが形成され、このチャネルによってソースとド
リフト領域は電気的に導通状態となる。ウェル１３は内
部に高濃度の第２導電型層１５を形成しこの層を介して
配線１９に接続される。隣接するウェルの間に溝を形成
し、この溝周辺のドリフト領域にドリフト領域と同じ導
電型の不純物を高濃度に導入する。これにより素子がオ
ン状態にあって電流が流れても高濃度２１は空乏化せず
寄生Ｊ ＦＥＴ効果を低減できる。A second conductivity type impurity is introduced onto the first conductivity type drift region 11 formed from the first surface side of the semiconductor substrate to form a well 13, and the first conductivity type impurity is highly concentrated in the well 13. to form the source 14. The edge of the well and the extra portion of the source formed within the well are where a surface inversion channel is formed. A drain 12 into which a first conductivity type impurity is introduced at a high concentration is formed at a certain distance from the well 13 in the depth direction of the substrate. At this time, the thickness and concentration of the drift region sandwiched between the well 13 and the drain 12 must be set to values that satisfy the desired breakdown voltage. A gate oxide film 1 is provided in the well region where the channel is to be formed.
A gate electrode 17 is formed via 6. When a voltage exceeding the threshold voltage is applied to the gate, an inversion channel is formed on the well surface, and the source and drift region are electrically connected through this channel. The well 13 has a highly doped second conductivity type layer 15 formed therein and is connected to the wiring 19 via this layer. A groove is formed between adjacent wells, and impurities of the same conductivity type as the drift region are introduced at a high concentration into the drift region around the groove. As a result, even if the element is in the on state and current flows, the high concentration 21 is not depleted and the parasitic JFET effect can be reduced.
本発明の第２の実施例を第６図に示す。ウェル間の溝の
断面は矩形あるいはＵ型である必要はない。アルカリエ
ッチャントによるエツチング速度の面方位依存性を用い
てＶ型溝としてもよい。A second embodiment of the invention is shown in FIG. The cross-section of the grooves between wells need not be rectangular or U-shaped. A V-shaped groove may be formed by using the surface orientation dependence of the etching rate with an alkali etchant.
本発明の第３の実施例を第６図および第７図に示す。溝
周辺への不純物導入法としてゲート電極からの拡散を利
用することができる。ゲート電極として高濃度に不純物
をドープした多結晶シリコンを用いたとき、溝内に酸化
膜等を介さず直接半導体基板に接する様に多結晶シリコ
ン膜を形成すれば、ゲート電極に不純物を導入して低抵
抗化する際に同時に溝周囲に高濃度層を形成することが
できる。A third embodiment of the invention is shown in FIGS. 6 and 7. Diffusion from the gate electrode can be used as a method for introducing impurities into the vicinity of the trench. When polycrystalline silicon doped with impurities at a high concentration is used as the gate electrode, if the polycrystalline silicon film is formed in the trench so as to be in direct contact with the semiconductor substrate without intervening an oxide film, impurities can be introduced into the gate electrode. When lowering the resistance, a high concentration layer can be formed around the groove at the same time.
本発明によればＶＤＭＯ８のオン抵抗を増大させること
なくウェル間のスペースを縮小できるためＲｏｓｎを低
減する効果がある。According to the present invention, the space between the wells can be reduced without increasing the on-resistance of the VDMO 8, which has the effect of reducing Rosn.
【図面の簡単な説明】
第１図は本発明を実施したＶＤＭＯ３の断面図、第２図
は従来のＶＤＭＯ８の断面図、第３図、第４図は従来の
ＶＤＭＯ８における電流通路と抵抗成分を示す図、第５
図はウェル間隔ＱとＲｏｓｎの関係を示す図、第６図、
第７図、第８図は本発明の他の実施例にもとづ＜ＶＤＭ
Ｏ８の断面図である。
１１・・・ドリフト領域、１２ ・・・ドレイン、１３
・・・ウェル、１４・・・ソース、１５・・・ウェル電
位引き上げ用高濃度層、１６・・・ゲート酸化膜、１７
・・・ゲート、１８・・・層間絶縁膜、１９・・・配線
、２０・・・溝、２１第１図
沼吐？嗜
１２図
輩３６
第４０
第６凹
竿′７凹[Brief Description of the Drawings] Fig. 1 is a sectional view of a VDMO3 embodying the present invention, Fig. 2 is a sectional view of a conventional VDMO8, and Figs. 3 and 4 show current paths and resistance components in the conventional VDMO8. Figure 5
The figure shows the relationship between well spacing Q and Rosn, FIG.
7 and 8 are based on other embodiments of the present invention
It is a sectional view of O8. 11... Drift region, 12... Drain, 13
... Well, 14... Source, 15... High concentration layer for raising well potential, 16... Gate oxide film, 17
...Gate, 18...Interlayer insulating film, 19...Wiring, 20...Groove, 21 Figure 1 Numatori? 12th figure 36th 40th concave rod '7 concave
Claims (1)
型からなる基体領域、半導体基板内に第１導電型のドレ
イン領域、基体領域とドレイン領域の間にドレイン領域
あるいは基体領域に比較して低い不純物濃度の第１導電
型のドリフト領域を備えた縦型絶縁ゲート電界効果トラ
ンジスタにおいて隣接する基体領域の間の半導体基板に
溝を形成し、この溝の周囲の半導体基板中の第１導電型
不純物の濃度をドリフト領域のそれに比較して高くした
ことを特徴とする縦型絶縁ゲート電界効果トランジスタ
。 ２、特許請求の範囲第１項記載の縦型絶縁ゲート電界効
果トランジスタにおいて、半導体基板に形成する溝の深
さを基体領域の深さ以上にすることを特徴とする縦型絶
縁ゲート電界効果トランジスタ。 ３、特許請求の範囲第１項記載の縦型絶縁ゲート電界効
果トランジスタにおいて、溝周囲の不純物を溝内に形成
した多結晶シリコンから拡散させたことを特徴とする縦
型絶縁ゲート電界効果トランジスタ。[Claims] 1. A base region consisting of a source region of a first conductivity type and a second conductivity type on a semiconductor substrate, a drain region of the first conductivity type within the semiconductor substrate, and a drain region between the base region and the drain region. In a vertical insulated gate field effect transistor having a first conductivity type drift region with a lower impurity concentration than the region or base region, a groove is formed in the semiconductor substrate between adjacent base regions, and a groove is formed around the groove. A vertical insulated gate field effect transistor characterized in that the concentration of a first conductivity type impurity in a semiconductor substrate is higher than that in a drift region. 2. The vertical insulated gate field effect transistor according to claim 1, wherein the depth of the groove formed in the semiconductor substrate is greater than or equal to the depth of the base region. . 3. A vertical insulated gate field effect transistor according to claim 1, characterized in that impurities around the trench are diffused from polycrystalline silicon formed in the trench.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62088838A JPS63254769A (en) | 1987-04-13 | 1987-04-13 | Vertical insulated-gate type field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62088838A JPS63254769A (en) | 1987-04-13 | 1987-04-13 | Vertical insulated-gate type field effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63254769A true JPS63254769A (en) | 1988-10-21 |
Family
ID=13954094
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62088838A Pending JPS63254769A (en) | 1987-04-13 | 1987-04-13 | Vertical insulated-gate type field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63254769A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5460985A (en) * | 1991-07-26 | 1995-10-24 | Ipics Corporation | Production method of a verticle type MOSFET |
| US5504360A (en) * | 1990-09-24 | 1996-04-02 | Nippondenso Co., Ltd. | Vertical type semiconductor device provided with an improved construction to greatly decrease device on-resistance without impairing breakdown |
| US6015737A (en) * | 1991-07-26 | 2000-01-18 | Denso Corporation | Production method of a vertical type MOSFET |
| US6603173B1 (en) | 1991-07-26 | 2003-08-05 | Denso Corporation | Vertical type MOSFET |
| JPWO2016067374A1 (en) * | 2014-10-29 | 2017-08-17 | 株式会社日立製作所 | Semiconductor device, power module, and power conversion device |
-
1987
- 1987-04-13 JP JP62088838A patent/JPS63254769A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5504360A (en) * | 1990-09-24 | 1996-04-02 | Nippondenso Co., Ltd. | Vertical type semiconductor device provided with an improved construction to greatly decrease device on-resistance without impairing breakdown |
| US5460985A (en) * | 1991-07-26 | 1995-10-24 | Ipics Corporation | Production method of a verticle type MOSFET |
| US6015737A (en) * | 1991-07-26 | 2000-01-18 | Denso Corporation | Production method of a vertical type MOSFET |
| US6603173B1 (en) | 1991-07-26 | 2003-08-05 | Denso Corporation | Vertical type MOSFET |
| JPWO2016067374A1 (en) * | 2014-10-29 | 2017-08-17 | 株式会社日立製作所 | Semiconductor device, power module, and power conversion device |
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