JP2017118024A - Silicon carbide semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an art to decrease on-resistance in a silicon carbide semiconductor device adopting a planar gate.SOLUTION: A silicon carbide semiconductor device 1 comprises: a silicon carbide semiconductor substrate 100; a planar gate 30 opposite to a part of a top face 100a of the semiconductor substrate 100; and a trench gate 40 for accumulation provided in a trench TR which extends from the other part of the top face 100a of the semiconductor substrate 100 toward the inside of th semiconductor substrate 100. The planar gate 30 is arranged to oppose a body region 13 which partitions the top face 100a of the semiconductor substrate 100 into a source region 14 and a drift region 12. The trench gate 40 for accumulation is arranged in the semiconductor substrate 100 to oppose the body region 13 across the drift region 12.SELECTED DRAWING: Figure 1

Description

  The technology disclosed in this specification relates to a silicon carbide semiconductor device including a planar gate.

  Development of a semiconductor device using a silicon carbide semiconductor substrate is in progress. Silicon carbide has a higher breakdown field strength than silicon. For this reason, in the silicon carbide semiconductor device, the thickness of the drift region can be reduced while ensuring a desired breakdown voltage. Thereby, extremely low drift resistance is realized in the silicon carbide semiconductor device.

  In the silicon carbide semiconductor device, since the drift resistance is extremely low, the ratio of the channel resistance to the on-resistance is high. For this reason, in the silicon carbide semiconductor device, in order to further reduce the on-resistance, the need for a technique for reducing the channel resistance is increasing.

  For example, Patent Document 1 discloses a technique that employs a planar gate and selects a surface with high carrier mobility on the upper surface of a semiconductor substrate. Thus, Patent Document 1 provides a silicon carbide semiconductor device having a reduced channel resistance.

JP 2010-41021 A

  In the silicon carbide semiconductor device, the channel resistance is reduced by employing a planar gate. However, when a planar gate is employed, the current path of a drift region (also referred to as a JFET portion in this specification) sandwiched between adjacent body regions is narrowed by a depletion layer extending from the body region, and the resistance of this portion is increased. There is a problem.

  An object of the present specification is to provide a technique for reducing on-resistance in a silicon carbide semiconductor device employing a planar gate.

  One embodiment of a semiconductor device disclosed in this specification includes a silicon carbide semiconductor substrate, a planar gate opposed to a part of the upper surface of the semiconductor substrate, and a trench extending from a part of the upper surface of the semiconductor substrate toward the semiconductor substrate. The accumulation trench gate is provided. The semiconductor substrate has a first conductivity type source region, a second conductivity type body region, and a first conductivity type drift region. The source region is exposed on the upper surface of the semiconductor substrate. The body region covers the source region and is exposed on the upper surface of the semiconductor substrate. The drift region covers the body region and is exposed on the upper surface of the semiconductor substrate. The planar gate is disposed on the upper surface of the semiconductor substrate so as to face the body region that separates the source region and the drift region. The accumulation trench gate is disposed in the semiconductor substrate so as to face the body region via the drift region.

  In the silicon carbide semiconductor device of the above embodiment, carriers that have flowed through the inversion layer induced by the planar gate can flow through the accumulation layer induced on the side surface of the accumulation trench gate. Thereby, the silicon carbide semiconductor device of the said embodiment can have a low on-resistance characteristic.

FIG. 3 is a schematic cross-sectional view of the main part of the silicon carbide semiconductor device of the example, corresponding to the II line in FIG. 2. FIG. 2 schematically shows a main part cross-sectional view of the silicon carbide semiconductor device of the example, and is a main part cross-sectional view corresponding to the II-II line of FIG. The principal part top view of the silicon carbide semiconductor device of a modification is shown typically. The principal part sectional view of the silicon carbide semiconductor device of a modification is shown typically. The principal part sectional view of the silicon carbide semiconductor device of a modification is shown typically. The principal part sectional view of the silicon carbide semiconductor device of a modification is shown typically. The principal part sectional view of the silicon carbide semiconductor device of a modification is shown typically. The principal part sectional view of the silicon carbide semiconductor device of a modification is shown typically. The principal part sectional view of the silicon carbide semiconductor device of a modification is shown typically. The principal part sectional view of the silicon carbide semiconductor device of a modification is shown typically. The principal part top view of the silicon carbide semiconductor device of a modification is shown typically.

  The technical features disclosed in this specification will be summarized below. The items described below have technical usefulness independently.

  Examples of the silicon carbide semiconductor device disclosed in this specification include a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and an IGBT (Insulated Gate Bipolar Transistor). One embodiment of these silicon carbide semiconductor devices is provided in a silicon carbide semiconductor substrate, a planar gate facing a part of the upper surface of the semiconductor substrate, and a trench extending from a part of the upper surface of the semiconductor substrate toward the semiconductor substrate. An accumulation trench gate may be provided. The semiconductor substrate may have a first conductivity type source region, a second conductivity type body region, and a first conductivity type drift region. The source region is exposed on the upper surface of the semiconductor substrate. The body region covers the source region and is exposed on the upper surface of the semiconductor substrate. The drift region covers the body region and is exposed on the upper surface of the semiconductor substrate. Thereby, an NPN structure or a PNP structure including a source region, a body region, and a drift region is provided in the upper layer portion of the semiconductor substrate. The planar gate is disposed on the upper surface of the semiconductor substrate so as to face the body region that separates the source region and the drift region. Thus, the planar gate can form an inversion layer in the body region on the upper surface of the semiconductor substrate. The accumulation trench gate is disposed in the semiconductor substrate so as to face the body region via the drift region. Thereby, the accumulation trench gate can form an accumulation layer in the drift region adjacent to the body region.

  In the silicon carbide semiconductor device of the above embodiment, the crystal plane of the upper surface of the semiconductor substrate may be a Si plane. According to this configuration, the presence of carbon (C) is reduced at the junction interface between the upper surface of the semiconductor substrate and the planar gate, and the generation of interface defects can be suppressed.

  In the silicon carbide semiconductor device of the above embodiment, the crystal plane of the side surface of the trench that is in contact with the side surface facing the body region among the side surfaces of the accumulation trench gate may be the a-plane or the m-plane. According to this configuration, the carrier mobility in the accumulation layer formed on the side surface of the accumulation trench gate is increased.

  In the silicon carbide semiconductor device of the above embodiment, the drift region may have a high concentration drift region in contact with the side surface of the accumulation trench gate. The dopant concentration in the high concentration drift region is configured to be higher than the dopant concentration in the portion of the drift region existing below the body region. According to this configuration, the carrier density in the accumulation layer formed on the side surface of the accumulation trench gate is increased.

  In the silicon carbide semiconductor device of the above embodiment, the planar gate and the accumulation trench gate may be integrally formed. According to this configuration, the accumulation layer on the side surface of the accumulation trench gate is formed when the silicon carbide semiconductor device is on, and disappears when the silicon carbide semiconductor device is off. Thus, the timing at which the accumulation layer is formed on the side surface of the accumulation trench gate is synchronized with the switching operation of the silicon carbide semiconductor device, so that the silicon carbide semiconductor device can have low on-resistance and high breakdown voltage characteristics. .

  In the silicon carbide semiconductor device of the above embodiment, the planar gate and the accumulation trench gate may be insulated and separated. The planar gate and the accumulation trench gate can be applied with different voltages. According to this configuration, for example, the on-voltage applied to the accumulation trench gate is adjusted to be lower than the on-voltage applied to the planar gate, thereby reducing the electric field concentration on the bottom surface of the accumulation trench gate.

  In the silicon carbide semiconductor device of the above embodiment, the accumulation trench gate may have a semiconductor portion into which a dopant is introduced and an insulating coating portion that covers the semiconductor portion. In this case, the dopant concentration of the semiconductor portion is configured to decrease as the depth increases along the thickness direction of the semiconductor substrate. According to this configuration, the electric field concentration on the bottom surface of the accumulation trench gate is reduced.

  The silicon carbide semiconductor device of the above embodiment may further include an upper surface electrode in contact with the upper surface of the semiconductor substrate. The source region may have a contact source part and a plurality of protruding source parts. The contact source portion is exposed on the upper surface of the semiconductor substrate and includes a contact surface in contact with the upper surface electrode. The protruding source part is exposed on the upper surface of the semiconductor substrate and protrudes from the contact source part when observed from a direction orthogonal to the upper surface of the semiconductor substrate. The accumulation trench gate is disposed so as to penetrate between adjacent projecting source portions when observed from a direction orthogonal to the upper surface of the semiconductor substrate. According to this configuration, the density of both the inversion layer induced by the planar gate and the accumulation layer induced by the accumulation trench gate increases, and the silicon carbide semiconductor device can have extremely low on-resistance characteristics.

  In the silicon carbide semiconductor device of the above embodiment, the dopant contained in the source region and the drift region may be nitrogen (N), and the dopant contained in the body region may be aluminum (Al). These dopants have low thermal diffusivity in a silicon carbide semiconductor substrate. Therefore, the NPN structure or PNP structure composed of the source region, the body region, and the drift region has a fine layout, and a low channel resistance is realized.

  As shown in FIG. 1, silicon carbide semiconductor device 1 is a power semiconductor element called MOSFET, and includes semiconductor substrate 100, drain electrode 22 in contact with lower surface 100 b of semiconductor substrate 100, and upper surface 100 a of semiconductor substrate 100. For the accumulation provided in the trench TR extending from the part of the upper surface of the semiconductor substrate 100 to the source electrode 24 in contact with the part, the planar gate 30 facing a part of the upper surface 100 a of the semiconductor substrate 100, and the semiconductor substrate 100. A trench gate 40 is provided. The planar gate 30 and the accumulation trench gate 40 are integrally formed, and are configured to have a T-shaped cross section.

  The semiconductor substrate 100 is a silicon carbide substrate made of 4H silicon carbide, and the crystal surface of the upper surface 100a is a {0001} Si surface. As shown in FIG. 1, the semiconductor substrate 100 includes an n-type drain region 11, an n-type drift region 12, a p-type body region 13, an n-type source region 14, and a p-type body contact region 15. .

The drain region 11 is also a base substrate for the later-described drift region 12 to be epitaxially grown, and is exposed to the lower surface 100 b of the semiconductor substrate 100. The drain region 11 is in ohmic contact with the drain electrode 22. In one example, the dopant of the drain region 11 is nitrogen (N), and the dopant concentration is desirably about 1 × 10 ¹⁸ cm ⁻³ or more.

The drift region 12 is provided on the drain region 11, is provided between the drain region 11 and the body region 13, and is configured to cover the body region 13. The drift region 12 is exposed to the upper surface 100 a of the semiconductor substrate 100 between the adjacent body regions 13. A portion of the drift region 12 disposed between the adjacent body regions 13 is referred to as a JFET portion 12A. The drift region 12 is formed by crystal growth from the surface of the drain region 11 using an epitaxial growth technique. Specifically, drift region 12 is crystal-grown from the surface of the silicon carbide substrate after preparing a silicon carbide substrate having a crystal plane of {0001} (corresponding to drain region 11). In one example, the dopant in the drift region is nitrogen (N), and the dopant concentration is desirably about 1 × 10 ¹⁵ to 1 × 10 ¹⁷ cm ⁻³ .

Body region 13 is provided on drift region 12 and is configured to cover source region 14 and body contact region 15. The body region 13 is disposed in the upper layer portion of the semiconductor substrate 100 and is exposed on the upper surface 100 a of the semiconductor substrate 100. The body region 13 is crystal-grown in the trench using an epitaxial growth technique after a trench is formed in the upper layer portion of the semiconductor substrate 100 using a reactive ion etching (RIE) technique. In one example, the dopant in the body region 13 is aluminum (Al), and the dopant concentration is desirably about 1 × 10 ¹⁷ to 1 × 10 ¹⁸ cm ⁻³ .

The source region 14 is provided on the body region 13, is disposed in the upper layer portion of the semiconductor substrate 100, and is exposed on the upper surface 100 a of the semiconductor substrate 100. Source region 14 is separated from drift region 12 by body region 13. The source region 14 is formed by introducing a dopant into the upper layer portion of the semiconductor substrate 100 using an ion implantation technique. In one example, the dopant of the source region 14 is nitrogen (N) or phosphorus (P), the dose is about 1 × 10 ¹³ to 1 × 10 ¹⁵ cm ⁻² , and the peak concentration is about 1 × 10 ¹⁹ to 5 × 10 ²⁰ cm ⁻³ is desirable.

The body contact region 15 is provided on the body region 13, is disposed on the upper layer portion of the semiconductor substrate 100, and is exposed on the upper surface 100 a of the semiconductor substrate 100. The body contact region 15 is in ohmic contact with the source electrode 24. The body contact region 15 is formed by introducing a dopant into the upper layer portion of the semiconductor substrate 100 using an ion implantation technique. In one example, the dopant of the body contact region 15 is aluminum (Al), the dose is about 1 × 10 ¹¹ to 1 × 10 ¹³ cm ⁻² , and the peak concentration is about 1 × 10 ¹⁷ to 1 × 10 ^18. Desirably it is cm ⁻³ .

  As shown in FIG. 2, when observed from a direction (z direction) orthogonal to the upper surface 100a of the semiconductor substrate 100 (hereinafter referred to as “when viewed in plan”), the upper surface 100a of the semiconductor substrate 100 is The JFET portion 12A, the body region 13, the source region 14 and the body contact region 15 of the drift region 12 are arranged in a stripe pattern. In this example, the JFET portion 12A, the body region 13, the source region 14, and the body contact region 15 of the drift region 12 extend along the y-axis direction and are aligned along the x-axis direction. As a result, an NPN structure including the JFET portion 12A of the drift region 12, the body region 13, and the source region 14 is provided in the upper layer portion of the semiconductor substrate 100.

  As shown in FIG. 1, the planar gate 30 and the accumulation trench gate 40 are configured to have a T-shaped cross section. In this embodiment, in the structure having a T-shaped cross section, the portion disposed on the upper surface 100a of the semiconductor substrate 100 is the planar gate 30, and the portion disposed in the semiconductor substrate 100 is the accumulation trench gate 40. is there.

  The planar gate 30 is provided to face a part of the upper surface 100 a of the semiconductor substrate 100 and has a gate electrode 32 and a gate insulating film 34. The gate electrode 32 faces the upper surface 100a of the semiconductor substrate 100 with the gate insulating film 34 interposed therebetween, and is made of polysilicon containing a dopant. The gate insulating film 34 is silicon oxide. The planar gate 30 is disposed on the upper surface 100 a of the semiconductor substrate 100 so as to face the NPN structure constituted by the JFET portion 12 </ b> A, the body region 13, and the source region 14 of the drift region 12.

  Accumulation trench gate 40 is provided in trench TR formed in JFET portion 12 </ b> A of drift region 12, and extends from upper surface 100 a of semiconductor substrate 100 into semiconductor substrate 100. The accumulation trench gate 40 faces the body region 13 through the JFET portion 12A of the drift region 12. As shown in FIG. 2, the accumulation trench gate 40 is provided in the range of the JFET portion 12 </ b> A of the drift region 12 when the semiconductor substrate 100 is viewed in plan, and extends along the JFET portion 12 </ b> A of the drift region 12. Is growing. Of the side surfaces of the accumulation trench gate 40, the crystal surface of the side surface of the trench TR, which is in contact with the pair of side surfaces 40Sa facing the body region 13, is the {11-20} a-plane or the {1-100} m-plane. .

  As shown in FIG. 1, the accumulation trench gate 40 has a polysilicon portion 42 and an insulating coating portion 44. The polysilicon portion 42 is in contact with the gate electrode 32 of the planar gate 30, is covered with an insulating coating portion 44, and is polysilicon including a dopant. The insulation coating portion 44 is silicon oxide. The dopant concentration contained in the polysilicon portion 42 is configured to decrease as the depth increases along the thickness direction (z-axis direction) of the semiconductor substrate 100. For example, such a dopant distribution is realized by selectively introducing a dopant into the gate electrode 32 of the planar gate 30 and thermally diffusing the dopant into the polysilicon portion 42 of the accumulation trench gate 40.

  Next, the operation of silicon carbide semiconductor device 1 will be described with reference to FIG. When a positive voltage is applied to drain electrode 22, source electrode 24 is grounded, and gate electrode 32 of planar gate 30 is grounded, silicon carbide semiconductor device 1 is off.

  When a positive voltage is applied to drain electrode 22, source electrode 24 is grounded, and a voltage that is more positive than source electrode 24 is applied to gate electrode 32 of planar gate 30, silicon carbide semiconductor device 1 is on. . At this time, an inversion layer is formed in a portion of the body region 13 that separates the JFET portion 12A and the source region 14 of the drift region 12 from the planar gate 30. Electrons supplied from the source region 14 reach the JFET portion 12A of the drift region 12 via the inversion layer. The planar gate 30 and the accumulation trench gate 40 are integrally formed. Therefore, when a positive voltage is applied to the gate electrode 32 of the planar gate 30, a positive voltage is also applied to the polysilicon portion 42 of the accumulation trench gate 40. As a result, an accumulation layer is formed in the JFET portion 12A of the drift region 12 in contact with the accumulation trench gate 40. Electrons reaching the JFET portion 12 A of the drift region 12 flow in the thickness direction via the drift region 12 located below the accumulation layer and the body region 13, and then flow to the drain region 11.

  The JFET portion 12A of the drift region 12 is provided between the adjacent body regions 13. Therefore, when the accumulation trench gate 40 is not provided, the current path of the JFET portion 12A of the drift region 12 is narrowed by the depletion layer extending from the body region 13, and as a result, the resistance of this portion is increased. In silicon carbide semiconductor device 1, accumulation trench gate 40 is provided in JFET portion 12 </ b> A of drift region 12. An accumulation layer having a high electron density is formed on the side surface of the accumulation trench gate 40. For this reason, in silicon carbide semiconductor device 1, current can flow through the accumulation layer formed on the side surface of accumulation trench gate 40, so that the resistance of JFET portion 12 </ b> A in drift region 12 is lowered. As a result, silicon carbide semiconductor device 1 can have a low on-resistance characteristic.

  In silicon carbide semiconductor device 1, upper surface 100a of semiconductor substrate 100 is a Si surface. Therefore, the presence of carbon (C) can be reduced at the junction interface between the upper surface 100a of the semiconductor substrate 100 and the gate insulating film 34 of the planar gate 30. When the gate insulating film 34 is formed on the upper surface 100a of the semiconductor substrate 100 using a thermal oxidation technique, the presence of carbon (C) causes interface defects. In silicon carbide semiconductor device 1, since upper surface 100a of semiconductor substrate 100 is a Si surface, high-quality gate insulating film 34 in which the occurrence of interface defects is suppressed is formed. Therefore, silicon carbide semiconductor device 1 can have a low channel resistance characteristic.

In addition, the characteristics of the silicon carbide semiconductor device 1 are listed.
(1) In the silicon carbide semiconductor device 1, the crystal plane of the side surface of the trench TR where the pair of side surfaces 40Sa of the accumulation trench gate 40 contacts is the a-plane or the m-plane. According to this configuration, the carrier mobility of the accumulation layer formed on the pair of side surfaces 40Sa of the accumulation trench gate 40 is increased. Thus, in the silicon carbide semiconductor device 1, the Si surface is selected as the surface facing the planar gate 30, and the a surface or m surface is selected as the surface facing the accumulation trench gate 40. Is realized.
(2) In the silicon carbide semiconductor device 1, the planar gate 30 and the accumulation trench gate 40 are integrally formed. According to this configuration, the accumulation layer on the side surface of accumulation trench gate 40 is formed when silicon carbide semiconductor device 1 is on, and disappears when silicon carbide semiconductor device 1 is off. Thus, the timing for forming the accumulation layer on the side surface of the accumulation trench gate 40 can be synchronized with the switching operation of the silicon carbide semiconductor device 1. For example, if the accumulation layer is not formed when silicon carbide semiconductor device 1 is on, the on-resistance does not decrease. If the accumulation layer is formed while silicon carbide semiconductor device 1 is off, the depletion layer extending from the junction surface between drift region 12 and body region 13 becomes non-uniform in the plane of semiconductor substrate 100, and the breakdown voltage is reduced. . Since such a situation does not occur, silicon carbide semiconductor device 1 can have a low on-resistance and a high breakdown voltage characteristic.

  The silicon carbide semiconductor device 2 of the modification shown in FIG. 3 is characterized in that a plurality of accumulation trench gates 40 are arranged in a distributed manner. In particular, when the semiconductor substrate 100 is viewed in plan, since the accumulation trench gate 40 is formed in a rectangular shape, the pair of side surfaces 40Sa and the pair of side surfaces 40Sb are orthogonal to each other. In this example, the crystal plane on the side surface of the trench TR in contact with the pair of side surfaces 40Sa is the {11-20} a-plane, and the crystal surface on the side surface of the trench TR in contact with the pair of side surfaces 40Sb is {1-100} m. Surface. In silicon carbide semiconductor device 2 of this modified example, the density of the accumulation layer in JFET portion 12A in drift region 12 increases, so the resistance of JFET portion 12A in drift region 12 significantly decreases.

  The silicon carbide semiconductor device 3 of the modification shown in FIG. 4 is characterized in that the drift region 12 has a high concentration drift region 12 a that contacts the side surface of the accumulation trench gate 40. The dopant concentration in the high concentration drift region 12 a is higher than the dopant concentration in the portion of the drift region 12 existing below the body region 13. In the silicon carbide semiconductor device 3 of this modification, since the electron density of the accumulation layer formed on the side surface of the accumulation trench gate 40 is increased, the resistance of the JFET portion 12A in the drift region 12 is decreased.

  The silicon carbide semiconductor device 4 of the modification shown in FIG. 5 is characterized in that the planar gate 30 and the accumulation trench gate 40 are insulated and separated. A pad electrically connected to the gate electrode 32 of the planar gate 30 and a pad electrically connected to the polysilicon portion 42 of the accumulation trench gate 40 are provided separately, and the gate electrode 32 of the planar gate 30 and the accumulation electrode are provided. The polysilicon part 42 of the trench gate 40 is configured to be able to apply different voltages. For example, in the ON state, the voltage applied to the polysilicon portion 42 of the accumulation trench gate 40 is adjusted to be lower than the voltage applied to the gate electrode 32 of the planar gate 30. In the silicon carbide semiconductor device 4 of this modification, the voltage applied to the polysilicon portion 42 of the accumulation trench gate 40 is kept low in the on state, so that the electric field in the insulating coating portion 44 on the bottom surface of the accumulation trench gate 40 is reduced. Concentration is eased.

  The silicon carbide semiconductor device 5 of the modification shown in FIG. 6 is characterized in that a p-type electric field relaxation region 16 in contact with the bottom surface of the accumulation trench gate 40 is provided. The electric field relaxation region 16 may have a floating potential or may be electrically connected to the source electrode 24. In addition, the silicon carbide semiconductor device 6 of the modification shown in FIG. 7 is characterized in that the insulating coating portion 44 on the bottom surface of the accumulation trench gate 40 is configured to be thicker than the insulating coating portion 44 on the side surface. In silicon carbide semiconductor devices 5 and 6 of these modified examples, electric field concentration in insulation coating portion 44 on the bottom surface of accumulation trench gate 40 is alleviated.

  The silicon carbide semiconductor device 7 of the modification shown in FIG. 8 is characterized in that the accumulation trench gate 40 is provided shallower than the body region 13. In the silicon carbide semiconductor device 7 of this modified example, the bottom surface of the accumulation trench gate 40 is satisfactorily covered with the depletion layer extending from the body region 13 in the off state, so that the insulation coating portion 44 on the bottom surface of the accumulation trench gate 40 Electric field concentration is reduced. Further, even in the example of such a shallow accumulation trench gate 40, a p-type electric field relaxation region 16 in contact with the bottom surface of the accumulation trench gate 40 is provided as in the silicon carbide semiconductor device 8 of the modification shown in FIG. The insulating coating 44 on the bottom surface of the accumulation trench gate 40 may be thicker than the side insulating coating 44 as in the silicon carbide semiconductor device 9 of the modification shown in FIG. Good. In silicon carbide semiconductor devices 8 and 9 of these modified examples, the electric field concentration in insulation coating portion 44 on the bottom surface of accumulation trench gate 40 is further alleviated.

  In the silicon carbide semiconductor device 10 of the modification shown in FIG. 11, when the semiconductor substrate 100 is viewed in plan, the source region 14 has a comb-like layout, and the accumulation trench gate 40 also has a comb-teeth shape. It has a layout. The source region 14 has a contact source part 14a and a plurality of protruding source parts 14b. The contact source portion 14a includes a contact surface that is exposed to the upper surface 100a of the semiconductor substrate 100 and that is in ohmic contact with the source electrode 24 (see FIG. 1). The contact source portion 14a extends along the y direction when the semiconductor substrate 100 is viewed in plan. Each of the plurality of protruding source parts 14b has a rectangular common shape when viewed in plan, and protrudes from the contact source part 14a along the x direction orthogonal to the y direction in which the contact source part 14a extends. The plurality of protruding source parts 14b are arranged at equal intervals along the y direction. Thus, the source region 14 has a comb-like shape when viewed in plan.

  As shown in FIG. 11, the accumulation trench gate 40 has a comb-like shape having a plurality of protrusions 40 a that protrude in opposite directions along the X direction when the semiconductor substrate 100 is viewed in plan. Each of the plurality of protruding portions 40a of the accumulation trench gate 40 is configured to enter between the protruding source portions 14b adjacent to each other in the Y direction when seen in a plan view. In other words, the comb teeth including the plurality of protruding portions 40 a of the accumulation trench gate 40 and the comb teeth including the plurality of protruding source portions 14 b of the source region 14 are alternately arranged. In the y-axis direction, the body region 13 and the JFET portion 12 </ b> A of the drift region 12 are disposed between the protruding portion 40 a of the accumulation trench gate 40 and the protruding source portion 14 b of the source region 14. Thus, in the silicon carbide semiconductor device 1 of the modified example, the NPN structure composed of the JFET portion 12A, the body region 13 and the source region 14 of the drift region 12 is also configured in the y-axis direction. The planar gate 30 (see FIG. 1) is also opposed.

  In the silicon carbide semiconductor device 10 of the modification shown in FIG. 11, the NPN structure is configured to meander when the semiconductor substrate 100 is viewed in plan by providing the comb-like source region 14. Yes. For this reason, the NPN structure has a short channel length and a long channel width. As a result, in the silicon carbide semiconductor device 10 of the modified example, the channel resistance is extremely low. In addition, the dopant aluminum (Al) contained in the body region 13 and the dopant nitrogen (N) contained in the drift region 12 and the source region 14 have low thermal diffusibility in the semiconductor substrate 100 of silicon carbide. Almost no heat diffusion. Such low thermal diffusivity is a characteristic characteristic of a silicon carbide substrate. In the silicon carbide semiconductor device 10 of the modified example, a fine NPN structure with a short channel length and a long channel width is realized by utilizing such a low thermal diffusibility feature.

  Furthermore, the silicon carbide semiconductor device 10 of the modified example has a layout in which the comb-shaped source region 14 and the comb-shaped accumulation trench gate 40 are engaged with each other. For this reason, the electrons that have reached the JFET portion 12A of the drift region 12 via the inversion layer having the NPN structure efficiently flow to the accumulation layer formed on the side surface of the accumulation trench gate 40. For this reason, the silicon carbide semiconductor device 10 of a modification can have an extremely low on-resistance characteristic.

  Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings can achieve a plurality of objects at the same time, and has technical usefulness by achieving one of the objects.

11: drain region 12: drift region 13: body region 14: source region 15: body contact region 22: drain electrode 24: source electrode 30: planar gate 32: gate electrode 34: gate insulating film 40: trench gate 42 for accumulation: Polysilicon part 44: insulation coating part 100: semiconductor substrate TR: trench

Claims (9)

A silicon carbide semiconductor substrate;
A planar gate facing a portion of the upper surface of the semiconductor substrate;
An accumulation trench gate provided in a trench extending from a part of the upper surface of the semiconductor substrate into the semiconductor substrate,
The semiconductor substrate is
A source region of a first conductivity type exposed on the upper surface;
A body region of a second conductivity type covering the source region and exposed on the upper surface;
A drift region of a first conductivity type that covers the body region and is exposed on the upper surface,
The planar gate is disposed on the upper surface of the semiconductor substrate so as to face the body region that separates the source region and the drift region,
The accumulation trench gate is a silicon carbide semiconductor device arranged in the semiconductor substrate so as to face the body region via the drift region.   The silicon carbide semiconductor device according to claim 1, wherein a crystal plane of the upper surface of the semiconductor substrate is a Si plane.   3. The silicon carbide semiconductor device according to claim 2, wherein a crystal plane of a side surface of the trench, which is in contact with a side surface facing the body region, of the side surfaces of the accumulation trench gate is an a plane or an m plane. The drift region has a high concentration drift region in contact with a side surface of the accumulation trench gate,
The dopant concentration in the high-concentration drift region is configured to be higher than the dopant concentration in the portion of the drift region existing below the body region. Silicon carbide semiconductor device.   The silicon carbide semiconductor device according to claim 1, wherein the planar gate and the accumulation trench gate are integrally formed. The planar gate and the accumulation trench gate are insulated and separated,
The silicon carbide semiconductor device according to claim 1, wherein the planar gate and the accumulation trench gate are configured to be able to apply different voltages. The accumulation trench gate has a semiconductor part into which a dopant is introduced and an insulating coating part that covers the semiconductor part,
The silicon carbide semiconductor device as described in any one of Claims 1-6 comprised so that the dopant concentration of the said semiconductor part may fall, so that it may become deep along the thickness direction of the said semiconductor substrate. A top electrode in contact with the top surface of the semiconductor substrate;
The source region is
A contact source portion exposed on the upper surface of the semiconductor substrate and including a contact surface in contact with the upper surface electrode;
A plurality of projecting source portions that are exposed on the upper surface of the semiconductor substrate and project from the contact source portion when observed from a direction orthogonal to the upper surface of the semiconductor substrate;
8. The accumulation gate according to claim 1, wherein the accumulation trench gate is disposed so as to penetrate between adjacent protruding source portions when observed from a direction orthogonal to the upper surface of the semiconductor substrate. A silicon carbide semiconductor device according to claim 1. The dopant contained in the source region and the drift region is nitrogen or phosphorus,
The silicon carbide semiconductor device according to claim 8, wherein the type of dopant contained in the body region is aluminum.

Images