JPH08102538A - Field effect type semiconductor device - Google Patents

Abstract

PURPOSE: To reduce ON-resistance of a field effect type semiconductor device. CONSTITUTION: A field effect type semiconductor device has semiconductor regions 11, 12 of one conductivity type to become a drain wherein a recessed part 12a is formed in a surface, a semiconductor region 13 of the other conductivity type which is formed in a region at a specified distance from the recessed part 12a in a surface of the semiconductor regions 11, 12, a semiconductor region 14 of one conductivity type which is formed inside the semiconductor region 13 of the other conductivity type and becomes a source and a gate electrode 16 which is applied to a surface of the semiconductor region 13 of the other conductivity type interleaving an insulation layer 15 and attains the recessed part 12a.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect semiconductor device, and more particularly to a field effect semiconductor device capable of reducing on-resistance.

[0002]

2. Description of the Related Art FIG. 12 shows a sectional structure of a conventional planar type field effect semiconductor device. This is shown as the prior art in Japanese Utility Model Laid-Open No. 63-124762. In FIG. 12, an n ⁻ type layer 112 is laminated on the n ⁺ type semiconductor substrate 111 by an epitaxial method. The n ⁺ type semiconductor substrate 111 and the n ⁻ type layer 112 serve as drains. Circular p-type layer 11
3 is diffused and formed on the surface side of the n ⁻ type layer 112, and a ring-shaped n ⁺ type layer 114 serving as a source is further diffused and formed on the surface side of the p type layer 113. The gate electrode 116 is the insulating layer 1
It is formed so as to cover the front surface side of the p-type layer 113 located between the n ⁻ -type layer 112 and the n ⁺ -type layer 114 via 15. Note that L _G is the gate length. The source electrode 117 is ohmic-connected to the n ⁺ type layer 114 and the p type layer 113 located outside the n ⁺ type layer 114.

In this case, when a positive voltage is applied to the gate electrode 116, an inversion layer serving as a channel is formed on the gate electrode 116 side (front surface side) of the p-type layer 113, and the source region 1 is formed.
14 and the drain region 112 are turned on. The resistance between the source and the drain at the time of this ON is the resistance R _{ch1 of} this channel, and the resistance R of the n ⁻ type layer 112 on the side of the gate electrode 116.
_acc1 , channel resistance R of parasitic vertical field effect transistor
The resistance R of the n ⁻ -type layer 112 other than the _{JFET 1} and each of the above resistances
_{It is} the sum of _drift1 . Here, the resistance R _acc1 is the resistance of the charge storage layer on the surface of the n ⁻ type layer 112. Gate electrode 1
When a positive voltage is applied to 16, electrons are accumulated in the surface side region of the n ⁻ type layer 112 and the resistance becomes low. This region is called a charge storage layer. When a voltage is applied to the source electrode 117, a depletion layer spreads to the right from the p-type layer 113 on the left side in the figure, and a depletion layer spreads to the left from the p-type layer 113 on the right side in the figure. A channel of the parasitic junction transistor is formed between the layers. The resistance R _JFET1 is the resistance of the parasitic junction transistor thus formed. The integration of the parasitic junction transistor resistance is improved, and the gate length L _G
It becomes higher as the (channel width X) becomes smaller.

FIG. 13 shows a conventional trench type electric field effect.
The fruit type semiconductor device is shown. This is the actual exploitation 63-12
It is disclosed in Japanese Patent No. 4762. In FIG.
By the way, n⁺Drain on the semiconductor substrate 121
n^-The mold layer 122 is formed by an epitaxial method
You. Further, the p-type layer 123 is n^-Formed on the mold layer 122
N as a source⁺The mold layer 124 is the surface of the p-type layer 123
Diffusion formed on the side. The source electrode 125 is n⁺Type
Ohmic-connected to the layer 124 and the p-type layer 123
You. The groove-shaped recess 127 is n⁺Mold layer 124, p-type layer 123
Through n^-Formed to reach the mold layer 122
You. The gate electrode 128 has the recess 1 through the insulating layer 129.
It is located within 27. A positive voltage is applied to the gate electrode 128
A region in contact with the recess 127 of the p-type layer 123 when applied
A channel is formed in the source 124 and the drain 122.
There is continuity between the two. On-resistance of this field effect semiconductor device
Is the resistance R_ch2, Resistance R_acc2And resistance R _drift2The sum of
You. The resistance R_ch2Is resistance R_ch1Is similar to
Resistance R _acc2Is resistance R_acc1Is similar to the resistance
R_drift2Is resistance R_drift1Is similar to. in this case
Is the resistance R_JFET1There is no resistance equivalent to.

[0005]

The problem shown in FIG.
Then, the on-resistance is the resistance R_ch1, Resistance R_acc1, Resistance R
_JFET1And resistance R_drift1Is the sum of In particular, the resistance R
_JFET1Because of this, the on-resistance becomes relatively high
There were drawbacks. Therefore, in order to reduce the ON resistance,
Increase the cell density per unit area, that is, the gate length
L_GAnd shorten the resistance R_ch1Try to reduce the reverse
Since the gate width X becomes smaller, the resistance R_JFET1Is large
ON resistance can be kept below a certain level
There wasn't. Further, in the above-mentioned one shown in FIG.
To form the p-type layer 123 and n^-Pair of layers 122
And etching such as RIE (Reactive Ion Etching)
If this is done, the sidewalls of the recess 127 will not be etched.
In the channel because the image is not completely removed
Carrier mobility decreases. Therefore, the resistance Rch₂Is high
And the on-resistance does not decrease as expected.
There was a point. Therefore, one problem of the present invention is
The on-resistance is sufficiently reduced by eliminating the drawbacks of the conventional example described above.
Another object of the present invention is to provide a field effect semiconductor device. Furthermore,
Another object of the present invention is to reduce the on-resistance while
It is also intended to improve the gate / drain breakdown voltage.

[0006]

In order to solve the above-mentioned problems, a structure of a first invention of the present application is to provide a one-conductivity-type semiconductor source region, a one-conductivity-type semiconductor drain region, and a space between the source region and the drain region. In the field-effect-type semiconductor device, comprising: the other-conductivity-type semiconductor region provided on the gate electrode and the other-conductivity-type semiconductor region adjacent to the other-conductivity-type semiconductor region via an insulating layer. The side portion has lower conductivity than the portion of the gate electrode other than the drain region side portion. According to the configuration of the first invention, the drain region side portion of the gate electrode has a lower conductivity than the other portions of the gate electrode.
The electric field concentration in the drain side portion of the gate electrode can be relaxed. Therefore, the breakdown voltage of the gate / drain can be improved and the thickness of the insulating film of the gate can be reduced, so that the on-resistance can be reduced.

Further, in the structure of the second invention, one conductivity type semiconductor source region, one conductivity type semiconductor drain region, another conductivity type semiconductor region provided between the source region and the drain region, A gate electrode provided to be adjacent to the semiconductor region of another conductivity type and the drain region with an insulating layer interposed therebetween, the gate electrode being formed of a semiconductor of one conductivity type, and the drain region and another conductivity type of the other. The field effect semiconductor device is characterized in that it is connected through a semiconductor region. According to the configuration of the second aspect of the invention, when the diode structure is formed between the gate and the drain and a voltage higher than the punch through voltage is applied between the gate and the drain, the diode punches through to increase the gate potential. Since the field effect semiconductor device is turned on, it is possible to prevent the field effect semiconductor device from being destroyed.

Further, in the structure of the third invention, a one-conductivity-type semiconductor region serving as a drain in which a recess is formed on the surface and a region of the surface of the one-conductivity-type semiconductor region separated from the recess by a predetermined distance. Another conductivity type semiconductor region formed,
A one-conductivity-type semiconductor region serving as a source, which is formed in the other-conductivity-type semiconductor region, and a gate electrode which coats the surface of the other-conductivity-type semiconductor region with an insulating layer interposed therebetween and reaches the recess. It is a field effect semiconductor device having. According to the configuration of the third invention, basically, a planar type field effect semiconductor device similar to that of FIG. 12 is formed. However, in this case, since the gate electrode extends through the insulating layer in the concave portion, a low resistance portion in which electric charges are concentrated is formed in a portion near the concave portion of the one-conductivity-type semiconductor region serving as the drain, which is a conventional planar type. It is possible to eliminate the resistance R _JFET which cannot be avoided in the field effect semiconductor device. Note that unlike a trench-type field effect semiconductor device, a channel is not formed on the sidewall of the recess, so even if the sidewall of the recess is damaged by etching for forming the recess, the Is never high.

Further, in the structure of the fourth invention, in the structure of the third invention, the conductivity of the gate electrode is lower at the bottom of the recess than at other parts. Fourth above
According to the structure of the invention of claim 3, in addition to the function of the structure of the third invention, the portion of the gate electrode at the bottom of the recess has a high resistance, and the electric field concentration at the edge of the bottom of the recess can be alleviated. -The drain breakdown voltage can be improved.

Further, in the structure of the fifth invention, in the structure of the third invention, the gate electrode is formed of a semiconductor of one conductivity type in at least a lower portion of the recess, and the gate electrode of one conductivity type is formed. That is, the drain region of one conductivity type is connected via a semiconductor region of another conductivity type. According to the structure of the fifth invention, in addition to the function of the structure of the third invention, when a diode structure is formed between the gate and the drain and a voltage higher than the punch-through voltage is applied between the gate and the drain, Since the diode punches through to increase the gate potential and turn on the field effect semiconductor device, it is possible to prevent the field effect semiconductor device from being destroyed.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a sectional structure of a first embodiment of the present invention. The first embodiment is claim 3.
It corresponds to. In FIG. 1, as one conductivity type semiconductor region to be a drain, n ⁻ on the n ⁺ type semiconductor substrate 11 is formed.
The mold layer 12 is formed by an epitaxial method. The trench structure recess 12 a is formed on the surface side of the n ⁻ type layer 12. P-type layer 13 as another conductivity type semiconductor region
Are diffused and formed on the surface side of the n ⁻ type layer 12. Further, the n ⁺ layer 14 is formed as one conductive type semiconductor region serving as a source.
Are diffused and formed on the surface side of the p-type layer 13. The p-type layer 13 and the n ⁺ layer 14 are formed in the recess 12
It is formed in a ring shape so as to surround the recess 12a at a predetermined distance from a. The T-shaped cross-section gate electrode 16 covers the surface of the p-type layer 13 inside the n ⁺ -type layer 14 with the insulating layer 15 in between, and further extends into the recess 12 a. The source electrode 17 is in ohmic contact with the n ⁺ -type layer 14 and the p-type layer 13 outside thereof. In addition,
The material of each electrode 16, 17 is a metal such as aluminum, M
It is a silicide such as oSi ₂ or a semiconductor such as polycrystalline silicon.

With the above structure, the T-shaped gate electrode 16 is arranged in the recess 12a with the insulating layer 15 interposed therebetween. Therefore, the parasitic vertical MOS transistor unlike the conventional example is not formed. As a result, when a voltage is applied to the gate electrode 16, the electric charges are concentrated on the portion of the n ⁻ type layer 12 in the vicinity of the recess 12a, and the resistance of this portion is reduced. For this reason,
The R _JFET, which has occurred in the structure of FIG. 12 described above, does not occur.
Therefore, the ON resistance can be made smaller than that shown in FIG. In addition, the channel is p
Reactive ion etching (RI) for forming the recess 12a is formed in the portion by lateral diffusion of the type impurities.
Since the channel is not damaged by E), the channel resistance is small. Therefore, the on-resistance becomes smaller than that shown in FIG. As a result, the on-resistance becomes smaller than that of the above-mentioned conventional example.

FIG. 2 shows a sectional structure of the second embodiment. The second embodiment corresponds to claims 1, 3, and 4,
This is an improvement of the first embodiment described above. In FIG. 2, the T-shaped gate electrode 26 as a conductive member includes a low resistance gate electrode 26a and a high resistance gate electrode 26b as a bottom side portion of the recess 22a. Low resistance gate electrode 26
a is T-shaped, and the high resistance gate electrode 26b is connected to the lower end of the low resistance gate electrode 26a. The T-shaped gate electrode 26 is arranged in the recess 22a from the surface side of the p-type layer 23 with the insulating layer 25 interposed therebetween. It should be noted that the same members as those shown in FIG. 1 are designated by the reference numerals corresponding to those in FIG. 1 (for example, “21” in FIG. 2 corresponds to “11” in FIG. 1), and the description thereof is omitted. .

With the above structure, the operation of the first embodiment of the first invention described above is achieved, and the bottom side portion (high resistance gate electrode 26b) of the recess 22a of the T-type gate electrode 26 has a high resistance. Therefore, the electric field concentration at the edge of the bottom of the recess 22a can be relaxed, and the gate / drain breakdown voltage can be improved. The resistance change between the low resistance gate electrode 26a and the high resistance gate electrode 26b may be graded. In this way, the low resistance gate electrode 26a
Since the electric field concentration at the boundary between the high resistance gate electrode 26b and the high resistance gate electrode 26b can be relaxed, the breakdown voltage between the gate and the drain is further improved.
As the breakdown voltage increases, the thickness of the gate insulating film can be reduced. Since the on-resistance depends on the thickness of the gate insulating film, thinning the insulating film can reduce the on-resistance.

FIG. 3 shows a sectional structure of the third embodiment. The third embodiment corresponds to claims 1, 3, and 4,
It is a modification of the said 2nd Embodiment. In FIG.
The parts other than the gate electrode 28 are the same as those shown in FIG. The gate electrode 28 includes a T-type p ⁺ -type semiconductor region 28a and a p ⁻ -type semiconductor region 28b in contact with the bottom of the T-type p ⁺ -type semiconductor region 28a. T-type p ⁺ -type semiconductor region 28a
Corresponds to the low resistance gate electrode 26a in FIG.
^{The −} type semiconductor region 28b corresponds to the high resistance gate electrode 26b in FIG. Therefore, the one shown in FIG. 3 operates in the same manner as the one shown in FIG. 2 described above in accordance with the first embodiment of the first invention described above, and the portion of the gate electrode 28 on the bottom side of the recess 22 a is located. (P ⁻ type semiconductor region 28b)
Has a high resistance, the electric field concentration at the edge of the bottom of the recess 22a can be relaxed, and the gate / drain breakdown voltage can be improved.

FIG. 4 shows a sectional structure of the fourth embodiment. The fourth embodiment corresponds to claims 2, 3, and 5,
It is an improvement of the first embodiment. In FIG. 4, at least the bottom portion of the T-shaped gate electrode 36a located in the recess 32a is made of an n ⁺ type semiconductor. A p-type semiconductor region 36b is interposed between the n ⁺ -type semiconductor substrate 31 and a portion of the gate electrode 36a which is made of an n ⁺ -type semiconductor. Therefore, a diode structure is formed between the gate electrode 36a and the n ⁺ type semiconductor substrate 31. The same members as those shown in FIG. 1 have the same reference numerals as those in FIG. 1 (for example, “31” in FIG. 4 is “11” in FIG. 1).
(Corresponding to) and the description thereof is omitted.

With the above structure, when a voltage higher than the voltage at which the p-type semiconductor region 36b punches through is applied between the gate and the drain, the n ⁺ -type gate electrodes 36a and n are formed.
Punch-through is performed between the ⁺ type drain region 31 and the ⁺ type drain region 31. n ⁺
If the potential of the mold drain electrode 31 rises abnormally, DM
It is possible to prevent the DMOS from being destroyed by turning on the OS. Furthermore, the chip area does not increase even if the P-type region 36b is added. In this structure, the punch-through voltage can be adjusted by adjusting the thickness of the p-type semiconductor region 36b. Further, a plurality of diodes connected in series may be formed between the gate electrode 36a and the drain 31.

FIG. 5 shows a sectional structure of the fifth embodiment. The fifth embodiment corresponds to claim 3, and a semiconductor layer is added to the first embodiment to add an IGBT (Insula).
tedGate Bipola Transistor). Figure 5
In the above, the n-type layer 4 serving as the drain is formed on the p ⁺ -type layer 48.
1 is formed by an epitaxial method, and an n-type layer 41
An n ⁻ -type layer 42 serving as a drain is formed on the above by an epitaxial method. It should be noted that the same members as those shown in FIG. 1 are designated by the reference numerals corresponding to those in FIG. 1 (for example, “43” in FIG. 5 corresponds to “13” in FIG. 1), and the description thereof is omitted. . With the above configuration, the resistance R _drift can be reduced by injecting minority carriers from the p ⁺ -type layer 48 into the n-type layer 41 and the n ⁻ -type layer 42. Therefore, even if the n ⁻ -type layer 42 is thickened to increase the breakdown voltage, a low on-resistance can be realized. The n-type layer 41 is a p-type layer 43 when a voltage is applied to the drain.
And p ⁺ type layer 48 is prevented from punching through.

FIG. 6 is a first plan view of each of the above embodiments.
The outline of the example of is shown. In FIG. 6, the mesh-shaped gate 5
The n ⁺ type layer 52a and the p type layer 53a are exposed in the first opening 51a. Similarly, the n ⁺ -type layer 52b and the p-type layer 53b are exposed in the opening 51b, and the n ⁺ -type layer 52 is exposed in the opening 51c.
The c and p-type layers 53c are exposed, and the n ⁺ -type layer 52d and the p-type layer 53d are exposed in the opening 51d. FIG. 7 shows an outline of a second example of the plane of each of the above-described embodiments. In FIG. 7, the n ⁺ type layer 62a is exposed around the island-shaped gate electrode 61a. Similarly, the n ⁺ -type layer 62b is exposed around the island-shaped gate electrode 61b, the n ⁺ -type layer 62c is exposed around the island-shaped gate electrode 61c, and the n ⁺ -type layer 62d is exposed around the island-shaped gate electrode 61d. Exposed. In addition, 63 is a p-type layer.

FIG. 8 is a third plan view of each of the above embodiments.
The outline of the example of is shown. In FIG. 8, similarly to the first example, the n ⁺ type layers 72a to 72g and the p type layers 73a to 73g are exposed in the openings 71a to 71g of the mesh gate 71, respectively. However, the arrangement of the openings 71a to 71g is different from that of the first example. In each of the above-described embodiments, the p-type layers 13, 23, 33, 43 and the n ⁺ -type layer 1 are provided.
The numbers 4, 24, 34, 44 are not limited to ring shapes, and may be formed separately on both sides of the recesses 12a, 22a, 32a, 42a. Further, the n-type semiconductor region (or layer) may be a p-type semiconductor region (or layer), and the p-type semiconductor region (or layer) may be an n-type semiconductor region (or layer).

FIG. 9 shows a sectional structure of the sixth embodiment. The sixth embodiment corresponds to claim 1 and shows a lateral double-diffused MOS transistor. In FIG. 9, a p-type semiconductor region 82 is diffused from the surface of the n-type semiconductor layer 81, and an n ⁺ type semiconductor region 83 is further formed.
Of the n ⁺ type semiconductor region 84 is simultaneously diffused from the surface of the n type semiconductor layer 81. To be shown leftmost thin gate shown right end of the through oxide film 85a n ⁺ -type semiconductor layer 83 surface, the surface of the n-type semiconductor layer 81 and n ⁺ -type semiconductor layer 84 surface of the gate electrode 86 is oxidized film 85 It is formed like. In the gate electrode 86, the drain side portion is the p ⁻ type semiconductor layer 86b, and the other portion is the p ⁺ type semiconductor layer 86a. The surface of the p-type semiconductor layer 82 serves as a channel. The source electrode 87 is connected to the n ⁺ type semiconductor layer 83, and the drain electrode 88 is connected to the n ⁺ type semiconductor layer 84. With the above configuration, the drain side portion 86 of the gate electrode 86
Since the conductivity of b is lower than that of the other portion 86a of the gate electrode 86, the electric field concentration on the drain side portion 86b of the gate electrode 86 can be relaxed. Therefore, even with the thin gate oxide film 85a, the breakdown voltage between the gate 86 and the drains 81 and 84 can be improved. Further, the gate oxide film 85a
By reducing the thickness, ON resistance can be reduced. Therefore, it is possible to achieve both low on-resistance and high breakdown voltage.

FIG. 10 shows a sectional structure of the seventh embodiment. The seventh embodiment corresponds to claims 1, 3 and 4, and shows a 2-gate type. In FIG. 10, n
^An n-type drift layer 92 is formed on the ⁺ type drain layer 91 by an epitaxial method. Further, the p-type body layer 9
3 is diffused and formed on the surface side of the n-type drift layer 92, and n ⁺
The type source regions 94a and 94b are diffused from the surface of the p-type body layer 93. Recesses (trench) 92a, 9
2b is formed so as to penetrate the n ⁺ type source regions 94a and 94b and the p type body layer 93 and reach the inside of the n type drift layer 92. The gate electrode 96 is the insulating layer 95a
It is formed so as to fill the concave portion 92a via the.
The insulating layer 95a also covers the upper end of the gate electrode 96 in the figure. On the other hand, the gate electrode 97 is formed so as to fill the recess 92a via the insulating layer 95b. The insulating layer 95b also covers the upper end of the gate electrode 97 in the figure.
The gate electrode 96 has the p ⁺ -type semiconductor region 9 on the upper side thereof.
6a and the p ⁻ type semiconductor region 96b at its lower end portion, and the gate electrode 97 is made up of the p ⁺ type semiconductor region 97a at its upper portion and the p ⁻ type semiconductor region 97b at its lower end portion. The drain electrode 98 is connected to the n ⁺ -type drain layer, and the source electrode 99 is the n ⁺ -type source regions 94a and 94b.
And the p-type body layer 93.

With the above structure, the n ⁺ type source region 94 is formed.
When a voltage is applied to the a and 94b and the gate electrodes 96 and 97 so that the drain electrode 98 is on the positive side, the depletion layer 92c spreads in the n-type drift layer 92, and the depletion layer 9
3a spreads in the p-type body 93, and the depletion layer 96c becomes p ^−.
In the p ^- type semiconductor region 97b, the depletion layer 97c extends in the p ^- type semiconductor region 97b. Therefore, the gate electrode 9
Since the electric field is not concentrated at the lower ends of 6, 97, the thin insulating layer 9
High breakdown voltage can be realized with 5a and 95b. Therefore, the insulating layers 95a and 95b which will be the gate oxide film can be thinned, and the on-resistance can be lowered. As a result, low on-resistance and high breakdown voltage can both be achieved.

FIG. 11 shows a sectional structure of the eighth embodiment. The eighth embodiment corresponds to claims 2, 3 and 5, and shows a case where a diode structure is added to the gate electrode. In FIG. 11, an n-type drift layer 102 is formed on the n ⁺ -type drain layer 101 by an epitaxial method. Further, the p-type body layer 103 is diffused and formed on the surface side of the n-type drift layer 92, and the n ⁺ -type source region 10 is formed.
4a and 104b are diffused from the surface of the p-type body layer 103. Recesses (trench) 102a and 102b are n ⁺ type source regions 104a and 104b, and p type body layer 9
It is formed so as to penetrate the 3 and n-type drift layers 92 and reach the n ⁺ -type drift layer 101. Insulating layer 10
5a is a side wall of the recess 102a and a gate electrode 10 described later.
6, the insulating layer 105b is formed so as to cover the upper end of the gate electrode 107 and the side wall of the recess 102b. The gate electrode 106 is the recess 1
02a and the gate electrode 107 is filled in the recess 102b. The gate electrode 106 is composed of the upper n ⁺ type semiconductor region 106a and the lower p type semiconductor region 106b, and the gate electrode 107 is the upper n ⁺ type semiconductor region 107a.
And the lower p-type semiconductor region 107b. The drain electrode 108 is connected to the n ⁺ type drain layer 101, and the source electrode 109 is connected to the n ⁺ type source regions 104 a and 104 b and the p type body layer 103.

With the above structure, the gate electrode 106 and n
^A first diode between the ⁺ type drain layer 101 (depending on the p type semiconductor region 106b and the n ⁺ type drain layer 101)
Exists, and the gate electrode 107 and the n ⁺ -type drain layer 101
A second diode (p-type semiconductor region 107b and n
⁺ Type drain layer 101). Therefore, the gate electrodes 106 and 107 and the source electrode 104
When a voltage is applied so that the potential of the drain electrode 108 is on the plus side with respect to a and 104b, the first diode and the second diode punch through even if the drain voltage becomes abnormally high, so that the MOS transistor Can be prevented from being destroyed. Therefore, the gate / drain breakdown voltage can be improved. Further, since the insulating layers 105a and 105b which will be the gate oxide film can be thinned, the on-resistance can be reduced. Therefore, it is possible to achieve both low on-resistance and high breakdown voltage. In this case, since the first diode and the second diode are formed at the positions of the gate electrodes 106 and 107, the chip area does not increase because the first diode and the second diode are formed.

As described in detail above, according to the field effect semiconductor device of the first invention of the present application, the electric field concentration on the drain side portion of the gate electrode can be relaxed, so that the gate oxide film as the insulating layer is formed. Can be made thinner, and the on-resistance can be reduced and the gate-drain breakdown voltage can be improved. Further, according to the field effect semiconductor device of the second aspect of the present invention, it is possible to prevent the field effect semiconductor device from being destroyed by punching through the diode formed in the gate electrode. Therefore, the gate oxide film as the insulating layer can be thinned, and the on-resistance can be reduced and the gate / drain breakdown voltage can be improved. Further, according to the field effect semiconductor device of the third invention, the parasitic vertical junction transistor as in the conventional example is not formed, and the channel is not damaged by the etching for forming the recess for the trench structure. can do. Further, according to the field effect semiconductor device of the fourth invention, in addition to the effect of the third invention,
The gate / drain breakdown voltage can be improved. Furthermore, according to the field effect semiconductor device of the fifth aspect of the invention, in addition to the effect of the third aspect of the invention, it is possible to prevent the field effect semiconductor device from being destroyed due to an abnormal rise in the gate potential.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a second embodiment.

FIG. 3 is a cross-sectional view showing a third embodiment.

FIG. 4 is a sectional view showing a fourth embodiment.

FIG. 5 is a sectional view showing a fifth embodiment.

FIG. 6 is a diagram illustrating a first plan example of each of the embodiments.

FIG. 7 is a diagram illustrating a second planar example of each of the embodiments.

FIG. 8 is a diagram illustrating a third plan example of each of the embodiments.

FIG. 9 is a sectional view showing a sixth embodiment.

FIG. 10 is a sectional view showing a seventh embodiment.

FIG. 11 is a sectional view showing an eighth embodiment.

FIG. 12 is a sectional view showing a conventional example.

FIG. 13 is a cross-sectional view showing another conventional example.

[Explanation of symbols]

11, 21, 31, 41 n ⁺ type semiconductor substrate 12, 22, 32, 42 n ⁻ type layer 12a, 22a, 32a, 42a n ⁻ type recessed portion 13, 23, 33, 43 p type layer 14, 24, 34, 44 n ⁺ type layer 15, 25, 35, 45 insulating layer 16, 26, 28, 46 gate electrode 26a low resistance gate electrode 26b high resistance gate electrode 28a p ⁺ type semiconductor region 28b p ⁻ type semiconductor region 36a n ⁺ Type gate electrode 36b p type region 81 n type semiconductor layer 82 p type semiconductor region 83, 84 n ⁺ type semiconductor region 86 gate electrode 86a p ⁺ type semiconductor layer 86b p ⁻ type semiconductor layer 91 n ⁺ type drain layer 92 n type drift Layers 92a and 92b Recesses 93 P-type body layers 94a and 94b n ⁺ type source regions 95a and 95b Insulating layers 96 and 97 Gate electrodes 96a and 97a p ⁺ type semiconductor regions 96b, 97b p ⁻ type semiconductor region 101 n ⁺ type drain layer 102 n type drift layer 102a, 102b recess 103 p type body layer 104a, 104b n ⁺ type source region 105a, 105b insulating layer 106, 107 gate electrode 106a, 107an ⁺ Type semiconductor region 106b, 107b p type semiconductor region

Claims (5)

[Claims] 1. A one-conductivity-type semiconductor source region, a one-conductivity-type semiconductor drain region, another conductivity-type semiconductor region provided between the source region and the drain region, and an insulating layer on the other-conductivity-type semiconductor region. In a field effect semiconductor device including a gate electrode provided so as to be adjacent to each other, the drain region side portion of the gate electrode has a conductivity higher than that of the gate electrode other than the drain region side portion. A field effect semiconductor device characterized by being low. 2. One conductivity type semiconductor source region, one conductivity type semiconductor drain region, another conductivity type semiconductor region provided between the source region and the drain region, the other conductivity type semiconductor region and the drain. A gate electrode provided so as to be adjacent to the region via an insulating layer, the gate electrode being formed of one conductivity type semiconductor, and being connected to the drain region via another other conductivity type semiconductor region. A field-effect type semiconductor device characterized in that 3. A one-conductivity-type semiconductor region having a recess formed on the surface and serving as a drain, and another-conductivity-type semiconductor region formed in a region at a predetermined distance from the recess on the surface of the one-conductivity-type semiconductor region. And a gate electrode reaching the recess by coating the surface of the one-conductivity-type semiconductor region formed in the other-conductivity-type semiconductor region with the one-conductivity-type semiconductor region serving as a source and an insulating layer. A field effect semiconductor device having: 4. The conductivity of the gate electrode is lower at the bottom of the recess than at other portions.
The field effect semiconductor device described. 5. The gate electrode is formed of a semiconductor of one conductivity type in at least a lower portion of the recess, and the gate electrode of one conductivity type and the drain region of the one conductivity type are connected via a semiconductor region of another conductivity type. The field effect semiconductor device according to claim 3, wherein