WO2017159034A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
WO2017159034A1
WO2017159034A1 PCT/JP2017/001783 JP2017001783W WO2017159034A1 WO 2017159034 A1 WO2017159034 A1 WO 2017159034A1 JP 2017001783 W JP2017001783 W JP 2017001783W WO 2017159034 A1 WO2017159034 A1 WO 2017159034A1
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Prior art keywords
region
gate electrode
gate
electric field
insulating film
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PCT/JP2017/001783
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French (fr)
Japanese (ja)
Inventor
侑佑 山下
雅裕 杉本
康裕 海老原
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トヨタ自動車株式会社
株式会社デンソー
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Publication of WO2017159034A1 publication Critical patent/WO2017159034A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the technology disclosed in this specification relates to a semiconductor device.
  • Semiconductor devices often include a trench type or planar type insulating gate portion.
  • the electric field concentrates on the gate insulating film at the drain side end of the insulated gate.
  • Japanese Patent Laid-Open No. 10-98188 discloses a p-type so as to be in contact with the bottom of the trench-type insulated gate, that is, the gate insulating film at the drain side end of the insulated gate.
  • a technique for providing an electric field relaxation region is disclosed. The electric field relaxation region can relieve the electric field concentrated on the gate insulating film at the drain side end of the insulated gate portion.
  • One embodiment of a semiconductor device disclosed in this specification includes a semiconductor substrate and an insulated gate portion.
  • the semiconductor substrate has a first conductivity type drain region, a first conductivity type drift region, a second conductivity type body region, a first conductivity type source region, and a second conductivity type electric field relaxation region,
  • the drain region, the drift region, the body region, and the source region are arranged in this order.
  • the insulated gate portion has a gate insulating film and a first conductivity type gate electrode.
  • the gate insulating film is in contact with the drift region, the body region, and the source region.
  • the gate electrode opposes at least a body region located between the drift region and the source region via a gate insulating film.
  • the electric field relaxation region has a portion arranged on the drain region side of the gate insulating film, is in contact with the gate electrode and the drift region, and separates the gate electrode and the drift region.
  • the electric field relaxation region has a portion disposed on the drain region side of the gate insulating film and is in contact with the drift region and the gate electrode. .
  • the semiconductor device of the above embodiment is configured such that the gate insulating film existing at the drain side end of the conventional structure is replaced with the electric field relaxation region.
  • the gate electrode is of the first conductivity type.
  • a pair of diodes are formed in which the first conductivity type drift region, the second conductivity type electric field relaxation region, and the first conductivity type gate electrode are connected in opposite directions. For this reason, in the semiconductor device of the above-described embodiment, even when the gate insulating film is partially replaced with the electric field relaxation region, the leakage current is suppressed and stable on and off operations are performed. Can do.
  • FIG. 1 is a schematic cross-sectional view of a main part of a semiconductor device according to a first embodiment.
  • the principal part sectional drawing of the semiconductor device of the modification of 1st Embodiment is shown typically.
  • the principal part sectional drawing of the semiconductor device of the modification of 1st Embodiment is shown typically.
  • the principal part sectional view of the semiconductor device of a 2nd embodiment is typically shown.
  • the semiconductor device 1 of the first embodiment is a power semiconductor element called a MOSFET, and includes a semiconductor substrate 10, a drain electrode 22 covering the back surface of the semiconductor substrate 10, and the surface of the semiconductor substrate 10. And a trench-type insulated gate portion 30 provided in the surface layer portion of the semiconductor substrate 10.
  • the semiconductor substrate 10 is a substrate made of silicon carbide (SiC), and includes an n + type drain region 11, an n ⁇ type drift region 12, a p type body region 13, a p + type body contact region 14, It has an n + type source region 15 and a p + type electric field relaxation region 16.
  • the drain region 11, the drift region 12, the body region 13, and the source region 15 are arranged in this order along the thickness direction of the semiconductor substrate 10.
  • the drain region 11 is disposed in the back layer portion of the semiconductor substrate 10 and is exposed on the back surface of the semiconductor substrate 10.
  • the drain region 11 is also a base substrate for the drift region 12 to grow epitaxially.
  • the drain region 11 is in ohmic contact with the drain electrode 22 that coats the back surface of the semiconductor substrate 10.
  • the drain region 11 preferably has a thickness of about 1 to 300 ⁇ m and an impurity concentration of about 1 ⁇ 10 18 to 1 ⁇ 10 23 cm ⁇ 3 .
  • the drift region 12 is provided on the drain region 11.
  • the drift region 12 is in contact with the side surface of the insulated gate portion 30.
  • the drift region 12 is formed by crystal growth from the surface of the drain region 11 using an epitaxial growth technique.
  • the drift region 12 preferably has a thickness of about 5 to 200 ⁇ m and an impurity concentration of about 1 ⁇ 10 13 to 1 ⁇ 10 17 cm ⁇ 3 .
  • the body region 13 is provided on the drift region 12 and is disposed on the surface layer portion of the semiconductor substrate 10. Body region 13 is in contact with the side surface of insulated gate portion 30. Body region 13 is formed by crystal growth from the surface of drift region 12 using an epitaxial growth technique. In one example, the body region 13 preferably has a thickness of about 1 to 5 ⁇ m and an impurity concentration of about 1 ⁇ 10 16 to 1 ⁇ 10 18 cm ⁇ 3 .
  • the body contact region 14 is provided on the body region 13, is disposed on the surface layer portion of the semiconductor substrate 10, and is exposed on the surface of the semiconductor substrate 10.
  • the body contact region 14 is formed by introducing aluminum or boron into the surface layer portion of the semiconductor substrate 10 using an ion implantation technique.
  • the body contact region 14 is in ohmic contact with the source electrode 24 that coats the surface of the semiconductor substrate 10.
  • the body contact region 14 has a dose amount of about 1 ⁇ 10 14 to 1 ⁇ 10 15 cm ⁇ 2 and a peak concentration of about 1 ⁇ 10 19 to 2 ⁇ 10 20 cm ⁇ 3. desirable.
  • the source region 15 is provided on the body region 13, is disposed on the surface layer portion of the semiconductor substrate 10, and is exposed on the surface of the semiconductor substrate 10. Source region 15 is separated from drift region 12 by body region 13. The source region 15 is in contact with the side surface of the insulated gate portion 30. The source region 15 is formed by introducing nitrogen or phosphorus into the surface layer portion of the semiconductor substrate 10 using an ion implantation technique. The source region 15 is in ohmic contact with the source electrode 24 that coats the surface of the semiconductor substrate 10. In one example, the source region 15 preferably has a dose of about 1 ⁇ 10 14 to 5 ⁇ 10 15 cm ⁇ 2 and a peak concentration of about 1 ⁇ 10 19 to 5 ⁇ 10 20 cm ⁇ 3. .
  • the insulated gate portion 30 extends from the surface of the semiconductor substrate 10 toward the deep portion, and includes a gate insulating film 32 and a gate electrode 34.
  • the insulated gate portion 30 is provided in a trench 30T that penetrates the source region 15 and the body region 13 and enters a part of the drift region 12.
  • the gate insulating film 32 covers the side surface of the trench 30T and is made of silicon oxide.
  • the gate insulating film 32 is formed by forming a trench 30T in the surface layer portion of the semiconductor substrate 10 and then selectively depositing the trench 30T on a side surface of the trench 30T using a vapor deposition technique.
  • the gate electrode 34 is separated from the source region 15, the body region 13 and the drift region 12 by the gate insulating film 32, and is made of n ⁇ type polysilicon.
  • the gate electrode 34 is opposed to the body region 13 located between the drift region 12 and the source region 15, and is configured to form an inversion layer in this opposed portion.
  • the gate electrode 34 is exposed on the bottom surface of the trench 30 ⁇ / b> T and is in contact with the electric field relaxation region 16.
  • the gate electrode 34 preferably has an impurity concentration of about 1 ⁇ 10 13 to 1 ⁇ 10 17 cm ⁇ 3 .
  • the electric field relaxation region 16 is disposed corresponding to the bottom of the insulating gate portion 30, is disposed closer to the drain region 11 than the gate insulating film 32, and is separated from the drain region 11 and the body region 13 by the drift region 12. It has been.
  • the electric field relaxation region 16 is disposed between the drift region 12 and the gate electrode 34, is in contact with the drift region 12 and the gate electrode 34, and separates the drift region 12 and the gate electrode 34.
  • the n ⁇ type drift region 12, the p + type electric field relaxation region 16, and the n ⁇ type gate electrode 34 are continuously arranged.
  • the drift region 12 and the electric field relaxation region 16 constitute one diode
  • the electric field relaxation region 16 and the gate electrode 34 constitute one diode
  • these diodes are arranged in the opposite directions.
  • the electric field relaxation region 16 is formed by forming the trench 30T in the surface layer portion of the semiconductor substrate 10 and then selectively depositing it on the bottom surface of the trench 30T using an epi growth technique. In one example, it is desirable that the electric field relaxation region 16 has a thickness of about 0.1 to 2 ⁇ m and an impurity concentration of about 1 ⁇ 10 18 to 1 ⁇ 10 23 cm ⁇ 3 .
  • the semiconductor device 1 When a positive voltage is applied to the drain electrode 22, the source electrode 24 is grounded, and the gate electrode 34 of the insulated gate portion 30 is grounded, the semiconductor device 1 is off. At this time, in the semiconductor device 1, since a reverse bias is applied to the diode constituted by the drift region 12 and the electric field relaxation region 16, the depletion layer extends from the pn junction between the drift region 12 and the electric field relaxation region 16. For this reason, the drain electrode 22 and the gate electrode 34 are insulated from each other, and the leakage current between the drain electrode 22 and the gate electrode 34 is suppressed. Therefore, the semiconductor device 1 can perform a stable off operation.
  • the electric field at the bottom of the insulating gate portion 30 is relaxed by the depletion layer extending from the pn junction between the drift region 12 and the electric field relaxation region 16.
  • the gate insulating film 32 is not provided on the bottom of the insulating gate portion 30.
  • the bottom of the insulated gate 30, that is, the drain side end of the insulated gate 30 is a place where electric field concentration tends to occur.
  • the dielectric breakdown of the gate insulating film 32 is suppressed.
  • the semiconductor device 1 can have high reliability because the dielectric breakdown of the gate insulating film 32 of the insulating gate portion 30 is suppressed.
  • the semiconductor device 1 When a positive voltage is applied to the drain electrode 22, the source electrode 24 is grounded, and a voltage that is more positive than the source electrode 24 is applied to the gate electrode 34 of the insulated gate portion 30, the semiconductor device 1 is on. At this time, in the semiconductor device 1, since a reverse bias is applied to the diode composed of the electric field relaxation region 16 and the gate electrode 34, the depletion layer extends from the pn junction between the electric field relaxation region 16 and the gate electrode 34. For this reason, the drain electrode 22 and the gate electrode 34 are insulated from each other, and the leakage current between the drain electrode 22 and the gate electrode 34 is suppressed. Therefore, the semiconductor device 1 can perform a stable on operation.
  • the semiconductor device 1 can perform a stable on-operation and off-operation, and can suppress the dielectric breakdown of the gate insulating film 32 and have high reliability. Further, in the semiconductor device 1, since the gate insulating film 32 does not exist at the bottom of the insulating gate portion 30, the feedback capacitance is extremely small and the switching speed is improved.
  • FIG. 2 shows a semiconductor device 2 according to a modification of the first embodiment.
  • the gate electrode 34 of the semiconductor device 2 includes a high concentration gate electrode 34a having a relatively high impurity concentration and a low concentration gate electrode 34b having a relatively low impurity concentration.
  • the high concentration gate electrode 34a is disposed in the upper portion of the trench 30T, and the low concentration gate electrode 34b is disposed in the lower portion of the trench 30T.
  • the boundary between the high-concentration gate electrode 34a and the low-concentration gate electrode 34b is preferably at the same depth as the boundary depth between the drift region 12 and the body region 13 or at a position deeper than the boundary depth.
  • the high-concentration gate electrode 34a is opposed to the entire range of the body region 13 located between the drift region 12 and the source region 15 via the gate insulating film 32, and the low-concentration gate electrode 34b is opposed to the electric field relaxation region 16.
  • the high-concentration gate electrode 34a preferably has an impurity concentration of about 1 ⁇ 10 18 to 1 ⁇ 10 23 cm ⁇ 3
  • the low concentration gate electrode 34b has an impurity concentration of about 1 ⁇ 10 13 to 1 ⁇ 10 17. Desirably it is cm ⁇ 3 .
  • the depletion layer extending from the pn junction between the electric field relaxation region 16 and the low concentration gate electrode 34b is prevented from extending deeply into the high concentration gate electrode 34a.
  • a constant gate voltage is applied over the entire high concentration gate electrode 34 a, a sufficient electric field can be applied to the body region 13.
  • a high-density inversion layer is formed over the entire range of the body region 13 located between the drift region 12 and the source region 15, and a low channel resistance is realized.
  • a low-resistance conductor may be provided on the upper portion in the trench 30T.
  • a metal may be used instead of the high-concentration gate electrode 34a.
  • FIG. 3 shows a semiconductor device 3 according to a modification of the first embodiment.
  • the electric field relaxation region 16 of the semiconductor device 3 is configured as a diffusion region.
  • the electric field relaxation region 16 is formed by forming the trench 30T in the surface layer portion of the semiconductor substrate 10 and then introducing aluminum or boron into the bottom surface of the trench 30T using an ion implantation technique.
  • the electric field relaxation region 16 configured as a diffusion region covers the drain side end portion of the gate insulating film 32 covering the side surface of the trench 30T. For this reason, the electric field concentration of the gate insulating film 32 in this portion can be relaxed, and the dielectric breakdown of the gate insulating film 32 in this portion can be suppressed.
  • the semiconductor device 3 can have higher reliability.
  • the semiconductor device 4 of the second embodiment is a power semiconductor element called MOSFET, and includes a semiconductor substrate 100, a drain electrode 122 that covers a part of the surface of the semiconductor substrate 100, and a semiconductor substrate.
  • a source electrode 124 covering a part of the surface of the semiconductor substrate 100 and a planar insulating gate part 130 which is a part of the surface of the semiconductor substrate 100 and is disposed between the drain electrode 122 and the source electrode 124 are provided.
  • the semiconductor substrate 100 is a substrate made of silicon carbide (SiC), and includes an n + type drain region 111, an n ⁇ type drift region 112, a p type body region 113, a p + type body contact region 114, An n + -type source region 115 and a p + -type electric field relaxation region 116 are included.
  • the drain region 111, the drift region 112, the body region 113, and the source region 115 are arranged in this order along the surface direction of the semiconductor substrate 10.
  • the drain region 111 is disposed on the surface layer portion of the semiconductor substrate 100 and is exposed on the surface of the semiconductor substrate 100.
  • the drain region 111 is formed by introducing nitrogen or phosphorus into the surface layer portion of the semiconductor substrate 100 using an ion implantation technique.
  • the drain region 111 is in ohmic contact with the drain electrode 122 that coats the surface of the semiconductor substrate 100.
  • the drift region 112 is provided between the drain region 111 and the body region 113 and is exposed on the surface of the semiconductor substrate 100.
  • the drift region 112 is in contact with the lower surface of the insulated gate portion 130.
  • the drift region 112 is configured as a remaining portion in which another semiconductor region of the semiconductor substrate 100 is formed.
  • the body region 113 is disposed in the surface layer portion of the semiconductor substrate 10, is provided between the drift region 112 and the source region 115, and is exposed on the surface of the semiconductor substrate 100. Body region 113 is in contact with the lower surface of insulated gate portion 130. The body region 113 is formed by introducing aluminum or boron into the surface layer portion of the semiconductor substrate 100 using an ion implantation technique.
  • the body contact region 114 is provided on the body region 113, is disposed on the surface layer portion of the semiconductor substrate 100, and is exposed on the surface of the semiconductor substrate 100.
  • the body contact region 114 is formed by introducing aluminum or boron into the surface layer portion of the semiconductor substrate 100 using an ion implantation technique.
  • the body contact region 114 is in ohmic contact with the source electrode 124 that coats the surface of the semiconductor substrate 100.
  • the source region 115 is provided on the body region 113, is disposed on the surface layer portion of the semiconductor substrate 100, and is exposed on the surface of the semiconductor substrate 100. Source region 115 is separated from drift region 112 by body region 113. The source region 115 is in contact with the lower surface of the insulated gate portion 130. The source region 115 is formed by introducing nitrogen or phosphorus into the surface layer portion of the semiconductor substrate 100 using an ion implantation technique. The source region 115 is in ohmic contact with the source electrode 124 that coats the surface of the semiconductor substrate 100.
  • the insulated gate portion 130 is provided on the surface of the semiconductor substrate 100 and includes a gate insulating film 132 and a gate electrode 134.
  • the gate insulating film 132 covers the surface of the semiconductor substrate 100 and is made of silicon oxide.
  • the gate electrode 134 is separated from the source region 115, the body region 113, and the drift region 112 by the gate insulating film 132, and is made of polysilicon.
  • the gate electrode 134 includes an n + type high concentration gate electrode 134a having a relatively high impurity concentration and an n ⁇ type low concentration gate electrode 134b having a relatively low impurity concentration.
  • the boundary between the high-concentration gate electrode 134a and the low-concentration gate electrode 134b is preferably the same as the boundary between the drift region 112 and the body region 113, or located closer to the drain region 111 than the boundary.
  • the high-concentration gate electrode 134a is opposed to the entire range of the body region 113 located between the drift region 112 and the source region 115 via the gate insulating film 132, and the low-concentration gate electrode 134b is opposed to the electric field relaxation region 116.
  • the high-concentration gate electrode 134a is opposed to the entire range of the body region 113 located between the drift region 112 and the source region 115 via the gate insulating film 132, and the low-concentration gate electrode 134b is opposed to the electric field relaxation region 116.
  • the high-concentration gate electrode 134a is opposed to the entire range of the body region 113 located between the drift region 112 and the source region 115 via the gate insulating film 132
  • the low-concentration gate electrode 134b
  • the electric field relaxation region 116 is provided on the drift region 112, is disposed on the surface layer portion of the semiconductor substrate 100, and is exposed on the surface of the semiconductor substrate 100.
  • the electric field relaxation region 116 is disposed corresponding to the drain side end of the insulated gate portion 130, and is disposed closer to the drain region 111 than the gate insulating film 132, and the drain region 111 and the body region are formed by the drift region 112. It is separated from 113.
  • the electric field relaxation region 116 is disposed between the drift region 112 and the gate electrode 134, is in contact with the drift region 112 and the gate electrode 134, and separates the drift region 112 and the gate electrode 134.
  • the n ⁇ type drift region 112, the p + type electric field relaxation region 116, and the n ⁇ type gate electrode 134 are continuously arranged.
  • the drift region 112 and the electric field relaxation region 116 constitute one diode
  • the electric field relaxation region 116 and the gate electrode 134 constitute one diode, and these diodes are arranged in the opposite directions.
  • the electric field relaxation region 116 is formed as a semiconductor layer containing aluminum or boron that spreads on the surface layer portion of the semiconductor substrate 100 using a crystal growth technique or an ion implantation technique, and then is used to etch the drift region 112 using an etching technique. It is formed so as to remain on a part of the surface.
  • the semiconductor device 4 When a positive voltage is applied to the drain electrode 122, the source electrode 124 is grounded, and the gate electrode 134 of the insulated gate portion 130 is grounded, the semiconductor device 4 is off. At this time, in the semiconductor device 4, since a reverse bias is applied to the diode constituted by the drift region 112 and the electric field relaxation region 116, the depletion layer extends from the pn junction between the drift region 112 and the electric field relaxation region 116. For this reason, the drain electrode 122 and the gate electrode 134 are insulated from each other, and leakage current between the drain electrode 122 and the gate electrode 134 is suppressed. Therefore, the semiconductor device 4 can perform a stable off operation.
  • the electric field at the drain side end of the insulated gate portion 130 is relaxed by the depletion layer extending from the pn junction between the drift region 112 and the electric field relaxation region 116.
  • the gate insulating film 132 is not provided at the drain side end portion of the insulating gate portion 130.
  • the drain side end of the insulated gate 130 is a location where electric field concentration is likely to occur.
  • the semiconductor device 4 since the gate insulating film 132 does not exist at a place where electric field concentration is likely to occur, the dielectric breakdown of the gate insulating film 132 is suppressed.
  • the semiconductor device 4 can have high reliability because the dielectric breakdown of the gate insulating film 132 of the insulating gate portion 130 is suppressed.
  • the semiconductor device 4 When a positive voltage is applied to the drain electrode 122, the source electrode 124 is grounded, and a voltage that is more positive than the source electrode 124 is applied to the gate electrode 134 of the insulated gate 130, the semiconductor device 4 is on. At this time, in the semiconductor device 4, since a reverse bias is applied to the diode composed of the electric field relaxation region 116 and the gate electrode 134, the depletion layer extends from the pn junction between the electric field relaxation region 116 and the gate electrode 134. For this reason, the drain electrode 122 and the gate electrode 134 are insulated from each other, and leakage current between the drain electrode 122 and the gate electrode 134 is suppressed. Therefore, the semiconductor device 4 can perform a stable on operation.
  • the semiconductor device 4 can perform stable on and off operations, suppress dielectric breakdown of the gate insulating film 132, and have high reliability.
  • the gate electrode 134 includes the high concentration gate electrode 134 a and the low concentration gate electrode 134 b, the body region 113 located between the drift region 112 and the source region 115. A high-density inversion layer is formed over the entire range, and a low channel resistance is realized.
  • a vertical or horizontal MOSFET Metal Oxide Semiconductor Semiconductor Field Effect Transistor
  • One embodiment of a semiconductor device disclosed in this specification may include a semiconductor substrate and an insulated gate portion.
  • the semiconductor substrate has a first conductivity type drain region, a first conductivity type drift region, a second conductivity type body region, a first conductivity type source region, and a second conductivity type electric field relaxation region,
  • the drain region, the drift region, the body region, and the source region are arranged in this order.
  • the semiconductor device is a vertical type
  • the drain region, the drift region, the body region, and the source region are arranged in this order along the thickness direction of the semiconductor substrate.
  • the insulated gate portion has a gate insulating film and a first conductivity type gate electrode.
  • the gate insulating film is in contact with the drift region, the body region, and the source region.
  • the gate electrode opposes at least a body region located between the drift region and the source region via a gate insulating film.
  • the electric field relaxation region has a portion arranged on the drain region side of the gate insulating film, is in contact with the gate electrode and the drift region, and separates the gate electrode and the drift region.
  • the gate electrode may include a high concentration gate electrode having a relatively high impurity concentration and a low concentration gate electrode having a relatively low impurity concentration.
  • the high-concentration gate electrode faces the entire range of the body region located between the drift region and the source region via the gate insulating film.
  • a low concentration gate electrode is provided between the electric field relaxation region and the high concentration gate electrode.
  • the high-concentration gate electrode can face the region of the body region where the inversion layer is formed. Therefore, when the semiconductor device is on, a sufficient electric field can be applied to the body region, a high-density inversion layer is formed in the body region, and a low channel resistance is realized.
  • the drain region, the drift region, the body region, and the source region are arranged in this order along the thickness direction of the semiconductor substrate, and may be a vertical type.
  • the insulated gate portion is provided in a trench that penetrates the source region and the body region from the surface of the semiconductor substrate and enters the drift region.
  • the gate insulating film covers the side surface of the trench.
  • the gate electrode is exposed on the bottom surface of the trench.
  • the electric field relaxation region is in contact with the gate electrode exposed on the bottom surface of the trench.

Abstract

A semiconductor device which is provided with: a semiconductor substrate which has a drain region of a first conductivity type, a drift region of the first conductivity type, a body region of a second conductivity type, a source region of the first conductivity type and an electric field attenuated region of the second conductivity type, and wherein the drain region, the drift region, the body region and the source region are arranged in this order; and an insulating gate part which faces the drift region, the body region and the source region. The insulating gate part comprises: a gate insulating film which is in contact with the drift region, the body region and the source region; and a gate electrode of the first conductivity type, which faces at least the body region that is positioned between the drift region and the source region, with the gate insulating film being interposed between the gate electrode and the body region. The electric field attenuated region has a portion that is arranged closer to the drain region than the gate insulating film, and is in contact with the drift region and the gate electrode, thereby separating the drift region and the gate electrode from each other.

Description

半導体装置Semiconductor device
　本明細書で開示する技術は、半導体装置に関する。 The technology disclosed in this specification relates to a semiconductor device.
　半導体装置は、トレンチ型又はプレーナ型の絶縁ゲート部を備えることが多い。このような半導体装置では、絶縁ゲート部のドレイン側端部のゲート絶縁膜に電界が集中する。特開平１０－９８１８８号公報は、このような電界集中を緩和するために、トレンチ型の絶縁ゲート部の底部、即ち、絶縁ゲート部のドレイン側端部のゲート絶縁膜に接するようにｐ型の電界緩和領域を設ける技術を開示する。電界緩和領域は、絶縁ゲート部のドレイン側端部のゲート絶縁膜に集中する電界を緩和することができる。 Semiconductor devices often include a trench type or planar type insulating gate portion. In such a semiconductor device, the electric field concentrates on the gate insulating film at the drain side end of the insulated gate. In order to alleviate such electric field concentration, Japanese Patent Laid-Open No. 10-98188 discloses a p-type so as to be in contact with the bottom of the trench-type insulated gate, that is, the gate insulating film at the drain side end of the insulated gate. A technique for providing an electric field relaxation region is disclosed. The electric field relaxation region can relieve the electric field concentrated on the gate insulating film at the drain side end of the insulated gate portion.
　しかしながら、電界緩和領域が設けられていても、絶縁ゲート部のドレイン側端部のゲート絶縁膜に集中する電界によってゲート絶縁膜が絶縁破壊し、半導体装置の信頼性が低下することが懸念される。本明細書は、ゲート絶縁膜の絶縁破壊を抑制し、信頼性の高い半導体装置を提供することを目的とする。 However, even if the electric field relaxation region is provided, there is a concern that the gate insulating film may be broken down due to the electric field concentrated on the gate insulating film at the drain side end of the insulating gate portion, thereby reducing the reliability of the semiconductor device. . It is an object of the present specification to provide a highly reliable semiconductor device in which breakdown of a gate insulating film is suppressed.
　本明細書で開示する半導体装置の一実施形態は、半導体基板及び絶縁ゲート部を備える。半導体基板は、第１導電型のドレイン領域と第１導電型のドリフト領域と第２導電型のボディ領域と第１導電型のソース領域と第２導電型の電界緩和領域を有しており、ドレイン領域とドリフト領域とボディ領域とソース領域がこの順で並んでいる。絶縁ゲート部は、ゲート絶縁膜と第１導電型のゲート電極を有する。ゲート絶縁膜は、ドリフト領域とボディ領域とソース領域に接する。ゲート電極は、少なくともドリフト領域とソース領域の間に位置するボディ領域にゲート絶縁膜を介して対向する。電界緩和領域は、ゲート絶縁膜よりもドレイン領域側に配置されている部分を有しており、ゲート電極とドリフト領域に接しており、ゲート電極とドリフト領域を隔てる。 One embodiment of a semiconductor device disclosed in this specification includes a semiconductor substrate and an insulated gate portion. The semiconductor substrate has a first conductivity type drain region, a first conductivity type drift region, a second conductivity type body region, a first conductivity type source region, and a second conductivity type electric field relaxation region, The drain region, the drift region, the body region, and the source region are arranged in this order. The insulated gate portion has a gate insulating film and a first conductivity type gate electrode. The gate insulating film is in contact with the drift region, the body region, and the source region. The gate electrode opposes at least a body region located between the drift region and the source region via a gate insulating film. The electric field relaxation region has a portion arranged on the drain region side of the gate insulating film, is in contact with the gate electrode and the drift region, and separates the gate electrode and the drift region.
　上記実施形態の半導体装置では、電界緩和領域が、ゲート絶縁膜よりもドレイン領域側に配置されている部分を有するとともにドリフト領域とゲート電極に接するように構成されていることを１つの特徴とする。このため、上記実施形態の半導体装置は、従来構造のドレイン側端部に存在するゲート絶縁膜が電界緩和領域に置き換えられたように構成されている。このように、上記実施形態の半導体装置では、電界集中が起きやすい箇所にそもそもゲート絶縁膜が存在しないことから、ゲート絶縁膜の絶縁破壊が抑制される。また、上記実施形態の半導体装置では、ゲート電極が第１導電型であることを１つの特徴とする。これにより、第１導電型のドリフト領域と第２導電型の電界緩和領域と第１導電型のゲート電極が逆向きに接続された一対のダイオードを構成する。このため、上記実施形態の半導体装置では、ゲート絶縁膜の一部が電界緩和領域に置き換えられたような構成であっても、リーク電流が抑えられ、安定したオン動作及びオフ動作を実行することができる。 One feature of the semiconductor device according to the above embodiment is that the electric field relaxation region has a portion disposed on the drain region side of the gate insulating film and is in contact with the drift region and the gate electrode. . For this reason, the semiconductor device of the above embodiment is configured such that the gate insulating film existing at the drain side end of the conventional structure is replaced with the electric field relaxation region. As described above, in the semiconductor device of the above embodiment, since the gate insulating film does not exist at a place where electric field concentration is likely to occur, the dielectric breakdown of the gate insulating film is suppressed. One feature of the semiconductor device of the above embodiment is that the gate electrode is of the first conductivity type. Thus, a pair of diodes are formed in which the first conductivity type drift region, the second conductivity type electric field relaxation region, and the first conductivity type gate electrode are connected in opposite directions. For this reason, in the semiconductor device of the above-described embodiment, even when the gate insulating film is partially replaced with the electric field relaxation region, the leakage current is suppressed and stable on and off operations are performed. Can do.
第１実施形態の半導体装置の要部断面図を模式的に示す。1 is a schematic cross-sectional view of a main part of a semiconductor device according to a first embodiment. 第１実施形態の変形例の半導体装置の要部断面図を模式的に示す。The principal part sectional drawing of the semiconductor device of the modification of 1st Embodiment is shown typically. 第１実施形態の変形例の半導体装置の要部断面図を模式的に示す。The principal part sectional drawing of the semiconductor device of the modification of 1st Embodiment is shown typically. 第２実施形態の半導体装置の要部断面図を模式的に示す。The principal part sectional view of the semiconductor device of a 2nd embodiment is typically shown.
　図１に示されるように、第１実施形態の半導体装置１は、ＭＯＳＦＥＴと称されるパワー半導体素子であり、半導体基板１０、半導体基板１０の裏面を被覆するドレイン電極２２、半導体基板１０の表面を被覆するソース電極２４及び半導体基板１０の表層部に設けられているトレンチ型の絶縁ゲート部３０を備える。 As shown in FIG. 1, the semiconductor device 1 of the first embodiment is a power semiconductor element called a MOSFET, and includes a semiconductor substrate 10, a drain electrode 22 covering the back surface of the semiconductor substrate 10, and the surface of the semiconductor substrate 10. And a trench-type insulated gate portion 30 provided in the surface layer portion of the semiconductor substrate 10.
　半導体基板１０は、炭化珪素（ＳｉＣ）を材料とする基板であり、ｎ+型のドレイン領域１１、ｎ-型のドリフト領域１２、ｐ型のボディ領域１３、ｐ+型のボディコンタクト領域１４、ｎ+型のソース領域１５及びｐ+型の電界緩和領域１６を有する。ドレイン領域１１とドリフト領域１２とボディ領域１３とソース領域１５は、半導体基板１０の厚み方向に沿ってこの順で並んでいる。 The semiconductor substrate 10 is a substrate made of silicon carbide (SiC), and includes an n + type drain region 11, an n − type drift region 12, a p type body region 13, a p + type body contact region 14, It has an n + type source region 15 and a p + type electric field relaxation region 16. The drain region 11, the drift region 12, the body region 13, and the source region 15 are arranged in this order along the thickness direction of the semiconductor substrate 10.
　ドレイン領域１１は、半導体基板１０の裏層部に配置されており、半導体基板１０の裏面に露出する。ドレイン領域１１は、ドリフト領域１２がエピタキシャル成長するための下地基板でもある。ドレイン領域１１は、半導体基板１０の裏面を被膜するドレイン電極２２にオーミック接触する。一例では、ドレイン領域１１は、その厚みが約１～３００μｍであり、その不純物濃度が約１×１０18～１×１０23ｃｍ-3であるのが望ましい。 The drain region 11 is disposed in the back layer portion of the semiconductor substrate 10 and is exposed on the back surface of the semiconductor substrate 10. The drain region 11 is also a base substrate for the drift region 12 to grow epitaxially. The drain region 11 is in ohmic contact with the drain electrode 22 that coats the back surface of the semiconductor substrate 10. In one example, the drain region 11 preferably has a thickness of about 1 to 300 μm and an impurity concentration of about 1 × 10 18 to 1 × 10 23 cm −3 .
　ドリフト領域１２は、ドレイン領域１１上に設けられている。ドリフト領域１２は、絶縁ゲート部３０の側面に接する。ドリフト領域１２は、エピタキシャル成長技術を利用して、ドレイン領域１１の表面から結晶成長して形成される。一例では、ドリフト領域１２は、その厚みが約５～２００μｍであり、その不純物濃度が約１×１０13～１×１０17ｃｍ-3であるのが望ましい。 The drift region 12 is provided on the drain region 11. The drift region 12 is in contact with the side surface of the insulated gate portion 30. The drift region 12 is formed by crystal growth from the surface of the drain region 11 using an epitaxial growth technique. In one example, the drift region 12 preferably has a thickness of about 5 to 200 μm and an impurity concentration of about 1 × 10 13 to 1 × 10 17 cm −3 .
　ボディ領域１３は、ドリフト領域１２上に設けられており、半導体基板１０の表層部に配置されている。ボディ領域１３は、絶縁ゲート部３０の側面に接する。ボディ領域１３は、エピタキシャル成長技術を利用して、ドリフト領域１２の表面から結晶成長して形成される。一例では、ボディ領域１３は、その厚みが約１～５μｍであり、その不純物濃度が約１×１０16～１×１０18ｃｍ-3であるのが望ましい。 The body region 13 is provided on the drift region 12 and is disposed on the surface layer portion of the semiconductor substrate 10. Body region 13 is in contact with the side surface of insulated gate portion 30. Body region 13 is formed by crystal growth from the surface of drift region 12 using an epitaxial growth technique. In one example, the body region 13 preferably has a thickness of about 1 to 5 μm and an impurity concentration of about 1 × 10 16 to 1 × 10 18 cm −3 .
　ボディコンタクト領域１４は、ボディ領域１３上に設けられており、半導体基板１０の表層部に配置されており、半導体基板１０の表面に露出する。ボディコンタクト領域１４は、イオン注入技術を利用して、半導体基板１０の表層部にアルミニウム又はボロンを導入して形成される。ボディコンタクト領域１４は、半導体基板１０の表面を被膜するソース電極２４にオーミック接触する。一例では、ボディコンタクト領域１４は、そのドーズ量が約１×１０14～１×１０15ｃｍ-2であり、そのピーク濃度が約１×１０19～２×１０20ｃｍ-3であるのが望ましい。 The body contact region 14 is provided on the body region 13, is disposed on the surface layer portion of the semiconductor substrate 10, and is exposed on the surface of the semiconductor substrate 10. The body contact region 14 is formed by introducing aluminum or boron into the surface layer portion of the semiconductor substrate 10 using an ion implantation technique. The body contact region 14 is in ohmic contact with the source electrode 24 that coats the surface of the semiconductor substrate 10. In one example, the body contact region 14 has a dose amount of about 1 × 10 14 to 1 × 10 15 cm −2 and a peak concentration of about 1 × 10 19 to 2 × 10 20 cm −3. desirable.
　ソース領域１５は、ボディ領域１３上に設けられており、半導体基板１０の表層部に配置されており、半導体基板１０の表面に露出する。ソース領域１５は、ボディ領域１３によってドリフト領域１２から隔てられている。ソース領域１５は、絶縁ゲート部３０の側面に接する。ソース領域１５は、イオン注入技術を利用して、半導体基板１０の表層部に窒素又はリンを導入して形成される。ソース領域１５は、半導体基板１０の表面を被膜するソース電極２４にオーミック接触する。一例では、ソース領域１５は、そのドーズ量が約１×１０14～５×１０15ｃｍ-2であり、そのピーク濃度が約１×１０19～５×１０20ｃｍ-3であるのが望ましい。 The source region 15 is provided on the body region 13, is disposed on the surface layer portion of the semiconductor substrate 10, and is exposed on the surface of the semiconductor substrate 10. Source region 15 is separated from drift region 12 by body region 13. The source region 15 is in contact with the side surface of the insulated gate portion 30. The source region 15 is formed by introducing nitrogen or phosphorus into the surface layer portion of the semiconductor substrate 10 using an ion implantation technique. The source region 15 is in ohmic contact with the source electrode 24 that coats the surface of the semiconductor substrate 10. In one example, the source region 15 preferably has a dose of about 1 × 10 14 to 5 × 10 15 cm −2 and a peak concentration of about 1 × 10 19 to 5 × 10 20 cm −3. .
　絶縁ゲート部３０は、半導体基板１０の表面から深部に向けて伸びており、ゲート絶縁膜３２及びゲート電極３４を有する。絶縁ゲート部３０は、ソース領域１５及びボディ領域１３を貫通してドリフト領域１２の一部に侵入するトレンチ３０Ｔ内に設けられている。ゲート絶縁膜３２は、トレンチ３０Ｔの側面を被覆しており、酸化シリコンで構成されている。ゲート絶縁膜３２は、半導体基板１０の表層部にトレンチ３０Ｔを形成した後に、蒸着技術を利用して、そのトレンチ３０Ｔの側面に選択的に堆積することで形成される。ゲート電極３４は、ゲート絶縁膜３２によってソース領域１５、ボディ領域１３及びドリフト領域１２から隔てられており、ｎ-型のポリシリコンで構成されている。特に、ゲート電極３４は、ドリフト領域１２とソース領域１５の間に位置するボディ領域１３に対向しており、この対向部分に反転層を形成するように構成されている。ゲート電極３４は、トレンチ３０Ｔの底面に露出しており、電界緩和領域１６に接する。一例では、ゲート電極３４は、その不純物濃度が約１×１０13～１×１０17ｃｍ-3であるのが望ましい。 The insulated gate portion 30 extends from the surface of the semiconductor substrate 10 toward the deep portion, and includes a gate insulating film 32 and a gate electrode 34. The insulated gate portion 30 is provided in a trench 30T that penetrates the source region 15 and the body region 13 and enters a part of the drift region 12. The gate insulating film 32 covers the side surface of the trench 30T and is made of silicon oxide. The gate insulating film 32 is formed by forming a trench 30T in the surface layer portion of the semiconductor substrate 10 and then selectively depositing the trench 30T on a side surface of the trench 30T using a vapor deposition technique. The gate electrode 34 is separated from the source region 15, the body region 13 and the drift region 12 by the gate insulating film 32, and is made of n − type polysilicon. In particular, the gate electrode 34 is opposed to the body region 13 located between the drift region 12 and the source region 15, and is configured to form an inversion layer in this opposed portion. The gate electrode 34 is exposed on the bottom surface of the trench 30 </ b> T and is in contact with the electric field relaxation region 16. In one example, the gate electrode 34 preferably has an impurity concentration of about 1 × 10 13 to 1 × 10 17 cm −3 .
　電界緩和領域１６は、絶縁ゲート部３０の底部に対応して配置されており、ゲート絶縁膜３２よりもドレイン領域１１側に配置されており、ドリフト領域１２によってドレイン領域１１及びボディ領域１３から隔てられている。電界緩和領域１６は、ドリフト領域１２とゲート電極３４の間に配置されており、ドリフト領域１２とゲート電極３４に接しており、ドリフト領域１２とゲート電極３４を隔てる。このように、ｎ-型のドリフト領域１２とｐ+型の電界緩和領域１６とｎ-型のゲート電極３４が連続して配置されている。これにより、ドリフト領域１２と電界緩和領域１６が１つのダイオードを構成しており、電界緩和領域１６とゲート電極３４が１つのダイオードを構成しており、これらダイオードが逆向きに配置されている。電界緩和領域１６は、半導体基板１０の表層部にトレンチ３０Ｔを形成した後に、エピ成長技術を利用して、トレンチ３０Ｔの底面に選択的に堆積することで形成される。一例では、電界緩和領域１６は、その厚みが約０．１～２μｍであり、その不純物濃度が約１×１０18～１×１０23ｃｍ-3であるのが望ましい。 The electric field relaxation region 16 is disposed corresponding to the bottom of the insulating gate portion 30, is disposed closer to the drain region 11 than the gate insulating film 32, and is separated from the drain region 11 and the body region 13 by the drift region 12. It has been. The electric field relaxation region 16 is disposed between the drift region 12 and the gate electrode 34, is in contact with the drift region 12 and the gate electrode 34, and separates the drift region 12 and the gate electrode 34. As described above, the n − type drift region 12, the p + type electric field relaxation region 16, and the n − type gate electrode 34 are continuously arranged. Thereby, the drift region 12 and the electric field relaxation region 16 constitute one diode, and the electric field relaxation region 16 and the gate electrode 34 constitute one diode, and these diodes are arranged in the opposite directions. The electric field relaxation region 16 is formed by forming the trench 30T in the surface layer portion of the semiconductor substrate 10 and then selectively depositing it on the bottom surface of the trench 30T using an epi growth technique. In one example, it is desirable that the electric field relaxation region 16 has a thickness of about 0.1 to 2 μm and an impurity concentration of about 1 × 10 18 to 1 × 10 23 cm −3 .
　次に、半導体装置１の動作を説明する。ドレイン電極２２に正電圧が印加され、ソース電極２４が接地され、絶縁ゲート部３０のゲート電極３４が接地されていると、半導体装置１はオフである。このとき、半導体装置１では、ドリフト領域１２と電界緩和領域１６で構成されるダイオードに逆バイアスが印加されるので、ドリフト領域１２と電界緩和領域１６の間のｐｎ接合から空乏層が伸びる。このため、ドレイン電極２２とゲート電極３４の間は絶縁され、ドレイン電極２２とゲート電極３４の間にリーク電流が流れることは抑制されている。したがって、半導体装置１は、安定したオフ動作を実行することができる。また、ドリフト領域１２と電界緩和領域１６の間のｐｎ接合から伸びる空乏層により、絶縁ゲート部３０の底部の電界が緩和される。特に、半導体装置１では、絶縁ゲート部３０の底部にゲート絶縁膜３２が設けられていない。絶縁ゲート部３０の底部、即ち、絶縁ゲート部３０のドレイン側端部は電界集中が起きやすい箇所である。半導体装置１では、電界集中が起きやすい箇所にそもそもゲート絶縁膜３２が存在しないことから、ゲート絶縁膜３２の絶縁破壊が抑制される。このように、半導体装置１は、絶縁ゲート部３０のゲート絶縁膜３２の絶縁破壊が抑制され、高い信頼性を有することができる。 Next, the operation of the semiconductor device 1 will be described. When a positive voltage is applied to the drain electrode 22, the source electrode 24 is grounded, and the gate electrode 34 of the insulated gate portion 30 is grounded, the semiconductor device 1 is off. At this time, in the semiconductor device 1, since a reverse bias is applied to the diode constituted by the drift region 12 and the electric field relaxation region 16, the depletion layer extends from the pn junction between the drift region 12 and the electric field relaxation region 16. For this reason, the drain electrode 22 and the gate electrode 34 are insulated from each other, and the leakage current between the drain electrode 22 and the gate electrode 34 is suppressed. Therefore, the semiconductor device 1 can perform a stable off operation. Further, the electric field at the bottom of the insulating gate portion 30 is relaxed by the depletion layer extending from the pn junction between the drift region 12 and the electric field relaxation region 16. In particular, in the semiconductor device 1, the gate insulating film 32 is not provided on the bottom of the insulating gate portion 30. The bottom of the insulated gate 30, that is, the drain side end of the insulated gate 30 is a place where electric field concentration tends to occur. In the semiconductor device 1, since the gate insulating film 32 does not exist in the place where electric field concentration is likely to occur, the dielectric breakdown of the gate insulating film 32 is suppressed. As described above, the semiconductor device 1 can have high reliability because the dielectric breakdown of the gate insulating film 32 of the insulating gate portion 30 is suppressed.
　ドレイン電極２２に正電圧が印加され、ソース電極２４が接地され、絶縁ゲート部３０のゲート電極３４にソース電極２４よりも正となる電圧が印加されていると、半導体装置１はオンである。このとき、半導体装置１では、電界緩和領域１６とゲート電極３４で構成されるダイオードに逆バイアスが印加されるので、電界緩和領域１６とゲート電極３４の間のｐｎ接合から空乏層が伸びる。このため、ドレイン電極２２とゲート電極３４の間は絶縁され、ドレイン電極２２とゲート電極３４の間にリーク電流が流れることは抑制されている。したがって、半導体装置１は、安定したオン動作を実行することができる。 When a positive voltage is applied to the drain electrode 22, the source electrode 24 is grounded, and a voltage that is more positive than the source electrode 24 is applied to the gate electrode 34 of the insulated gate portion 30, the semiconductor device 1 is on. At this time, in the semiconductor device 1, since a reverse bias is applied to the diode composed of the electric field relaxation region 16 and the gate electrode 34, the depletion layer extends from the pn junction between the electric field relaxation region 16 and the gate electrode 34. For this reason, the drain electrode 22 and the gate electrode 34 are insulated from each other, and the leakage current between the drain electrode 22 and the gate electrode 34 is suppressed. Therefore, the semiconductor device 1 can perform a stable on operation.
　上記したように、半導体装置１は、安定したオン動作及びオフ動作を実行することが可能であるとともに、ゲート絶縁膜３２の絶縁破壊が抑制され、高い信頼性を有することができる。さらに、半導体装置１では、絶縁ゲート部３０の底部にゲート絶縁膜３２が存在しないので、帰還容量が極めて小さく、スイッチング速度が向上する。 As described above, the semiconductor device 1 can perform a stable on-operation and off-operation, and can suppress the dielectric breakdown of the gate insulating film 32 and have high reliability. Further, in the semiconductor device 1, since the gate insulating film 32 does not exist at the bottom of the insulating gate portion 30, the feedback capacitance is extremely small and the switching speed is improved.
　図２に、第１実施形態の変形例の半導体装置２を示す。半導体装置２のゲート電極３４は、不純物濃度が相対的に高濃度な高濃度ゲート電極３４ａと不純物濃度が相対的に低濃度な低濃度ゲート電極３４ｂを有する。高濃度ゲート電極３４ａはトレンチ３０Ｔ内の上側部分に配置されており、低濃度ゲート電極３４ｂはトレンチ３０Ｔ内の下側部分に配置されている。高濃度ゲート電極３４ａと低濃度ゲート電極３４ｂの境界が、ドリフト領域１２とボディ領域１３の境界深さと同一又はその境界深さよりも深い位置にあるのが望ましい。換言すると、高濃度ゲート電極３４ａがドリフト領域１２とソース領域１５の間に位置するボディ領域１３の全範囲にゲート絶縁膜３２を介して対向しており、低濃度ゲート電極３４ｂが電界緩和領域１６と高濃度ゲート電極３４ａの間に配置されている。一例では、高濃度ゲート電極３４ａの不純物濃度が約１×１０18～１×１０23ｃｍ-3であるのが望ましく、低濃度ゲート電極３４ｂの不純物濃度が約１×１０13～１×１０17ｃｍ-3であるのが望ましい。 FIG. 2 shows a semiconductor device 2 according to a modification of the first embodiment. The gate electrode 34 of the semiconductor device 2 includes a high concentration gate electrode 34a having a relatively high impurity concentration and a low concentration gate electrode 34b having a relatively low impurity concentration. The high concentration gate electrode 34a is disposed in the upper portion of the trench 30T, and the low concentration gate electrode 34b is disposed in the lower portion of the trench 30T. The boundary between the high-concentration gate electrode 34a and the low-concentration gate electrode 34b is preferably at the same depth as the boundary depth between the drift region 12 and the body region 13 or at a position deeper than the boundary depth. In other words, the high-concentration gate electrode 34a is opposed to the entire range of the body region 13 located between the drift region 12 and the source region 15 via the gate insulating film 32, and the low-concentration gate electrode 34b is opposed to the electric field relaxation region 16. And the high-concentration gate electrode 34a. In one example, the high concentration gate electrode 34a preferably has an impurity concentration of about 1 × 10 18 to 1 × 10 23 cm −3 , and the low concentration gate electrode 34b has an impurity concentration of about 1 × 10 13 to 1 × 10 17. Desirably it is cm −3 .
　半導体装置２では、オンしているときに、電界緩和領域１６と低濃度ゲート電極３４ｂの間のｐｎ接合から伸びる空乏層が、高濃度ゲート電極３４ａ内に深く伸びることが抑制される。このため、半導体装置２では、高濃度ゲート電極３４ａの全体に亘って一定のゲート電圧が印加されるので、ボディ領域１３に対して十分な電界を加えることができる。このため、ドリフト領域１２とソース領域１５の間に位置するボディ領域１３の全範囲に亘って高密度な反転層が形成され、低いチャネル抵抗が実現される。なお、このような効果を得るためには、トレンチ３０Ｔ内の上側部分に低抵抗な導電体が設けられていればよく、例えば、高濃度ゲート電極３４ａに代えて金属が用いられてもよい。 In the semiconductor device 2, when it is turned on, the depletion layer extending from the pn junction between the electric field relaxation region 16 and the low concentration gate electrode 34b is prevented from extending deeply into the high concentration gate electrode 34a. For this reason, in the semiconductor device 2, since a constant gate voltage is applied over the entire high concentration gate electrode 34 a, a sufficient electric field can be applied to the body region 13. For this reason, a high-density inversion layer is formed over the entire range of the body region 13 located between the drift region 12 and the source region 15, and a low channel resistance is realized. In order to obtain such an effect, a low-resistance conductor may be provided on the upper portion in the trench 30T. For example, a metal may be used instead of the high-concentration gate electrode 34a.
　図３に、第１実施形態の変形例の半導体装置３を示す。半導体装置３の電界緩和領域１６は、拡散領域として構成されている。この電界緩和領域１６は、半導体基板１０の表層部にトレンチ３０Ｔを形成した後に、イオン注入技術を利用して、トレンチ３０Ｔの底面にアルミニウム又はボロンを導入して形成される。拡散領域として構成される電界緩和領域１６は、トレンチ３０Ｔの側面を被覆するゲート絶縁膜３２のドレイン側端部を被覆する。このため、この部分のゲート絶縁膜３２の電界集中を緩和することができ、この部分のゲート絶縁膜３２の絶縁破壊を抑制することができる。半導体装置３は、より高い信頼性を有することができる。 FIG. 3 shows a semiconductor device 3 according to a modification of the first embodiment. The electric field relaxation region 16 of the semiconductor device 3 is configured as a diffusion region. The electric field relaxation region 16 is formed by forming the trench 30T in the surface layer portion of the semiconductor substrate 10 and then introducing aluminum or boron into the bottom surface of the trench 30T using an ion implantation technique. The electric field relaxation region 16 configured as a diffusion region covers the drain side end portion of the gate insulating film 32 covering the side surface of the trench 30T. For this reason, the electric field concentration of the gate insulating film 32 in this portion can be relaxed, and the dielectric breakdown of the gate insulating film 32 in this portion can be suppressed. The semiconductor device 3 can have higher reliability.
　図４に示されるように、第２実施形態の半導体装置４は、ＭＯＳＦＥＴと称されるパワー半導体素子であり、半導体基板１００、半導体基板１００の表面の一部を被覆するドレイン電極１２２、半導体基板１００の表面の一部を被覆するソース電極１２４及び半導体基板１００の表面の一部であってドレイン電極１２２とソース電極１２４の間に配置されているプレーナ型の絶縁ゲート部１３０を備える。 As shown in FIG. 4, the semiconductor device 4 of the second embodiment is a power semiconductor element called MOSFET, and includes a semiconductor substrate 100, a drain electrode 122 that covers a part of the surface of the semiconductor substrate 100, and a semiconductor substrate. A source electrode 124 covering a part of the surface of the semiconductor substrate 100 and a planar insulating gate part 130 which is a part of the surface of the semiconductor substrate 100 and is disposed between the drain electrode 122 and the source electrode 124 are provided.
　半導体基板１００は、炭化珪素（ＳｉＣ）を材料とする基板であり、ｎ+型のドレイン領域１１１、ｎ-型のドリフト領域１１２、ｐ型のボディ領域１１３、ｐ+型のボディコンタクト領域１１４、ｎ+型のソース領域１１５及びｐ+型の電界緩和領域１１６を有する。ドレイン領域１１１とドリフト領域１１２とボディ領域１１３とソース領域１１５は、半導体基板１０の面方向に沿ってこの順で並んでいる。 The semiconductor substrate 100 is a substrate made of silicon carbide (SiC), and includes an n + type drain region 111, an n − type drift region 112, a p type body region 113, a p + type body contact region 114, An n + -type source region 115 and a p + -type electric field relaxation region 116 are included. The drain region 111, the drift region 112, the body region 113, and the source region 115 are arranged in this order along the surface direction of the semiconductor substrate 10.
　ドレイン領域１１１は、半導体基板１００の表層部に配置されており、半導体基板１００の表面に露出する。ドレイン領域１１１は、イオン注入技術を利用して、半導体基板１００の表層部に窒素又はリンを導入して形成される。ドレイン領域１１１は、半導体基板１００の表面を被膜するドレイン電極１２２にオーミック接触する。 The drain region 111 is disposed on the surface layer portion of the semiconductor substrate 100 and is exposed on the surface of the semiconductor substrate 100. The drain region 111 is formed by introducing nitrogen or phosphorus into the surface layer portion of the semiconductor substrate 100 using an ion implantation technique. The drain region 111 is in ohmic contact with the drain electrode 122 that coats the surface of the semiconductor substrate 100.
　ドリフト領域１１２は、ドレイン領域１１１とボディ領域１１３の間に設けられており、半導体基板１００の表面に露出する。ドリフト領域１１２は、絶縁ゲート部１３０の下面に接する。ドリフト領域１１２は、半導体基板１００の他の半導体領域を形成した残部として構成されている。 The drift region 112 is provided between the drain region 111 and the body region 113 and is exposed on the surface of the semiconductor substrate 100. The drift region 112 is in contact with the lower surface of the insulated gate portion 130. The drift region 112 is configured as a remaining portion in which another semiconductor region of the semiconductor substrate 100 is formed.
　ボディ領域１１３は、半導体基板１０の表層部に配置されており、ドリフト領域１１２とソース領域１１５の間に設けられており、半導体基板１００の表面に露出する。ボディ領域１１３は、絶縁ゲート部１３０の下面に接する。ボディ領域１１３は、イオン注入技術を利用して、半導体基板１００の表層部にアルミニウム又はボロンを導入して形成される。 The body region 113 is disposed in the surface layer portion of the semiconductor substrate 10, is provided between the drift region 112 and the source region 115, and is exposed on the surface of the semiconductor substrate 100. Body region 113 is in contact with the lower surface of insulated gate portion 130. The body region 113 is formed by introducing aluminum or boron into the surface layer portion of the semiconductor substrate 100 using an ion implantation technique.
　ボディコンタクト領域１１４は、ボディ領域１１３上に設けられており、半導体基板１００の表層部に配置されており、半導体基板１００の表面に露出する。ボディコンタクト領域１１４は、イオン注入技術を利用して、半導体基板１００の表層部にアルミニウム又はボロンを導入して形成される。ボディコンタクト領域１１４は、半導体基板１００の表面を被膜するソース電極１２４にオーミック接触する。 The body contact region 114 is provided on the body region 113, is disposed on the surface layer portion of the semiconductor substrate 100, and is exposed on the surface of the semiconductor substrate 100. The body contact region 114 is formed by introducing aluminum or boron into the surface layer portion of the semiconductor substrate 100 using an ion implantation technique. The body contact region 114 is in ohmic contact with the source electrode 124 that coats the surface of the semiconductor substrate 100.
　ソース領域１１５は、ボディ領域１１３上に設けられており、半導体基板１００の表層部に配置されており、半導体基板１００の表面に露出する。ソース領域１１５は、ボディ領域１１３によってドリフト領域１１２から隔てられている。ソース領域１１５は、絶縁ゲート部１３０の下面に接する。ソース領域１１５は、イオン注入技術を利用して、半導体基板１００の表層部に窒素又はリンを導入して形成される。ソース領域１１５は、半導体基板１００の表面を被膜するソース電極１２４にオーミック接触する。 The source region 115 is provided on the body region 113, is disposed on the surface layer portion of the semiconductor substrate 100, and is exposed on the surface of the semiconductor substrate 100. Source region 115 is separated from drift region 112 by body region 113. The source region 115 is in contact with the lower surface of the insulated gate portion 130. The source region 115 is formed by introducing nitrogen or phosphorus into the surface layer portion of the semiconductor substrate 100 using an ion implantation technique. The source region 115 is in ohmic contact with the source electrode 124 that coats the surface of the semiconductor substrate 100.
　絶縁ゲート部１３０は、半導体基板１００の表面上に設けられており、ゲート絶縁膜１３２及びゲート電極１３４を有する。ゲート絶縁膜１３２は、半導体基板１００の表面を被覆しており、酸化シリコンで構成されている。ゲート電極１３４は、ゲート絶縁膜１３２によってソース領域１１５、ボディ領域１１３及びドリフト領域１１２から隔てられており、ポリシリコンで構成されている。ゲート電極１３４は、不純物濃度が相対的に高濃度なｎ+型の高濃度ゲート電極１３４ａと不純物濃度が相対的に低濃度なｎ-型の低濃度ゲート電極１３４ｂを有する。高濃度ゲート電極１３４ａと低濃度ゲート電極１３４ｂの境界が、ドリフト領域１１２とボディ領域１１３の境界と同一又はその境界よりもドレイン領域１１１側に位置するのが望ましい。換言すると、高濃度ゲート電極１３４ａがドリフト領域１１２とソース領域１１５の間に位置するボディ領域１１３の全範囲にゲート絶縁膜１３２を介して対向しており、低濃度ゲート電極１３４ｂが電界緩和領域１１６と高濃度ゲート電極１３４ａの間に配置されている。 The insulated gate portion 130 is provided on the surface of the semiconductor substrate 100 and includes a gate insulating film 132 and a gate electrode 134. The gate insulating film 132 covers the surface of the semiconductor substrate 100 and is made of silicon oxide. The gate electrode 134 is separated from the source region 115, the body region 113, and the drift region 112 by the gate insulating film 132, and is made of polysilicon. The gate electrode 134 includes an n + type high concentration gate electrode 134a having a relatively high impurity concentration and an n − type low concentration gate electrode 134b having a relatively low impurity concentration. The boundary between the high-concentration gate electrode 134a and the low-concentration gate electrode 134b is preferably the same as the boundary between the drift region 112 and the body region 113, or located closer to the drain region 111 than the boundary. In other words, the high-concentration gate electrode 134a is opposed to the entire range of the body region 113 located between the drift region 112 and the source region 115 via the gate insulating film 132, and the low-concentration gate electrode 134b is opposed to the electric field relaxation region 116. And the high-concentration gate electrode 134a.
　電界緩和領域１１６は、ドリフト領域１１２上に設けられており、半導体基板１００の表層部に配置されており、半導体基板１００の表面に露出する。電界緩和領域１１６は、絶縁ゲート部１３０のドレイン側端部に対応して配置されており、ゲート絶縁膜１３２よりもドレイン領域１１１側に配置されており、ドリフト領域１１２によってドレイン領域１１１及びボディ領域１１３から隔てられている。電界緩和領域１１６は、ドリフト領域１１２とゲート電極１３４の間に配置されており、ドリフト領域１１２とゲート電極１３４に接しており、ドリフト領域１１２とゲート電極１３４を隔てる。このように、ｎ-型のドリフト領域１１２とｐ+型の電界緩和領域１１６とｎ-型のゲート電極１３４が連続して配置されている。これにより、ドリフト領域１１２と電界緩和領域１１６が１つのダイオードを構成しており、電界緩和領域１１６とゲート電極１３４が１つのダイオードを構成しており、これらダイオードが逆向きに配置されている。電界緩和領域１１６は、結晶成長技術又はイオン注入技術を利用して半導体基板１００の表層部に面的に広がるアルミニウム又はボロンを含む半導体層として形成された後に、エッチング技術を利用してドリフト領域１１２の表面上の一部に残存するように形成される。 The electric field relaxation region 116 is provided on the drift region 112, is disposed on the surface layer portion of the semiconductor substrate 100, and is exposed on the surface of the semiconductor substrate 100. The electric field relaxation region 116 is disposed corresponding to the drain side end of the insulated gate portion 130, and is disposed closer to the drain region 111 than the gate insulating film 132, and the drain region 111 and the body region are formed by the drift region 112. It is separated from 113. The electric field relaxation region 116 is disposed between the drift region 112 and the gate electrode 134, is in contact with the drift region 112 and the gate electrode 134, and separates the drift region 112 and the gate electrode 134. As described above, the n − type drift region 112, the p + type electric field relaxation region 116, and the n − type gate electrode 134 are continuously arranged. Thereby, the drift region 112 and the electric field relaxation region 116 constitute one diode, and the electric field relaxation region 116 and the gate electrode 134 constitute one diode, and these diodes are arranged in the opposite directions. The electric field relaxation region 116 is formed as a semiconductor layer containing aluminum or boron that spreads on the surface layer portion of the semiconductor substrate 100 using a crystal growth technique or an ion implantation technique, and then is used to etch the drift region 112 using an etching technique. It is formed so as to remain on a part of the surface.
　次に、半導体装置４の動作を説明する。ドレイン電極１２２に正電圧が印加され、ソース電極１２４が接地され、絶縁ゲート部１３０のゲート電極１３４が接地されていると、半導体装置４はオフである。このとき、半導体装置４では、ドリフト領域１１２と電界緩和領域１１６で構成されるダイオードに逆バイアスが印加されるので、ドリフト領域１１２と電界緩和領域１１６の間のｐｎ接合から空乏層が伸びる。このため、ドレイン電極１２２とゲート電極１３４の間は絶縁され、ドレイン電極１２２とゲート電極１３４の間にリーク電流が流れることは抑制されている。したがって、半導体装置４は、安定したオフ動作を実行することができる。また、ドリフト領域１１２と電界緩和領域１１６の間のｐｎ接合から伸びる空乏層により、絶縁ゲート部１３０のドレイン側端部の電界が緩和される。特に、半導体装置４では、絶縁ゲート部１３０のドレイン側端部にゲート絶縁膜１３２が設けられていない。絶縁ゲート部１３０のドレイン側端部は電界集中が起きやすい箇所である。半導体装置４では、電界集中が起きやすい箇所にそもそもゲート絶縁膜１３２が存在しないことから、ゲート絶縁膜１３２の絶縁破壊が抑制される。このように、半導体装置４は、絶縁ゲート部１３０のゲート絶縁膜１３２の絶縁破壊が抑制され、高い信頼性を有することができる。 Next, the operation of the semiconductor device 4 will be described. When a positive voltage is applied to the drain electrode 122, the source electrode 124 is grounded, and the gate electrode 134 of the insulated gate portion 130 is grounded, the semiconductor device 4 is off. At this time, in the semiconductor device 4, since a reverse bias is applied to the diode constituted by the drift region 112 and the electric field relaxation region 116, the depletion layer extends from the pn junction between the drift region 112 and the electric field relaxation region 116. For this reason, the drain electrode 122 and the gate electrode 134 are insulated from each other, and leakage current between the drain electrode 122 and the gate electrode 134 is suppressed. Therefore, the semiconductor device 4 can perform a stable off operation. Further, the electric field at the drain side end of the insulated gate portion 130 is relaxed by the depletion layer extending from the pn junction between the drift region 112 and the electric field relaxation region 116. In particular, in the semiconductor device 4, the gate insulating film 132 is not provided at the drain side end portion of the insulating gate portion 130. The drain side end of the insulated gate 130 is a location where electric field concentration is likely to occur. In the semiconductor device 4, since the gate insulating film 132 does not exist at a place where electric field concentration is likely to occur, the dielectric breakdown of the gate insulating film 132 is suppressed. As described above, the semiconductor device 4 can have high reliability because the dielectric breakdown of the gate insulating film 132 of the insulating gate portion 130 is suppressed.
　ドレイン電極１２２に正電圧が印加され、ソース電極１２４が接地され、絶縁ゲート部１３０のゲート電極１３４にソース電極１２４よりも正となる電圧が印加されていると、半導体装置４はオンである。このとき、半導体装置４では、電界緩和領域１１６とゲート電極１３４で構成されるダイオードに逆バイアスが印加されるので、電界緩和領域１１６とゲート電極１３４の間のｐｎ接合から空乏層が伸びる。このため、ドレイン電極１２２とゲート電極１３４の間は絶縁され、ドレイン電極１２２とゲート電極１３４の間にリーク電流が流れることは抑制されている。したがって、半導体装置４は、安定したオン動作を実行することができる。 When a positive voltage is applied to the drain electrode 122, the source electrode 124 is grounded, and a voltage that is more positive than the source electrode 124 is applied to the gate electrode 134 of the insulated gate 130, the semiconductor device 4 is on. At this time, in the semiconductor device 4, since a reverse bias is applied to the diode composed of the electric field relaxation region 116 and the gate electrode 134, the depletion layer extends from the pn junction between the electric field relaxation region 116 and the gate electrode 134. For this reason, the drain electrode 122 and the gate electrode 134 are insulated from each other, and leakage current between the drain electrode 122 and the gate electrode 134 is suppressed. Therefore, the semiconductor device 4 can perform a stable on operation.
　上記したように、半導体装置４は、安定したオン及びオフの動作を実行することが可能であるとともに、ゲート絶縁膜１３２の絶縁破壊が抑制され、高い信頼性を有することができる。また、図２に示す半導体装置２と同様に、ゲート電極１３４が高濃度ゲート電極１３４ａと低濃度ゲート電極１３４ｂを有しているので、ドリフト領域１１２とソース領域１１５の間に位置するボディ領域１１３の全範囲に亘って高密度な反転層が形成され、低いチャネル抵抗が実現される。 As described above, the semiconductor device 4 can perform stable on and off operations, suppress dielectric breakdown of the gate insulating film 132, and have high reliability. Similarly to the semiconductor device 2 shown in FIG. 2, since the gate electrode 134 includes the high concentration gate electrode 134 a and the low concentration gate electrode 134 b, the body region 113 located between the drift region 112 and the source region 115. A high-density inversion layer is formed over the entire range, and a low channel resistance is realized.
　以下、本明細書で開示される技術の特徴を整理する。なお、以下に記す事項は、各々単独で技術的な有用性を有している。 The following summarizes the features of the technology disclosed in this specification. The items described below have technical usefulness independently.
　本明細書で開示する半導体装置としては、縦型又は横型のＭＯＳＦＥＴ（Metal Oxide Semiconductor Field Effect Transistor）が例示される。本明細書で開示する半導体装置の一実施形態は、半導体基板及び絶縁ゲート部を備えていてもよい。半導体基板は、第１導電型のドレイン領域と第１導電型のドリフト領域と第２導電型のボディ領域と第１導電型のソース領域と第２導電型の電界緩和領域を有しており、ドレイン領域とドリフト領域とボディ領域とソース領域がこの順で並んでいる。半導体装置が縦型の場合、ドレイン領域とドリフト領域とボディ領域とソース領域が半導体基板の厚み方向に沿ってこの順で並んでいる。半導体基板が横型の場合、ドレイン領域とドリフト領域とボディ領域とソース領域が半導体基板の面方向に沿ってこの順で並んでいる。必要に応じて、これら半導体領域の間に他の半導体領域が介在してもよい。絶縁ゲート部は、ゲート絶縁膜と第１導電型のゲート電極を有する。ゲート絶縁膜は、ドリフト領域とボディ領域とソース領域に接する。ゲート電極は、少なくともドリフト領域とソース領域の間に位置するボディ領域にゲート絶縁膜を介して対向する。電界緩和領域は、ゲート絶縁膜よりもドレイン領域側に配置されている部分を有しており、ゲート電極とドリフト領域に接しており、ゲート電極とドリフト領域を隔てる。 As a semiconductor device disclosed in this specification, a vertical or horizontal MOSFET (Metal Oxide Semiconductor Semiconductor Field Effect Transistor) is exemplified. One embodiment of a semiconductor device disclosed in this specification may include a semiconductor substrate and an insulated gate portion. The semiconductor substrate has a first conductivity type drain region, a first conductivity type drift region, a second conductivity type body region, a first conductivity type source region, and a second conductivity type electric field relaxation region, The drain region, the drift region, the body region, and the source region are arranged in this order. When the semiconductor device is a vertical type, the drain region, the drift region, the body region, and the source region are arranged in this order along the thickness direction of the semiconductor substrate. When the semiconductor substrate is a horizontal type, the drain region, the drift region, the body region, and the source region are arranged in this order along the surface direction of the semiconductor substrate. If necessary, other semiconductor regions may be interposed between these semiconductor regions. The insulated gate portion has a gate insulating film and a first conductivity type gate electrode. The gate insulating film is in contact with the drift region, the body region, and the source region. The gate electrode opposes at least a body region located between the drift region and the source region via a gate insulating film. The electric field relaxation region has a portion arranged on the drain region side of the gate insulating film, is in contact with the gate electrode and the drift region, and separates the gate electrode and the drift region.
　上記半導体装置の一実施形態では、ゲート電極が、不純物濃度が相対的に高濃度な高濃度ゲート電極と不純物濃度が相対的に低濃度な低濃度ゲート電極を有していてもよい。この場合、高濃度ゲート電極が、ドリフト領域とソース領域の間に位置するボディ領域の全範囲にゲート絶縁膜を介して対向する。さらに、低濃度ゲート電極が、電界緩和領域と高濃度ゲート電極の間に設けられている。この態様によると、高濃度ゲート電極が、ボディ領域のうちの反転層が形成される領域に対向することができる。このため、半導体装置がオンのときに、ボディ領域に十分な電界を加えることができ、ボディ領域に高密度な反転層が形成され、低いチャネル抵抗が実現される。 In one embodiment of the semiconductor device, the gate electrode may include a high concentration gate electrode having a relatively high impurity concentration and a low concentration gate electrode having a relatively low impurity concentration. In this case, the high-concentration gate electrode faces the entire range of the body region located between the drift region and the source region via the gate insulating film. Further, a low concentration gate electrode is provided between the electric field relaxation region and the high concentration gate electrode. According to this aspect, the high-concentration gate electrode can face the region of the body region where the inversion layer is formed. Therefore, when the semiconductor device is on, a sufficient electric field can be applied to the body region, a high-density inversion layer is formed in the body region, and a low channel resistance is realized.
　上記半導体装置の一実施形態は、ドレイン領域とドリフト領域とボディ領域とソース領域が半導体基板の厚み方向に沿ってこの順で並んでおり、縦型であってもよい。この場合、絶縁ゲート部が、半導体基板の表面からソース領域及びボディ領域を貫通してドリフト領域に侵入するトレンチ内に設けられている。ゲート絶縁膜は、トレンチの側面を被覆する。ゲート電極は、トレンチの底面に露出する。電界緩和領域が、トレンチの底面に露出するゲート電極に接する。この態様によると、絶縁ゲート部の底部、即ち、絶縁ゲート部のドレイン側端部にゲート絶縁膜が存在しないことから、ゲート絶縁膜の絶縁破壊が抑制される。 In one embodiment of the semiconductor device, the drain region, the drift region, the body region, and the source region are arranged in this order along the thickness direction of the semiconductor substrate, and may be a vertical type. In this case, the insulated gate portion is provided in a trench that penetrates the source region and the body region from the surface of the semiconductor substrate and enters the drift region. The gate insulating film covers the side surface of the trench. The gate electrode is exposed on the bottom surface of the trench. The electric field relaxation region is in contact with the gate electrode exposed on the bottom surface of the trench. According to this aspect, since the gate insulating film does not exist at the bottom of the insulating gate part, that is, the drain side end of the insulating gate part, the dielectric breakdown of the gate insulating film is suppressed.
　以上、本発明の具体例を詳細に説明したが、これらは例示に過ぎず、特許請求の範囲を限定するものではない。特許請求の範囲に記載の技術には、以上に例示した具体例を様々に変形、変更したものが含まれる。また、本明細書または図面に説明した技術要素は、単独であるいは各種の組合せによって技術的有用性を発揮するものであり、出願時請求項記載の組合せに限定されるものではない。また、本明細書または図面に例示した技術は複数目的を同時に達成し得るものであり、そのうちの一つの目的を達成すること自体で技術的有用性を持つものである。 Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings can achieve a plurality of objects at the same time, and has technical usefulness by achieving one of the objects.

Claims (3)

  1. 　第１導電型のドレイン領域と第１導電型のドリフト領域と第２導電型のボディ領域と第１導電型のソース領域と第２導電型の電界緩和領域を有しており、前記ドレイン領域と前記ドリフト領域と前記ボディ領域と前記ソース領域がこの順で並んでいる半導体基板と、
    　前記ドリフト領域と前記ボディ領域と前記ソース領域に対向する絶縁ゲート部と、を備えており、
    　前記絶縁ゲート部は、
    　　前記ドリフト領域と前記ボディ領域と前記ソース領域に接するゲート絶縁膜と、
    　　少なくとも前記ドリフト領域と前記ソース領域の間に位置する前記ボディ領域に前記ゲート絶縁膜を介して対向する第１導電型のゲート電極と、を有しており、
    　前記電界緩和領域は、前記ゲート絶縁膜よりも前記ドレイン領域側に配置されている部分を有しており、前記ドリフト領域と前記ゲート電極に接しており、前記ドリフト領域と前記ゲート電極を隔てる、半導体装置。     A first conductivity type drain region; a first conductivity type drift region; a second conductivity type body region; a first conductivity type source region; and a second conductivity type electric field relaxation region; A semiconductor substrate in which the drift region, the body region, and the source region are arranged in this order;
    An insulating gate portion facing the drift region, the body region, and the source region;
    The insulated gate portion is
    A gate insulating film in contact with the drift region, the body region, and the source region;
    A gate electrode of a first conductivity type facing at least the body region located between the drift region and the source region via the gate insulating film;
    The electric field relaxation region has a portion disposed closer to the drain region than the gate insulating film, is in contact with the drift region and the gate electrode, and separates the drift region and the gate electrode. Semiconductor device.
  2. 　前記ゲート電極は、不純物濃度が相対的に高濃度な高濃度ゲート電極と不純物濃度が相対的に低濃度な低濃度ゲート電極を有しており、
    　前記高濃度ゲート電極が、前記ドリフト領域と前記ソース領域の間に位置する前記ボディ領域の全範囲に前記ゲート絶縁膜を介して対向しており、
    　前記低濃度ゲート電極が、前記電界緩和領域と前記高濃度ゲート電極の間に設けられている、請求項１に記載の半導体装置。     The gate electrode has a high concentration gate electrode having a relatively high impurity concentration and a low concentration gate electrode having a relatively low impurity concentration,
    The high-concentration gate electrode is opposed to the entire range of the body region located between the drift region and the source region via the gate insulating film,
    The semiconductor device according to claim 1, wherein the low concentration gate electrode is provided between the electric field relaxation region and the high concentration gate electrode.
  3. 　前記ドレイン領域と前記ドリフト領域と前記ボディ領域と前記ソース領域が前記半導体基板の厚み方向に沿ってこの順で並んでおり、
    　前記絶縁ゲート部が、前記半導体基板の表面から前記ソース領域及び前記ボディ領域を貫通して前記ドリフト領域に侵入するトレンチ内に設けられており、
    　前記ゲート絶縁膜は、前記トレンチの側面を被覆しており、
    　前記ゲート電極は、前記トレンチの底面に露出しており、
    　前記電界緩和領域が、前記トレンチの底面に露出する前記ゲート電極に接する、請求項１又は２に記載の半導体装置。     The drain region, the drift region, the body region, and the source region are arranged in this order along the thickness direction of the semiconductor substrate,
    The insulated gate portion is provided in a trench that penetrates the source region and the body region from the surface of the semiconductor substrate and enters the drift region;
    The gate insulating film covers a side surface of the trench;
    The gate electrode is exposed on the bottom surface of the trench,
    The semiconductor device according to claim 1, wherein the electric field relaxation region is in contact with the gate electrode exposed on a bottom surface of the trench.
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