TW201735187A - Semiconductor device - Google Patents
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- TW201735187A TW201735187A TW106103970A TW106103970A TW201735187A TW 201735187 A TW201735187 A TW 201735187A TW 106103970 A TW106103970 A TW 106103970A TW 106103970 A TW106103970 A TW 106103970A TW 201735187 A TW201735187 A TW 201735187A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 134
- 239000000758 substrate Substances 0.000 claims abstract description 69
- 230000005684 electric field Effects 0.000 claims abstract description 68
- 210000000746 body region Anatomy 0.000 claims abstract description 17
- 239000012535 impurity Substances 0.000 claims description 15
- 230000000116 mitigating effect Effects 0.000 claims description 3
- 230000002238 attenuated effect Effects 0.000 abstract 2
- 239000002344 surface layer Substances 0.000 description 18
- 238000000034 method Methods 0.000 description 14
- 239000010410 layer Substances 0.000 description 13
- 230000015556 catabolic process Effects 0.000 description 11
- 238000005468 ion implantation Methods 0.000 description 8
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 229910052796 boron Inorganic materials 0.000 description 5
- 238000012986 modification Methods 0.000 description 5
- 230000004048 modification Effects 0.000 description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 229910052757 nitrogen Inorganic materials 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 238000000151 deposition Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- NFFIWVVINABMKP-UHFFFAOYSA-N methylidynetantalum Chemical compound [Ta]#C NFFIWVVINABMKP-UHFFFAOYSA-N 0.000 description 2
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000002040 relaxant effect Effects 0.000 description 2
- 230000006641 stabilisation Effects 0.000 description 2
- 238000011105 stabilization Methods 0.000 description 2
- 229910003468 tantalcarbide Inorganic materials 0.000 description 2
- 239000004020 conductor Substances 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000007888 film coating Substances 0.000 description 1
- 238000009501 film coating Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
在本說明書所揭示之技術係有關半導體裝置。 The technology disclosed in this specification relates to a semiconductor device.
半導體裝置係多為具備溝渠型或平面型的絕緣閘極部者。在如此之半導體裝置中，於絕緣閘極部之汲極側端部的閘極絕緣膜，集中有電場。日本特開平10-98188號公報係揭示：為了緩和如此之電場集中，呈接觸於溝渠型之絕緣閘極部的底部，即，絕緣閘極部之汲極側端部的閘極絕緣膜地，設置p型的電場緩和範圍之技術。電場緩和範圍係可緩和集中於絕緣閘極部之汲極側端部的閘極絕緣膜之電場。 Most of the semiconductor devices are those having a trench type or a planar insulating gate. In such a semiconductor device, an electric field is concentrated on the gate insulating film at the end portion on the drain side of the insulating gate portion. Japanese Laid-Open Patent Publication No. H10-98188 discloses that in order to alleviate such electric field concentration, it is in contact with the bottom of the trench gate type insulating gate portion, that is, the gate insulating film of the drain gate end portion of the insulating gate portion, A technique for setting a p-type electric field relaxation range. The electric field relaxation range can alleviate the electric field of the gate insulating film concentrated on the drain side end portion of the insulating gate portion.
但即使設置有電場緩和範圍，經由集中於絕緣閘極部之汲極側端部的閘極絕緣膜之電場而閘極絕緣膜則亦產生絕緣破壞，而擔憂半導體裝置之信賴性產生下降 之情況。本說明書係抑制閘極絕緣膜之絕緣破壞，而提供信賴性高之半導體裝置者為目的。 However, even if an electric field relaxation range is provided, the gate insulating film is also subjected to dielectric breakdown via an electric field of the gate insulating film concentrated on the drain side end portion of the insulating gate portion, and there is concern that the reliability of the semiconductor device is degraded. The situation. This specification is intended to suppress the dielectric breakdown of the gate insulating film and to provide a highly reliable semiconductor device.
在本說明書所揭示之半導體裝置之一實施形態係具備半導體基板及絕緣閘極部。半導體基板係具有：第1導電型之汲極範圍與第1導電型之漂移範圍與第2導電型之主體範圍與第1導電型之源極範圍與第2導電型之電場緩和範圍，而汲極範圍與漂移範圍與主體範圍與源極範圍則依此順序而排列。絕緣閘極部係具有：閘極絕緣膜與第1導電型之閘極電極。閘極絕緣膜係接觸於漂移範圍與主體範圍與源極範圍。閘極電極係於至少位置在漂移範圍與源極範圍之間的主體範圍，隔著閘極絕緣膜而對向。電場緩和範圍係具有較閘極絕緣膜加以配置於汲極範圍側之部分，而接觸於閘極電極與漂移範圍，隔開閘極電極與漂移範圍。 One embodiment of the semiconductor device disclosed in the present specification includes a semiconductor substrate and an insulating gate portion. The semiconductor substrate has a drift range of the first conductivity type and a drift range of the first conductivity type, a body range of the second conductivity type, and a source range of the first conductivity type and an electric field relaxation range of the second conductivity type, and 汲The range of the pole and the range of the drift and the range of the source and the source are arranged in this order. The insulating gate portion has a gate insulating film and a gate electrode of a first conductivity type. The gate insulating film is in contact with the drift range and the body range and source range. The gate electrode is opposed to the body region at least between the drift range and the source range, and is opposed to each other via the gate insulating film. The electric field relaxation range has a portion where the gate insulating film is disposed on the side of the drain region, and is in contact with the gate electrode and the drift range, and separates the gate electrode from the drift range.
在上述實施形態之半導體裝置中，電場緩和範圍則呈具有較閘極絕緣膜加以配置於汲極範圍側的部份之同時，接觸於漂移範圍與閘極電極地加以構成者，作為1個特徵。因此，上述實施形態之半導體裝置係存在於以往構造之汲極側端部的閘極絕緣膜則呈加以置換為電場緩和範圍地加以構成。如此，在上述實施形態之半導體裝置中，從於容易引起電場集中之處，本來就未存在有閘極絕緣膜之情況，加以抑制閘極絕緣膜之絕緣破壞。另外，在 上述實施形態之半導體裝置中，閘極電極則為第1導電型者為1個特徵。經由此，構成逆方向地加以連接第1導電型之漂移範圍與第2導電型之電場緩和範圍與第1導電型之閘極電極的一對的二極體。因此，在上述實施形態之半導體裝置中，即使閘極絕緣膜之一部分則為呈加以置換為電場緩和範圍之構成，亦可抑制洩放電流，而執行安定之開啟動作及關閉動作者。 In the semiconductor device of the above-described embodiment, the electric field relaxation range is a portion in which the gate insulating film is disposed on the side of the drain region, and is in contact with the drift region and the gate electrode. . Therefore, in the semiconductor device of the above-described embodiment, the gate insulating film which is present at the end portion on the drain side of the conventional structure is replaced with an electric field relaxation range. As described above, in the semiconductor device of the above-described embodiment, the gate insulating film is not originally present from the place where the electric field is likely to be concentrated, and the dielectric breakdown of the gate insulating film is suppressed. In addition, in In the semiconductor device of the above-described embodiment, the gate electrode has one feature as the first conductivity type. Thereby, a pair of diodes in which the drift range of the first conductivity type and the electric field relaxation range of the second conductivity type and the gate electrode of the first conductivity type are connected in the reverse direction are formed. Therefore, in the semiconductor device of the above-described embodiment, even if one portion of the gate insulating film is replaced with an electric field relaxation range, the bleeder current can be suppressed, and the stable opening operation and the closing of the actor can be performed.
1，2，3，4‧‧‧半導體裝置 1,2,3,4‧‧‧Semiconductor devices
10‧‧‧半導體基板 10‧‧‧Semiconductor substrate
11，111‧‧‧n+型之汲極範圍 11,111‧‧‧n + type bungee range
12，112‧‧‧n-型之漂移範圍 12,112‧‧‧n - type drift range
13，113‧‧‧p型之主體範圍 13,113‧‧‧p body range
14，114‧‧‧n+型之源極範圍 Source range of 14,114‧‧n +
16，116‧‧‧p+型之電場緩和範圍 16,116‧‧‧p + type electric field mitigation range
22，122‧‧‧汲極範圍 22,122‧‧‧Bungee range
24，124‧‧‧源極範圍 24,124‧‧‧Source range
30，130‧‧‧絕緣閘極部 30,130‧‧‧Insulated gate
30T‧‧‧溝渠 30T‧‧‧ Ditch
32，132‧‧‧閘極絕緣膜 32,132‧‧‧gate insulating film
34，134‧‧‧閘極電極 34,134‧‧‧gate electrode
34a，134a‧‧‧高濃度閘極電極 34a, 134a‧‧‧High concentration gate electrode
34b，134b‧‧‧低濃度閘極電極 34b, 134b‧‧‧ low concentration gate electrode
100‧‧‧半導體基板 100‧‧‧Semiconductor substrate
圖1係模式性地顯示第1實施形態之半導體裝置的要部剖面圖。 Fig. 1 is a cross-sectional view showing a principal part of a semiconductor device according to a first embodiment.
圖2係模式性地顯示第1實施形態之變形例的半導體裝置的要部剖面圖。 FIG. 2 is a cross-sectional view of a principal part of a semiconductor device according to a modification of the first embodiment.
圖3係模式性地顯示第1實施形態之變形例的半導體裝置的要部剖面圖。 FIG. 3 is a cross-sectional view of a principal part of a semiconductor device according to a modification of the first embodiment.
圖4係模式性地顯示第2實施形態之半導體裝置的要部剖面圖。 Fig. 4 is a cross-sectional view showing the principal part of the semiconductor device of the second embodiment.
如圖1所示，第1實施形態之半導體裝置1係稱為MOSFET之功率半導體元件，而具備：半導體基板10，被覆半導體基板10背面之汲極電極22，被覆半導體基板10表面之源極電極24及加以設置於半導體基板 10表層部之溝渠型的絕緣閘極部30。 As shown in FIG. 1, the semiconductor device 1 of the first embodiment is a power semiconductor device of a MOSFET, and includes a semiconductor substrate 10, a drain electrode 22 covering the back surface of the semiconductor substrate 10, and a source electrode covering the surface of the semiconductor substrate 10. 24 and disposed on the semiconductor substrate 10 trench-type insulating gate portion 30 of the surface layer portion.
半導體基板10係將碳化矽(SiC)作為材料之基板，而具有n+型之汲極範圍11，n-型之漂移範圍12，p型之主體範圍13，p+型之主體接觸範圍14，n+型之源極範圍15及p+型之電場緩和範圍16。汲極範圍11與漂移範圍12與主體範圍13與源極範圍15係沿著半導體基板10之厚度方向而以此順序排列。 The semiconductor substrate 10 is a substrate made of tantalum carbide (SiC), and has a drain range of n + type 11, a drift range of n − type, a body range 13 of p type, and a body contact range 14 of p + type. n + type source 15 and the extreme range of the p + -type electric field relaxing range 16. The drain range 11 and the drift range 12 and the body range 13 and the source range 15 are arranged in this order along the thickness direction of the semiconductor substrate 10.
汲極範圍11係加以配置於半導體基板10之背層部，而露出於半導體基板10的背面。汲極範圍11係漂移範圍12則為了磊晶成長之基底基板。汲極範圍11係電阻接觸於被覆半導體基板10背面之汲極電極22。在一例中，汲極範圍11係其厚度為約1~300μm，而其不純物濃度則約為1×1018~1×1023cm-3者為佳。 The drain region 11 is disposed on the back surface portion of the semiconductor substrate 10 and exposed on the back surface of the semiconductor substrate 10. The drain range is 11 and the drift range is 12 for the epitaxial growth of the base substrate. The drain 11-type resistor is in contact with the drain electrode 22 covering the back surface of the semiconductor substrate 10. In one example, the drain region 11 has a thickness of about 1 to 300 μm, and the impurity concentration is preferably about 1 × 10 18 to 1 × 10 23 cm -3 .
漂移範圍12係加以設置於汲極範圍11上。漂移範圍12係接觸於絕緣閘極部30之側面。漂移範圍12係利用磊晶成長技術，自汲極範圍11之表面進行結晶成長而加以形成。在一例中，漂移範圍12係其厚度為約5~200μm，而其不純物濃度則約為1×1013~1×1017cm-3者為佳。 The drift range 12 is set on the drain range 11. The drift range 12 is in contact with the side of the insulated gate portion 30. The drift range 12 is formed by crystal growth from the surface of the drain region 11 by an epitaxial growth technique. In one example, the drift range 12 is preferably about 5 to 200 μm, and the impurity concentration is preferably about 1 × 10 13 to 1 × 10 17 cm -3 .
主體範圍13係加以設置於漂移範圍12上，再加以配置於半導體基板10的表層部。主體範圍13係接觸於絕緣閘極部30之側面。主體範圍13係利用磊晶成長技術，自漂移範圍12之表面進行結晶成長而加以形成。在一例中，主體範圍13係其厚度為約1~5μm，而其不純 物濃度則約為1×1016~1×1018cm-3者為佳。 The main body range 13 is provided on the drift range 12 and is disposed on the surface layer portion of the semiconductor substrate 10. The body range 13 is in contact with the side of the insulating gate portion 30. The main body range 13 is formed by crystal growth from the surface of the drift range 12 by an epitaxial growth technique. In one example, the main body range 13 has a thickness of about 1 to 5 μm, and the impurity concentration thereof is preferably about 1 × 10 16 to 1 × 10 18 cm -3 .
主體接觸範圍14係加以設置於主體範圍13上，而加以配置於半導體基板10的表層部，露出於半導體基板10的表面。主體接觸範圍14係利用離子注入技術，於半導體基板10的表層部，導入鋁或硼而加以形成。主體接觸範圍14係電阻接觸於被覆半導體基板10表面之源極電極24。在一例中，主體接觸範圍14係其摻雜量約為1×1014~1×1015cm-2，而其最高濃度約為1×1019~2×1020cm-3者為佳。 The main body contact range 14 is provided on the main body range 13 and is disposed on the surface layer portion of the semiconductor substrate 10 to be exposed on the surface of the semiconductor substrate 10. The main body contact range 14 is formed by introducing aluminum or boron into the surface layer portion of the semiconductor substrate 10 by an ion implantation technique. The body contact range 14 is a resistance contact with the source electrode 24 covering the surface of the semiconductor substrate 10. In one example, the body contact range 14 is preferably a doping amount of about 1 × 10 14 to 1 × 10 15 cm -2 , and a maximum concentration of about 1 × 10 19 to 2 × 10 20 cm -3 is preferred.
源極範圍15係加以設置於主體範圍13上，而加以配置於半導體基板10的表層部，露出於半導體基板10的表面。源極範圍15係經由主體範圍13而自漂移範圍12加以隔離。源極範圍15接觸於絕緣閘極部30之側面。源極範圍15係利用離子注入技術，於半導體基板10的表層部，導入氮或磷而加以形成。源極範圍15係電阻接觸於被覆半導體基板10表面之源極電極24。在一例中，源極範圍15係其摻雜量約為1×1014~5×1015cm-2，而其最高濃度約為1×1019~5×1020cm-3者為佳。 The source range 15 is provided on the main body range 13 and is disposed on the surface layer portion of the semiconductor substrate 10 to be exposed on the surface of the semiconductor substrate 10. The source range 15 is isolated from the drift range 12 via the body range 13. The source range 15 is in contact with the side of the insulating gate portion 30. The source range 15 is formed by introducing nitrogen or phosphorus into the surface layer portion of the semiconductor substrate 10 by an ion implantation technique. The source range 15 is in contact with the source electrode 24 covering the surface of the semiconductor substrate 10. In one example, the source range 15 is preferably a doping amount of about 1 × 10 14 to 5 × 10 15 cm -2 , and a maximum concentration of about 1 × 10 19 to 5 × 10 20 cm -3 is preferred.
絕緣閘極部30係自半導體基板10的表面朝向深部，具有閘極絕緣膜32及閘極電極34。絕緣閘極部30係加以設置於貫通源極範圍15及主體範圍13而侵入至漂移範圍12之一部分的溝渠30T內。閘極絕緣膜32係被覆溝渠30T之側面，由氧化矽而加以構成。閘極絕緣膜32係在形成溝渠30T於半導體基板10的表層部之後，利 用蒸鍍技術，由選擇性地堆積於其溝渠30T的側面者而加以形成。閘極電極34係經由閘極絕緣膜32而自源極範圍15，主體範圍13及漂移範圍12加以隔離，由n-型的多晶矽而加以構成。特別是，閘極電極34係對向於位置在漂移範圍12與源極範圍15之間的主體範圍13，呈形成反轉層於此對向部分地加以構成。閘極電極34係露出於溝渠30T之底面，接觸於電場緩和範圍16。在一例中，閘極電極34係其不純物濃度約為1×1013~1×1017cm-3者為佳。 The insulating gate portion 30 has a gate insulating film 32 and a gate electrode 34 from the surface of the semiconductor substrate 10 toward the deep portion. The insulating gate portion 30 is provided in the trench 30T that penetrates the source range 15 and the main body range 13 and enters one of the drift ranges 12 . The gate insulating film 32 is formed on the side surface of the trench 30T and is made of yttrium oxide. The gate insulating film 32 is formed by forming a trench 30T on the surface layer portion of the semiconductor substrate 10, and then selectively depositing it on the side surface of the trench 30T by a vapor deposition technique. The gate electrode 34 is isolated from the source region 15, the main body region 13 and the drift region 12 via the gate insulating film 32, and is configured by an n - type polysilicon. In particular, the gate electrode 34 is opposed to the body region 13 having a position between the drift range 12 and the source range 15, and an inversion layer is formed in the opposite direction. The gate electrode 34 is exposed on the bottom surface of the trench 30T and is in contact with the electric field relaxation range 16. In one example, the gate electrode 34 preferably has an impurity concentration of about 1 × 10 13 to 1 × 10 17 cm -3 .
電場緩和範圍16係對應於絕緣閘極部30之底部而加以配置，較閘極絕緣膜32而加以配置於汲極範圍11側，經由漂移範圍12而自汲極範圍11及主體範圍13加以隔離。電場緩和範圍16係加以配置於漂移範圍12與閘極電極34之間，而接觸於漂移範圍12與閘極電極34，隔離漂移範圍12與閘極電極34。如此，連續而加以配置n-型之漂移範圍12與p+型之電場緩和範圍16與n-型之閘極電極34。經由此，漂移範圍12與電場緩和範圍16則構成1個的二極體，而電場緩和範圍16與閘極電極34則構成1個的二極體，逆方向地加以配置此等二極體。電場緩和範圍16係在形成溝渠30T於半導體基板10的表層部之後，利用磊晶成長技術，由選擇性地堆積於其溝渠30T的底面者而加以形成。在一例中，電場緩和範圍16係其厚度為約0.1~2μm，而其不純物濃度則約為1×1018~1×1023cm-3者為佳。 The electric field relaxation range 16 is disposed corresponding to the bottom of the insulating gate portion 30, is disposed on the side of the drain region 11 from the gate insulating film 32, and is isolated from the drain region 11 and the body region 13 via the drift region 12. . The electric field relaxation range 16 is disposed between the drift range 12 and the gate electrode 34, and is in contact with the drift range 12 and the gate electrode 34, and isolates the drift range 12 from the gate electrode 34. In this manner, the n - type drift range 12 and the p + type electric field relaxation range 16 and the n - type gate electrode 34 are continuously arranged. Thus, the drift range 12 and the electric field relaxation range 16 constitute one diode, and the electric field relaxation range 16 and the gate electrode 34 constitute one diode, and the diodes are arranged in the reverse direction. The electric field relaxation range 16 is formed by selectively depositing the bottom surface of the trench 30T by the epitaxial growth technique after forming the trench 30T on the surface layer portion of the semiconductor substrate 10. In one example, the electric field relaxation range 16 is preferably about 0.1 to 2 μm thick, and the impurity concentration is preferably about 1 × 10 18 to 1 × 10 23 cm -3 .
接著，說明半導體裝置1之動作。施加正電壓於汲極電極22，而加以接地源極電極24，加以接地絕緣閘極部30之閘極電極34時，半導體裝置1係為關閉。此時，在半導體裝置1中，因加以施加逆偏壓於由漂移範圍12與電場緩和範圍16所構成之二極體之故，自漂移範圍12與電場緩和範圍16之間的pn接合，空乏層則延伸。因此，汲極電極22與閘極電極34之間係被絕緣，而加以抑制洩放電流流動於汲極電極22與閘極電極34之間。隨之，半導體裝置1係可執行安定之關閉動作者。另外，經由自漂移範圍12與電場緩和範圍16之間的pn接合延伸的空乏層，而加以緩和絕緣閘極部30之底部的電場。特別是在半導體裝置1中，於絕緣閘極部30之底部，加以設置閘極絕緣膜32。絕緣閘極部30之底部，即絕緣閘極部30之汲極側端部係為容易引起電場集中之處。在半導體裝置1中，從於容易引起電場集中之處，本來就未存在有閘極絕緣膜32之情況，加以抑制閘極絕緣膜32之絕緣破壞。如此，半導體裝置1係可加以抑制絕緣閘極部30之閘極絕緣膜32之絕緣破壞，而具有高信賴性者。 Next, the operation of the semiconductor device 1 will be described. When a positive voltage is applied to the drain electrode 22 and the ground source electrode 24 is applied, and the gate electrode 34 of the grounded insulating gate portion 30 is applied, the semiconductor device 1 is turned off. At this time, in the semiconductor device 1, a reverse bias is applied to the diode composed of the drift range 12 and the electric field relaxation range 16, and the pn junction between the drift range 12 and the electric field relaxation range 16 is depleted. The layer extends. Therefore, the gate electrode 22 and the gate electrode 34 are insulated from each other, and the bleeder current is suppressed from flowing between the gate electrode 22 and the gate electrode 34. Accordingly, the semiconductor device 1 can perform a stable shutdown of the actor. Further, the electric field at the bottom of the insulating gate portion 30 is alleviated via the depletion layer extending from the pn junction between the drift range 12 and the electric field relaxation range 16. In particular, in the semiconductor device 1, a gate insulating film 32 is provided at the bottom of the insulating gate portion 30. The bottom of the insulating gate portion 30, that is, the end portion of the insulating gate portion 30 on the drain side is a place where electric field concentration is easily caused. In the semiconductor device 1, from the point where the electric field concentration is likely to occur, the gate insulating film 32 is not originally present, and the dielectric breakdown of the gate insulating film 32 is suppressed. As described above, the semiconductor device 1 can suppress the dielectric breakdown of the gate insulating film 32 of the insulating gate portion 30, and has high reliability.
施加正電壓於汲極電極22，而加以接地源極電極24，加以施加較源極電極24成為正的電壓於絕緣閘極部30之閘極電極34時，半導體裝置1係為開啟。此時，在半導體裝置1中，因加以施加逆偏壓於由電場緩和範圍16與閘極電極34所構成之二極體之故，自電場緩和 範圍16與閘極電極34之間的pn接合，空乏層則延伸。因此，汲極電極22與閘極電極34之間係被絕緣，而加以抑制洩放電流流動於汲極電極22與閘極電極34之間。隨之，半導體裝置1係可執行安定之開啟動作者。 When a positive voltage is applied to the drain electrode 22 and the ground source electrode 24 is applied, and a voltage higher than the source electrode 24 is applied to the gate electrode 34 of the insulating gate portion 30, the semiconductor device 1 is turned on. At this time, in the semiconductor device 1, since the reverse bias is applied to the diode composed of the electric field relaxation range 16 and the gate electrode 34, the electric field is alleviated. The pn junction between the range 16 and the gate electrode 34 extends the depletion layer. Therefore, the gate electrode 22 and the gate electrode 34 are insulated from each other, and the bleeder current is suppressed from flowing between the gate electrode 22 and the gate electrode 34. Accordingly, the semiconductor device 1 can perform a stable start-up author.
如上述，半導體裝置1係可執行安定之開啟動作及關閉動作之同時，可抑制閘極絕緣膜32之絕緣破壞，而具有高信賴性。更且，在半導體裝置1中，因未存在有閘極絕緣膜32於絕緣閘極部30的底部之故，反饋電容則極小，而開關速度則提升。 As described above, the semiconductor device 1 can perform the opening operation and the closing operation of the stabilization, and can suppress the insulation breakdown of the gate insulating film 32, and has high reliability. Further, in the semiconductor device 1, since the gate insulating film 32 is not present at the bottom of the insulating gate portion 30, the feedback capacitance is extremely small, and the switching speed is improved.
於圖2，顯示第1實施形態之變形例的半導體裝置2。半導體裝置2之閘極電極34係具有不純物濃度為相對性高濃度之高濃度閘極電極34a與不純物濃度為相對性低濃度之低濃度閘極電極34b。高濃度閘極電極34a係加以配置於溝渠30T內之上側部分，而低濃度閘極電極34b係加以配置於溝渠30T內之下側部分。高濃度閘極電極34a與低濃度閘極電極34b之邊界則位於與漂移範圍12與主體範圍13之邊界深度同一或較其邊界深度為深之位置者為佳。換言之，高濃度閘極電極34a則藉由閘極絕緣膜32而對向於位置在漂移範圍12與源極範圍15之間的主體範圍13之全範圍，而低濃度閘極電極34b則加以配置於電場緩和範圍16與高濃度閘極電極34a之間。在一例中，高濃度閘極電極34a之不純物濃度約為1×1018~1×1023cm-3者為佳，而低濃度閘極電極34b之不純物濃度約為1×1013~1×1017cm-3者為佳。 Fig. 2 shows a semiconductor device 2 according to a modification of the first embodiment. The gate electrode 34 of the semiconductor device 2 has a high-concentration gate electrode 34a having a relatively high concentration of impurities and a low-concentration gate electrode 34b having a relatively low concentration of impurities. The high-concentration gate electrode 34a is disposed on the upper side portion of the trench 30T, and the low-concentration gate electrode 34b is disposed on the lower side portion of the trench 30T. It is preferable that the boundary between the high-concentration gate electrode 34a and the low-concentration gate electrode 34b is located at a position which is the same as or deeper than the boundary depth of the drift range 12 and the main body range 13. In other words, the high-concentration gate electrode 34a is opposed to the entire range of the body range 13 between the drift range 12 and the source range 15 by the gate insulating film 32, and the low-concentration gate electrode 34b is disposed. The electric field relaxation range 16 is between the high concentration gate electrode 34a. In one example, the impurity concentration of the high-concentration gate electrode 34a is preferably about 1 × 10 18 to 1 × 10 23 cm -3 , and the impurity concentration of the low-concentration gate electrode 34b is about 1 × 10 13 - 1 × 10 17 cm -3 is better.
在半導體裝置2中，當開啟時，加以抑制自電場緩和範圍16與低濃度閘極電極34b之間的pn接合所延伸之空乏層則深入延伸於高濃度閘極電極34a內者。因此，在半導體裝置2中，因遍布於高濃度閘極電極34a全體而加以施加一定的閘極電壓之故，對於主體範圍13而言可施加充分的電場者。因此，遍布於位置在漂移範圍12與源極範圍15之間的主體範圍13全範圍而加以形成有高密度之反轉層，而實現低通道阻抗。然而，對於為了得到如此之效果，係如於溝渠30T內之上側部分加以設置低阻抗之導電體即可，而例如，取代於高濃度閘極電極34a而使用金屬亦可。 In the semiconductor device 2, when turned on, the depletion layer which is extended from the pn junction between the electric field relaxation range 16 and the low-concentration gate electrode 34b is extended deeper than the high-concentration gate electrode 34a. Therefore, in the semiconductor device 2, since a constant gate voltage is applied throughout the high-concentration gate electrode 34a, a sufficient electric field can be applied to the main body range 13. Therefore, a high-density inversion layer is formed over the entire range of the body range 13 between the drift range 12 and the source range 15, and a low channel impedance is achieved. However, in order to obtain such an effect, a low-impedance conductor may be provided on the upper side portion of the trench 30T, and for example, a metal may be used instead of the high-concentration gate electrode 34a.
於圖3，顯示第1實施形態之變形例的半導體裝置3。半導體裝置3之電場緩和範圍16係作為擴散範圍而加以構成。此電場緩和範圍16係在形成溝渠30T於半導體基板10的表層部之後，利用離子注入技術，導入鋁或硼於溝渠30T的底面而加以形成。作為擴散範圍而加以構成之電場緩和範圍16係被覆溝渠30T之側面，被覆閘極絕緣膜32之汲極側端部。因此，可緩和此部分之閘極絕緣膜32的電場集中，而可抑制此部分之閘極絕緣膜32的絕緣破壞者。半導體裝置3係可具有更高信賴性者。 Fig. 3 shows a semiconductor device 3 according to a modification of the first embodiment. The electric field relaxation range 16 of the semiconductor device 3 is configured as a diffusion range. This electric field relaxation range 16 is formed by introducing aluminum or boron on the bottom surface of the trench 30T by ion implantation using the trench 30T after forming the surface portion of the semiconductor substrate 10. The electric field relaxation range 16 configured as a diffusion range covers the side surface of the trench 30T and covers the end portion of the gate insulating film 32 on the drain side. Therefore, the electric field concentration of the gate insulating film 32 in this portion can be alleviated, and the insulation breakdown of the gate insulating film 32 in this portion can be suppressed. The semiconductor device 3 can have higher reliability.
如圖4所示，第2實施形態之半導體裝置4係為稱為MOSFET之功率半導體元件，具備：半導體基板100，被覆半導體基板100表面之一部分的汲極電極 122，被覆半導體基板100表面之一部分的源極電極124及在半導體基板100表面之一部分，加以配置於汲極電極122與源極電極124之間的平面型之絕緣閘極部130。 As shown in FIG. 4, the semiconductor device 4 of the second embodiment is a power semiconductor element called a MOSFET, and includes a semiconductor substrate 100 and a drain electrode covering a part of the surface of the semiconductor substrate 100. 122. A source electrode 124 covering a part of the surface of the semiconductor substrate 100 and a planar insulating gate portion 130 disposed between the drain electrode 122 and the source electrode 124 on a portion of the surface of the semiconductor substrate 100.
半導體基板100係將碳化矽(SiC)作為材料之基板，而具有n+型之汲極範圍111，n-型之漂移範圍112，p型之主體範圍113，p+型之主體接觸範圍114，n+型之源極範圍115及p+型之電場緩和範圍116。汲極範圍111與漂移範圍112與主體範圍113與源極範圍115係沿著半導體基板10之面方向而以此順序排列。 The semiconductor substrate 100 is a substrate made of tantalum carbide (SiC), and has a n + type drain range 111, an n − type drift range 112, a p type body range 113, and a p + type body contact range 114. the n + -type source electrode 115, and the scope of the p + -type electric field relaxing range 116. The drain range 111 and the drift range 112 and the body range 113 and the source range 115 are arranged in this order along the plane direction of the semiconductor substrate 10.
汲極範圍111係加以配置於半導體基板100之表層部，而露出於半導體基板100的表面。汲極範圍111係利用離子注入技術，於半導體基板100的表層部，導入氮或磷而加以形成。汲極範圍111係電阻接觸於被覆半導體基板100表面之汲極電極122。 The drain region 111 is disposed on the surface layer portion of the semiconductor substrate 100 and exposed on the surface of the semiconductor substrate 100. The drain region 111 is formed by introducing nitrogen or phosphorus into the surface layer portion of the semiconductor substrate 100 by an ion implantation technique. The drain region 111-type resistor is in contact with the drain electrode 122 covering the surface of the semiconductor substrate 100.
漂移範圍112係加以設置於汲極範圍111與主體範圍113之間，而露出於半導體基板100之表面。漂移範圍112係接觸於絕緣閘極部130之下面。漂移範圍112係作為形成半導體基板100之其他的半導體範圍的殘留部而加以構成。 The drift range 112 is provided between the drain range 111 and the body range 113 and is exposed on the surface of the semiconductor substrate 100. The drift range 112 is in contact with the underside of the insulating gate portion 130. The drift range 112 is configured as a residual portion forming another semiconductor range of the semiconductor substrate 100.
主體範圍113係加以配置於半導體基板10之表層部，而加以設置於漂移範圍112與源極範圍115之間，露出於半導體基板100之表面。主體範圍113係接觸於絕緣閘極部130之下面。主體範圍113係利用離子注入技術，於半導體基板100的表層部，導入鋁或硼而加以形 成。 The main body region 113 is disposed on the surface layer portion of the semiconductor substrate 10, and is disposed between the drift region 112 and the source region 115, and is exposed on the surface of the semiconductor substrate 100. The body range 113 is in contact with the underside of the insulating gate portion 130. The main body range 113 is formed by introducing aluminum or boron into the surface layer portion of the semiconductor substrate 100 by an ion implantation technique. to make.
主體接觸範圍114係加以設置於主體範圍113上，而加以配置於半導體基板100的表層部，露出於半導體基板100的表面。主體接觸範圍114係利用離子注入技術，於半導體基板100的表層部，導入鋁或硼而加以形成。主體接觸範圍114係電阻接觸於被覆半導體基板100表面之源極電極124。 The main body contact range 114 is provided on the main body range 113, and is disposed on the surface layer portion of the semiconductor substrate 100 to be exposed on the surface of the semiconductor substrate 100. The main body contact range 114 is formed by introducing aluminum or boron into the surface layer portion of the semiconductor substrate 100 by an ion implantation technique. The body contact range 114 is a resistance contact with the source electrode 124 covering the surface of the semiconductor substrate 100.
源極範圍115係加以設置於主體範圍113上，而加以配置於半導體基板100的表層部，露出於半導體基板100的表面。源極範圍115係經由主體範圍113而自漂移範圍112加以隔離。源極範圍115係接觸於絕緣閘極部130之下面。源極範圍115係利用離子注入技術，於半導體基板100的表層部，導入氮或磷而加以形成。源極範圍115係電阻接觸於被覆半導體基板100表面之源極電極124。 The source range 115 is provided on the body region 113, and is disposed on the surface layer portion of the semiconductor substrate 100, and is exposed on the surface of the semiconductor substrate 100. The source range 115 is isolated from the drift range 112 via the body range 113. The source range 115 is in contact with the underside of the insulating gate portion 130. The source range 115 is formed by introducing nitrogen or phosphorus into the surface layer portion of the semiconductor substrate 100 by an ion implantation technique. The source range 115-type resistor is in contact with the source electrode 124 covering the surface of the semiconductor substrate 100.
絕緣閘極部130係加以設置於半導體基板100之表面上，具有閘極絕緣膜132及閘極電極134。閘極絕緣膜132係被覆半導體基板100之表面，由氧化矽而加以構成。閘極電極134係經由閘極絕緣膜132而自源極範圍115，主體範圍113及漂移範圍112加以隔離，由多晶矽而加以構成。閘極電極134係具有不純物濃度為相對性高濃度之n+型的高濃度閘極電極134a與不純物濃度為相對性低濃度之n-型的低濃度閘極電極134b。高濃度閘極電極134a與低濃度閘極電極134b之邊界則位於與漂移範圍 112與主體範圍113之邊界同一或較其邊界位置於汲極範圍111側者為佳。換言之，高濃度閘極電極134a則藉由閘極絕緣膜132而對向於位置在漂移範圍112與源極範圍115之間的主體範圍113之全範圍，而低濃度閘極電極134b則加以配置於電場緩和範圍116與高濃度閘極電極134a之間。 The insulating gate portion 130 is provided on the surface of the semiconductor substrate 100 and has a gate insulating film 132 and a gate electrode 134. The gate insulating film 132 is coated on the surface of the semiconductor substrate 100 and is made of yttrium oxide. The gate electrode 134 is isolated from the source region 115, the body region 113, and the drift region 112 via the gate insulating film 132, and is formed of polysilicon. The gate electrode 134 is a high-concentration gate electrode 134a having an n + type having a relatively high concentration of impurities, and a low-concentration gate electrode 134b having an n - type having a relatively low concentration of impurities. The boundary between the high concentration gate electrode 134a and the low concentration gate electrode 134b is preferably the same as the boundary between the drift range 112 and the body range 113 or the boundary position on the side of the drain region 111. In other words, the high-concentration gate electrode 134a is opposed to the entire range of the body range 113 between the drift range 112 and the source range 115 by the gate insulating film 132, and the low-concentration gate electrode 134b is disposed. The electric field relaxation range 116 is between the high concentration gate electrode 134a.
電場緩和範圍116係加以設置於漂移範圍112上，而加以配置於半導體基板100的表層部，露出於半導體基板100的表面。電場緩和範圍116係對應於絕緣閘極部130之汲極側端部而加以配置，較閘極絕緣膜132而加以配置於汲極範圍111側，經由漂移範圍112而自汲極範圍111及主體範圍113加以隔離。電場緩和範圍116係加以配置於漂移範圍112與閘極電極134之間，而接觸於漂移範圍112與閘極電極134，隔離漂移範圍112與閘極電極134。如此，連續而加以配置n-型之漂移範圍112與p+型之電場緩和範圍116與n-型之閘極電極134。經由此，漂移範圍112與電場緩和範圍116則構成1個的二極體，而電場緩和範圍116與閘極電極134則構成1個的二極體，逆方向地加以配置此等二極體。電場緩和範圍116係作為利用結晶成長技術或離子注入技術而整面地含有擴散於半導體基板100之表層部的鋁或硼的半導體層而加以形成之後，利用蝕刻技術而呈殘存於漂移範圍112之表面上的一部分地加以形成。 The electric field relaxation range 116 is provided on the drift range 112, and is placed on the surface layer portion of the semiconductor substrate 100 to be exposed on the surface of the semiconductor substrate 100. The electric field relaxation range 116 is disposed corresponding to the drain side end portion of the insulating gate portion 130, and is disposed on the side of the drain region 111 from the gate insulating film 132, and extends from the drain region 111 and the body via the drift region 112. Range 113 is isolated. The electric field relaxation range 116 is disposed between the drift range 112 and the gate electrode 134, and contacts the drift range 112 and the gate electrode 134 to isolate the drift range 112 from the gate electrode 134. In this manner, the n - type drift range 112 and the p + type electric field relaxation range 116 and the n - type gate electrode 134 are continuously arranged. Thus, the drift range 112 and the electric field relaxation range 116 constitute one diode, and the electric field relaxation range 116 and the gate electrode 134 constitute one diode, and the diodes are arranged in the reverse direction. The electric field relaxation range 116 is formed by including a semiconductor layer of aluminum or boron diffused on the surface layer portion of the semiconductor substrate 100 over the entire surface by a crystal growth technique or an ion implantation technique, and then remains in the drift range 112 by an etching technique. A part of the surface is formed.
接著，說明半導體裝置4之動作。施加正電 壓於汲極電極122，而加以接地源極電極124，加以接地絕緣閘極部130之閘極電極134時，半導體裝置4係為關閉。此時，在半導體裝置4中，因加以施加逆偏壓於由漂移範圍112與電場緩和範圍116所構成之二極體之故，自漂移範圍112與電場緩和範圍116之間的pn接合，空乏層則延伸。因此，汲極電極122與閘極電極134之間係被絕緣，而加以抑制洩放電流流動於汲極電極122與閘極電極134之間。隨之，半導體裝置4係可執行安定之關閉動作者。另外，經由自漂移範圍112與電場緩和範圍116之間的pn接合延伸的空乏層，而加以緩和絕緣閘極部130之汲極側端部的電場。特別是在半導體裝置4中，於絕緣閘極部130之汲極側端部，未加以設置閘極絕緣膜132。絕緣閘極部130之汲極側端部係容易引起電場集中之處所。在半導體裝置4中，從於容易引起電場集中之處，本來就未存在有閘極絕緣膜132之情況，加以抑制閘極絕緣膜132之絕緣破壞。如此，半導體裝置4係可加以抑制絕緣閘極部130之閘極絕緣膜132之絕緣破壞，而具有高信賴性者。 Next, the operation of the semiconductor device 4 will be described. Positive electricity When the gate electrode 122 is pressed against the gate electrode 122 and the gate electrode 134 of the grounded insulating gate portion 130 is grounded, the semiconductor device 4 is turned off. At this time, in the semiconductor device 4, since the reverse bias is applied to the diode composed of the drift range 112 and the electric field relaxation range 116, the pn junction between the self-drift range 112 and the electric field relaxation range 116 is deficient. The layer extends. Therefore, the drain electrode 122 and the gate electrode 134 are insulated from each other, and the bleeder current is suppressed from flowing between the drain electrode 122 and the gate electrode 134. Accordingly, the semiconductor device 4 can perform a stable shutdown of the actor. Further, the electric field of the drain-side end portion of the insulating gate portion 130 is alleviated via the depletion layer extending from the pn junction between the drift range 112 and the electric field relaxation range 116. In particular, in the semiconductor device 4, the gate insulating film 132 is not provided at the end portion of the insulating gate portion 130 on the drain side. The end portion of the insulating gate portion 130 on the drain side tends to cause electric field concentration. In the semiconductor device 4, the gate insulating film 132 is not originally present from the place where the electric field concentration is likely to occur, and the dielectric breakdown of the gate insulating film 132 is suppressed. As described above, the semiconductor device 4 can suppress the dielectric breakdown of the gate insulating film 132 of the insulating gate portion 130, and has high reliability.
施加正電壓於汲極電極122，而加以接地源極電極124，加以施加較源極電極124成為正的電壓於絕緣閘極部130之閘極電極134時，半導體裝置4係為開啟。此時，在半導體裝置4中，因加以施加逆偏壓於由電場緩和範圍116與閘極電極134所構成之二極體之故，自電場緩和範圍116與閘極電極134之間的pn接合，空乏層則 延伸。因此，汲極電極122與閘極電極134之間係被絕緣，而加以抑制洩放電流流動於汲極電極122與閘極電極134之間。隨之，半導體裝置4係可執行安定之開啟動作者。 When a positive voltage is applied to the drain electrode 122 and the ground source electrode 124 is applied, and a voltage higher than the source electrode 124 is applied to the gate electrode 134 of the insulating gate portion 130, the semiconductor device 4 is turned on. At this time, in the semiconductor device 4, since the reverse bias is applied to the diode composed of the electric field relaxation range 116 and the gate electrode 134, the pn junction between the electric field relaxation range 116 and the gate electrode 134 is applied. Depleted layer extend. Therefore, the drain electrode 122 and the gate electrode 134 are insulated from each other, and the bleeder current is suppressed from flowing between the drain electrode 122 and the gate electrode 134. Accordingly, the semiconductor device 4 can perform a stable start-up author.
如上述，半導體裝置4係可執行安定之開啟及關閉動作之同時，可抑制閘極絕緣膜132之絕緣破壞，而具有高信賴性。另外，與圖2所示之半導體裝置2同樣地，閘極電極134因具有高濃度閘極電極134a與低濃度閘極電極134b之故，遍布於位置在漂移範圍112與源極範圍115之間的主體範圍113之全範圍而加以形成高密度之反轉層，而實現低通道阻抗。 As described above, the semiconductor device 4 can perform the opening and closing operations of the stabilization, and can suppress the insulation breakdown of the gate insulating film 132, and has high reliability. Further, similarly to the semiconductor device 2 shown in FIG. 2, the gate electrode 134 has a high concentration gate electrode 134a and a low concentration gate electrode 134b, and is disposed between the drift range 112 and the source range 115. The full extent of the body range 113 is formed to form a high density inversion layer to achieve low channel impedance.
以下，整理在本說明書所揭示之技術的特徵。然而，以下記述之事項係在各單獨具有技術性之有用性。 Hereinafter, the features of the technology disclosed in the present specification will be organized. However, the matters described below are technically useful in each case.
作為在本說明書所揭示之半導體裝置，係加以例示有縱型或橫型之MOSFET(Metal Oxide Semiconductor Field Effect Transistor)。在本說明書所揭示之半導體裝置之一實施形態係具備半導體基板及絕緣閘極部亦可。半導體基板係具有：第1導電型之汲極範圍與第1導電型之漂移範圍與第2導電型之主體範圍與第1導電型之源極範圍與第2導電型之電場緩和範圍，而汲極範圍與漂移範圍與主體範圍與源極範圍則依此順序而排列。半導體裝置為縱型之情況，汲極範圍與漂移範圍與主體範圍與源極範圍則沿著半導體基板之厚度方向，依此順序而排列。半導體 基板為橫型之情況，汲極範圍與漂移範圍與主體範圍與源極範圍則沿著半導體基板之面方向，依此順序而排列。因應必要，介入存在有其他的半導體範圍於此等半導體範圍之間亦可。絕緣閘極部係具有：閘極絕緣膜與第1導電型之閘極電極。閘極絕緣膜係接觸於漂移範圍與主體範圍與源極範圍。閘極電極係於至少位置在漂移範圍與源極範圍之間的主體範圍，隔著閘極絕緣膜而對向。電場緩和範圍係具有較閘極絕緣膜加以配置於汲極範圍側之部分，而接觸於閘極電極與漂移範圍，隔開閘極電極與漂移範圍。 As a semiconductor device disclosed in the present specification, a vertical or horizontal MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is exemplified. In one embodiment of the semiconductor device disclosed in the present specification, the semiconductor substrate and the insulating gate portion may be provided. The semiconductor substrate has a drift range of the first conductivity type and a drift range of the first conductivity type, a body range of the second conductivity type, and a source range of the first conductivity type and an electric field relaxation range of the second conductivity type, and 汲The range of the pole and the range of the drift and the range of the source and the source are arranged in this order. In the case where the semiconductor device is vertical, the drain range and the drift range, and the body range and the source range are arranged in the order of the thickness direction of the semiconductor substrate. semiconductor When the substrate is in a horizontal shape, the drain range and the drift range, and the body range and the source range are arranged in the order along the plane of the semiconductor substrate. If necessary, there are other semiconductor ranges that can be interposed between these semiconductor ranges. The insulating gate portion has a gate insulating film and a gate electrode of a first conductivity type. The gate insulating film is in contact with the drift range and the body range and source range. The gate electrode is opposed to the body region at least between the drift range and the source range, and is opposed to each other via the gate insulating film. The electric field relaxation range has a portion where the gate insulating film is disposed on the side of the drain region, and is in contact with the gate electrode and the drift range, and separates the gate electrode from the drift range.
在上述半導體裝置之一實施形態中，閘極電極則具有不純物濃度為相對性高濃度之高濃度閘極電極與不純物濃度為相對性低濃度之低濃度閘極電極。此情況，高濃度閘極電極則於位置在漂移範圍與源極範圍之間的主體範圍之全範圍，隔著閘極絕緣膜而對向。更且，低濃度閘極電極則加以設置於電場緩和範圍與高濃度閘極電極之間。如根據此形態時，高濃度閘極電極則可對向於形成有主體範圍之中的反轉層之範圍者。因此，半導體裝置為開啟時，可加上充分的電場於主體範圍，而加以形成高密度之反轉層於主體範圍，實現低通道阻抗。 In one embodiment of the semiconductor device described above, the gate electrode has a high concentration gate electrode having a relatively high concentration of impurities and a low concentration gate electrode having a relatively low concentration of impurities. In this case, the high-concentration gate electrode is opposed to the entire range of the body between the drift range and the source range, with the gate insulating film interposed therebetween. Moreover, the low concentration gate electrode is disposed between the electric field relaxation range and the high concentration gate electrode. According to this aspect, the high-concentration gate electrode can be opposed to the range in which the inversion layer in the main body range is formed. Therefore, when the semiconductor device is turned on, a sufficient electric field can be added to the main body range, and a high-density inversion layer can be formed in the main body range to achieve low channel impedance.
上述半導體裝置之一實施形態，係汲極範圍與漂移範圍與主體範圍與源極範圍則沿著半導體基板之厚度方向，依此順序而排列，而亦可為縱型。此情況，絕緣閘極部則加以設置於自半導體基板的表面貫通源極範圍及主體範圍，侵入至漂移範圍之溝渠內。閘極絕緣膜係被覆 溝渠的側面。閘極電極係露出於溝渠的底面。電場緩和範圍則接觸於露出於溝渠底面之閘極電極。當根據此形態時，從未存在有閘極絕緣膜於絕緣閘極部的底部，即絕緣閘極部之汲極側端部之情況，加以抑制閘極絕緣膜之絕緣破壞。 In one embodiment of the semiconductor device, the drain range and the drift range, and the body range and the source range are arranged in the order along the thickness direction of the semiconductor substrate, or may be vertical. In this case, the insulating gate portion is provided so as to penetrate the source range and the main body range from the surface of the semiconductor substrate, and enter the trench in the drift range. Gate insulating film coating The side of the ditch. The gate electrode is exposed on the bottom surface of the trench. The electric field relaxation range is in contact with the gate electrode exposed on the bottom surface of the trench. According to this aspect, the gate insulating film is never present at the bottom of the insulating gate portion, that is, the end portion of the insulating gate portion on the drain side, and the dielectric breakdown of the gate insulating film is suppressed.
以上，對於本發明之具體例加以詳細說明過，但此不過是例示，並非限定申請專利範圍者。對於記載於申請專利範圍之技術，係包含有將以上例示之具體例作種種變形，變更者。另外，本說明書或圖面所說明之技術要素係經由單獨或者各種組合而發揮技術性有用性之構成，並非加以限定於申請時申請專利範圍記載之組合者。另外，本說明書或圖面所例示之技術係可同時達成複數目的之構成，而由達成其中一個目的者，本身具有技術性有用性之構成。 The specific examples of the present invention have been described in detail above, but are merely illustrative and are not intended to limit the scope of the claims. The technology described in the scope of the patent application includes various modifications and changes to the specific examples described above. In addition, the technical elements described in the specification or the drawings are technically useful by a single or various combinations, and are not limited to those described in the patent application scope of the application. In addition, the technology exemplified in the present specification or the drawings can achieve a complex number of configurations at the same time, and the composition of one of the objects is technically useful.
1‧‧‧半導體裝置 1‧‧‧Semiconductor device
10‧‧‧半導體基板 10‧‧‧Semiconductor substrate
11‧‧‧n+型之汲極範圍 11‧‧‧n + type bungee range
12‧‧‧n-型之漂移範圍 12‧‧‧n - type drift range
13‧‧‧p型之主體範圍 13‧‧‧p-type body range
14‧‧‧n+型之源極範圍 14‧‧‧n + source range
15‧‧‧源極範圍 15‧‧‧Source range
16‧‧‧p+型之電場緩和範圍 16‧‧‧p + type electric field mitigation range
22‧‧‧汲極範圍 22‧‧‧Bungee range
24‧‧‧源極範圍 24‧‧‧Source range
30‧‧‧絕緣閘極部 30‧‧‧Insulated gate
30T‧‧‧溝渠 30T‧‧‧ Ditch
32‧‧‧閘極絕緣膜 32‧‧‧gate insulating film
34‧‧‧閘極電極 34‧‧‧gate electrode
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