JP6814652B2 - Semiconductor device - Google Patents

Description

The techniques disclosed herein relate to semiconductor devices.

Semiconductor devices called MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) or IGBTs (Insulated Gate Bipolar Transistors) often include trench-type or planar-type insulated gates. Taking MOSFET as an example, it is known that in such a semiconductor device, an electric field is concentrated on the gate insulating film at the drain side end of the insulated gate portion. In Patent Document 1, in order to alleviate such electric field concentration, a p-type electric field relaxation region is provided so as to be in contact with the bottom of the trench-type insulated gate portion, that is, the gate insulating film at the drain side end of the insulating gate portion. Disclose the technology to be provided. The electric field relaxation region can relax the electric field concentrated on the gate insulating film at the drain side end of the insulated gate portion.

JP-A-10-98188

However, even if the electric field relaxation region is provided, there is a concern that the gate insulating film may undergo dielectric breakdown due to the electric field concentrated on the gate insulating film at the drain side end of the insulated gate portion, and the reliability of the semiconductor device may decrease. .. An object of the present specification is to provide a highly reliable semiconductor device by suppressing dielectric breakdown of a gate insulating film.

Semiconductor devices disclosed herein can include, for example, vertical or horizontal MOSFETs, vertical or horizontal IGBTs. One embodiment of the semiconductor device disclosed in the present specification may include a semiconductor substrate, a first main electrode, a second main electrode, and an insulating gate portion. The semiconductor substrate has a first conductive type first semiconductor region, a second conductive type second semiconductor region, a first conductive type third semiconductor region, and a second conductive type gate separation region. The semiconductor region, the second semiconductor region, and the third semiconductor region are arranged in this order along the first direction. When the semiconductor device is a vertical type, the first direction is the thickness direction of the semiconductor substrate, and the first semiconductor region, the second semiconductor region, and the third semiconductor region are arranged in this order along the thickness direction of the semiconductor substrate. When the semiconductor substrate is horizontal, the first direction is the plane direction of the semiconductor substrate, and the first semiconductor region, the second semiconductor region, and the third semiconductor region are arranged in this order along the plane direction of the semiconductor substrate. If necessary, other semiconductor regions may intervene between these semiconductor regions. The first main electrode is in contact with the third semiconductor region. The second main electrode is arranged away from the first main electrode along the first direction. The insulated gate portion has a gate insulating film and a first conductive type gate electrode. The gate insulating film is in contact with the first semiconductor region, the second semiconductor region, and the third semiconductor region. The gate electrode faces at least a portion of the second semiconductor region located between the first semiconductor region and the third semiconductor region via the gate insulating film. The gate separation region has at least a portion arranged on the second main electrode side of the gate insulating film, is in contact with the first semiconductor region and the gate electrode, and separates the first semiconductor region from the gate electrode. There is. The gate separation region is further electrically connected to the first main electrode.

In the semiconductor device of the above embodiment, the gate separation region is configured to have at least a portion arranged on the second main electrode side of the gate insulating film and to be in contact with the first semiconductor region and the gate electrode. It is one of the features. Therefore, the semiconductor device of the above embodiment is configured such that the gate insulating film existing at the end on the side of the second main electrode of the conventional structure is replaced with the gate separation region. As described above, in the semiconductor device of the above embodiment, since the gate insulating film does not exist in the place where the electric field concentration is likely to occur, the dielectric breakdown of the gate insulating film is suppressed. In particular, in the semiconductor device of the above embodiment, since the gate separation region is electrically connected to the first main electrode, the depletion layer width extending from the junction surface between the gate separation region and the first semiconductor region when off is large. It becomes large and the electric field can be relaxed satisfactorily. As a result, the semiconductor device of the above embodiment can have a high withstand voltage. Further, in the semiconductor device of the above embodiment, one feature is that the gate electrode is a first conductive type. As a result, a pair of diodes in which the first conductive type first semiconductor region, the second conductive type gate separation region, and the first conductive type gate electrode are connected in opposite directions are formed. Therefore, in the semiconductor device of the above embodiment, even if a part of the gate insulating film is replaced with a gate separation region, the leakage current is suppressed and stable on and off operations are executed. Can be done.

In the semiconductor device of the above embodiment, the gate electrode may have a high concentration gate electrode having a relatively high impurity concentration and a low concentration gate electrode having a relatively low impurity concentration. The high-concentration gate electrode faces the entire range of the portion of the second semiconductor region located between the first semiconductor region and the third semiconductor region via the gate insulating film. A low concentration gate electrode is provided between the gate separation region and the high concentration gate electrode. According to this aspect, the high concentration gate electrode can face the region of the second semiconductor region where the inversion layer is formed. Therefore, when the semiconductor device is on, a sufficient electric field can be applied to the second semiconductor region, a high-density inversion layer is formed in the second semiconductor region, and low channel resistance is realized.

The semiconductor device of the above embodiment can be configured as a vertical element. In this case, the first direction is the thickness direction of the semiconductor substrate, the first main electrode is provided on the front surface of the semiconductor substrate, and the second main electrode is provided on the back surface of the semiconductor substrate. The insulating gate portion is provided in a trench that penetrates the first semiconductor region from the surface of the semiconductor substrate through the third semiconductor region and the second semiconductor region. The gate insulating film covers the side surface of the trench. The gate electrode is exposed on the bottom surface of the trench. The gate separation region is in contact with the gate electrode exposed on the bottom surface of the trench. According to this aspect, since the gate insulating film does not exist at the bottom of the insulated gate portion, that is, at the end of the insulated gate portion on the second main electrode side, dielectric breakdown of the gate insulating film is suppressed.

When the semiconductor device of the above embodiment is configured as a vertical element, the semiconductor device can further have a connection region. The connection region extends along the thickness direction of the semiconductor substrate and is in contact with the gate separation region. The connection region is arranged outside the end portion of the insulating gate portion in the longitudinal direction when observed from a direction orthogonal to the surface of the semiconductor substrate. The gate separation region is electrically connected to the first main electrode via the connection region. Various materials can be used for the connection region as long as the gate separation region and the first main electrode can be electrically connected. For example, the connection region can be a second conductive type semiconductor. In this aspect, the connection area is arranged outside the range in which the insulated gate portion is provided. As a result, the gate separation region and the first main electrode can be electrically connected via the connection region without impairing the characteristics of the channel region formed by the insulated gate portion.

It is sectional drawing of the main part of the semiconductor device of 1st Embodiment, and the sectional view corresponding to line I (I) of FIG. 2 is schematically shown. It is sectional drawing of the main part of the semiconductor device of 1st Embodiment, and the sectional view corresponding to line II-II of FIG. 1 is schematically shown. It is sectional drawing of the main part of the semiconductor device of 1st Embodiment, and the sectional view corresponding to line III-III of FIG. 2 is schematically shown. The withstand voltage characteristics of the semiconductor device of the first embodiment and the semiconductor device of the comparative example are shown. The forward characteristics of the built-in diode of the semiconductor device of the first embodiment and the semiconductor device of the comparative example are shown. A sectional view of a main part of a modified example of the semiconductor device of the first embodiment is schematically shown. A sectional view of a main part of a modified example of the semiconductor device of the first embodiment is schematically shown. The cross-sectional view of the main part of the semiconductor device of the second embodiment is schematically shown.

(First Embodiment) As shown in FIGS. 1 to 3, the semiconductor device 1 is a power semiconductor element called a MOSFET, and is a semiconductor substrate 10, a drain electrode 22 that covers the back surface of the semiconductor substrate 10, and a semiconductor substrate. The source electrode 24 that covers the surface of the semiconductor substrate 10 and the trench-type insulating gate portion 30 provided on the surface layer portion of the semiconductor substrate 10 are provided. The source electrode 24 is an example of the first main electrode, and the drain electrode 22 is an example of the second main electrode.

The semiconductor substrate 10 is a substrate made of silicon carbide (SiC), and has an n ⁺ type drain region 11, an n ^- type drift region 12, a p-type body region 13, a p ⁺ type body contact region 14, and the like. It has an n ⁺ type source region 15, a p ⁺ type gate separation region 16 and a p ⁺ type connection region 17. The drain region 11, the drift region 12, the body region 13, and the source region 15 are arranged in this order along the thickness direction of the semiconductor substrate 10.

The drain region 11 is arranged on the back layer portion of the semiconductor substrate 10 and is exposed on the back surface of the semiconductor substrate 10. The drain region 11 is also a base substrate for epitaxially growing the drift region 12. The drain region 11 makes ohmic contact with the drain electrode 22 that coats the back surface of the semiconductor substrate 10. In one example, the drain region 11 has a thickness of about 1 to 300 μm and an impurity concentration of about 1 × 10 ¹⁸ to 1 × 10 ²³ cm ^-3 .

The drift region 12 is provided on the drain region 11. The drift region 12 is in contact with the side surface of the insulated gate portion 30. The drift region 12 is formed by crystal growth from the surface of the drain region 11 using an epitaxial growth technique. In one example, the drift region 12 has a thickness of about 5 to 200 μm and an impurity concentration of about 1 × 10 ¹³ to 1 × 10 ¹⁷ cm ^-3 . The drift region 12 is an example of the first semiconductor region.

The body region 13 is provided on the drift region 12 and is arranged on the surface layer portion of the semiconductor substrate 10. The body region 13 is in contact with the side surface of the insulated gate portion 30. The body region 13 is formed by crystal growth from the surface of the drift region 12 by utilizing an epitaxial growth technique. In one example, the body region 13 has a thickness of about 1-5 μm and an impurity concentration of about 1 × 10 ¹⁶ to 1 × 10 ¹⁸ cm ^-3 . The body region 13 is an example of the second semiconductor region.

The body contact region 14 is provided on the body region 13, is arranged on the surface layer portion of the semiconductor substrate 10, and is exposed on the surface of the semiconductor substrate 10. The body contact region 14 makes ohmic contact with the source electrode 24 that coats the surface of the semiconductor substrate 10. The body contact region 14 is formed by introducing aluminum or boron into the surface layer portion of the semiconductor substrate 10 by utilizing ion implantation technology. In one example, the body contact region 14 has a dose amount of about 1 × 10 ¹⁴ to 1 × 10 ¹⁵ cm- ² and a peak concentration of about 1 × 10 ¹⁹ to 2 × 10 ²⁰ cm ^-3 .

The source region 15 is provided on the body region 13, is arranged on the surface layer portion of the semiconductor substrate 10, and is exposed on the surface of the semiconductor substrate 10. The source region 15 is separated from the drift region 12 by the body region 13. The source region 15 is in contact with the side surface of the insulated gate portion 30. The source region 15 makes ohmic contact with the source electrode 24 that coats the surface of the semiconductor substrate 10. The source region 15 is formed by introducing nitrogen or phosphorus into the surface layer portion of the semiconductor substrate 10 by utilizing the ion implantation technique. In one example, the source region 15 has a dose of about 1 × 10 ^{14 to} 5 × 10 ¹⁵ cm- ² and a peak concentration of about 1 × 10 ^{19 to} 5 × 10 ²⁰ cm ^-3 . The source region 15 is an example of a third semiconductor region.

The insulating gate portion 30 extends from the surface of the semiconductor substrate 10 toward the deep portion, and has a gate insulating film 32 and a gate electrode 34. The insulated gate portion 30 is provided in the trench 30T that penetrates the source region 15 and the body region 13 and penetrates a part of the drift region 12. The gate insulating film 32 covers the side surface of the trench 30T and is made of silicon oxide. The gate insulating film 32 is formed by forming a trench 30T on the surface layer portion of the semiconductor substrate 10 and then selectively depositing the trench 30T on the side surface of the trench 30T by using CVD (Chemical Vapor Deposition) technology. The gate electrode 34 is separated from the source region 15, the body region 13, and the drift region 12 by the gate insulating film 32, and is made of n ^- type polysilicon. In particular, the gate electrode 34 faces a portion of the body region 13 located between the drift region 12 and the source region 15, and is configured to form an inversion layer in the facing portion. The gate electrode 34 is exposed on the bottom surface of the trench 30T and is in contact with the gate separation region 16. In one example, the gate electrode 34 has an impurity concentration of about 1 × 10 ¹³ to 1 × 10 ¹⁷ cm ^-3 .

The gate separation region 16 is arranged corresponding to the bottom of the insulated gate portion 30, is arranged on the drain electrode 22 side of the gate insulating film 32, and is separated from the drain region 11 and the body region 13 by the drift region 12. Has been done. The gate separation region 16 is arranged between the drift region 12 and the gate electrode 34, is in contact with the drift region 12 and the gate electrode 34, and separates the drift region 12 from the gate electrode 34. In this way, the n ^- type drift region 12, the p ⁺ -type gate separation region 16, and the n ^- type gate electrode 34 are continuously arranged. As a result, the drift region 12 and the gate separation region 16 form one pn diode, the gate separation region 16 and the gate electrode 34 form one pn diode, and these pn diodes are arranged in opposite directions. ing. The gate separation region 16 is formed by forming a trench 30T on the surface layer portion of the semiconductor substrate 10 and then selectively depositing the trench 30T on the bottom surface of the trench 30T by using epi-growth technology. In one example, the gate separation region 16 has a thickness of about 0.1 to 2 μm and an impurity concentration of about 1 × 10 ¹⁸ to 1 × 10 ²³ cm ^-3 .

The connection region 17 is arranged outside the end portion of the insulating gate portion 30 in the longitudinal direction when observed from a direction orthogonal to the surface of the semiconductor substrate 10. The connection region 17 extends along the thickness direction of the semiconductor substrate 10 along the side surface of the end portion in the longitudinal direction of the insulating gate portion 30. One end of the connection region 17 is in contact with the gate separation region 16, and the other end of the connection region 17 is exposed on the surface of the semiconductor substrate 10 and is in contact with the source electrode 24. The connection region 17 makes ohmic contact with the source electrode 24 that coats the surface of the semiconductor substrate 10. In this way, the connection region 17 electrically connects the gate separation region 16 and the source electrode 24. The connection region 17 may not be in contact with the source electrode 24 as long as it extends from the gate separation region 16 to the body region 13 beyond the drift region 12. Since the body region 13 is electrically connected to the source electrode 24, even in this case, the connection region 17 can electrically connect the gate separation region 16 and the source electrode 24. In the connection region 17, after forming the trench 30T for the insulating gate portion 30 on the surface layer portion of the semiconductor substrate 10, aluminum or boron is introduced into the side surface of the end portion in the longitudinal direction of the trench 30T by using the oblique ion implantation technique. Is formed. In one example, the impurity concentration in the contiguous zone 17 is about 1 × 10 ¹⁸ to 1 × 10 ²³ cm ^-3 .

Next, the operation of the semiconductor device 1 will be described. When a positive voltage is applied to the drain electrode 22, the source electrode 24 is grounded, and the gate electrode 34 of the insulated gate portion 30 is grounded, the semiconductor device 1 is turned off. At this time, in the semiconductor device 1, since the reverse bias is applied to the pn diode composed of the drift region 12 and the gate separation region 16, the depletion layer extends from the pn junction between the drift region 12 and the gate separation region 16. Therefore, the drain electrode 22 and the gate electrode 34 are insulated from each other, and the leakage current is suppressed from flowing between the drain electrode 22 and the gate electrode 34. Therefore, the semiconductor device 1 can perform a stable off operation. Further, the depletion layer extending from the pn junction between the drift region 12 and the gate separation region 16 relaxes the electric field at the bottom of the insulated gate portion 30. In particular, in the semiconductor device 1, the gate insulating film 32 is not provided at the bottom of the insulating gate portion 30. The bottom of the insulated gate portion 30, that is, the drain-side end of the insulated gate portion 30, is a place where electric field concentration is likely to occur. In the semiconductor device 1, since the gate insulating film 32 does not exist in the place where the electric field concentration is likely to occur, the dielectric breakdown of the gate insulating film 32 is suppressed. In this way, the semiconductor device 1 can have high reliability by suppressing dielectric breakdown of the gate insulating film 32 of the insulating gate portion 30.

When a positive voltage is applied to the drain electrode 22, the source electrode 24 is grounded, and a voltage more positive than that of the source electrode 24 is applied to the gate electrode 34 of the insulated gate portion 30, the semiconductor device 1 is turned on. At this time, in the semiconductor device 1, since the reverse bias is applied to the pn diode composed of the gate separation region 16 and the gate electrode 34, the depletion layer extends from the pn junction between the gate separation region 16 and the gate electrode 34. Therefore, the drain electrode 22 and the gate electrode 34 are insulated from each other, and the leakage current is suppressed from flowing between the drain electrode 22 and the gate electrode 34. Therefore, the semiconductor device 1 can perform a stable on-operation.

As described above, the semiconductor device 1 can perform stable on-operation and off-operation, and can suppress dielectric breakdown of the gate insulating film 32 and have high reliability. Further, in the semiconductor device 1, since the gate insulating film 32 does not exist at the bottom of the insulated gate portion 30, the feedback capacitance is extremely small and the switching speed is improved.

FIG. 4 shows the withstand voltage characteristics of the semiconductor device 1. Here, the comparative example is an example in which the gate separation region 16 is not connected to the source electrode 24. As shown in FIG. 4, the semiconductor device 1 can have a higher withstand voltage as compared with the comparative example. In the semiconductor device 1, since the gate separation region 16 is electrically connected to the source electrode 24, the gate separation region 16 is fixed to the ground potential. As a result, when the semiconductor device 1 is off, the width of the depletion layer extending from the pn junction between the drift region 12 and the gate separation region 16 is increased, and the electric field at the bottom of the insulated gate portion 30 is satisfactorily relaxed. Therefore, the semiconductor device 1 can have a high withstand voltage.

FIG. 5 shows the forward voltage characteristics of the built-in diode of the semiconductor device 1. Here, the comparative example is an example in which the gate separation region 16 is not connected to the source electrode 24. As shown in FIG. 5, the built-in diode of the semiconductor device 1 can have a lower forward voltage as compared with the comparative example. In the semiconductor device 1, in addition to the pn diode composed of the body region 13 and the drift region 12, the gate separation region 16 is connected to the source electrode 24, so that the semiconductor device 1 is composed of the gate separation region 16 and the drift region 12. The pn diode can also operate as a built-in diode. Further, a pn diode composed of a connection region 17 and a drift region 12 can also operate as a built-in diode. As a result, the built-in diode of the semiconductor device 1 can have a low forward voltage.

FIG. 6 shows a modified semiconductor device 2. The gate electrode 34 of the semiconductor device 2 has a high-concentration gate electrode 34a having a relatively high impurity concentration and a low-concentration gate electrode 34b having a relatively low impurity concentration. The high-concentration gate electrode 34a is arranged in the upper portion in the trench 30T, and the low-concentration gate electrode 34b is arranged in the lower portion in the trench 30T. It is desirable that the boundary between the high-concentration gate electrode 34a and the low-concentration gate electrode 34b is the same as or deeper than the boundary depth between the drift region 12 and the body region 13. In other words, the high-concentration gate electrode 34a faces the entire range of the body region 13 located between the drift region 12 and the source region 15 via the gate insulating film 32, and the low-concentration gate electrode 34b is gate-separated. It is arranged between the region 16 and the high concentration gate electrode 34a. In one example, the impurity concentration of the high concentration gate electrode 34a is about 1 × 10 ¹⁸ to 1 × 10 ²³ cm ^-3 , and the impurity concentration of the low concentration gate electrode 34b is about 1 × 10 ¹³ to 1 × 10 ¹⁷ cm ^-3. Is.

In the semiconductor device 2, when the semiconductor device 2 is turned on, the depletion layer extending from the pn junction between the gate separation region 16 and the low-concentration gate electrode 34b is suppressed from extending deeply into the high-concentration gate electrode 34a. Therefore, in the semiconductor device 2, a constant gate voltage is applied over the entire high-concentration gate electrode 34a, so that a sufficient electric field can be applied to the body region 13. Therefore, a high-density inversion layer is formed over the entire range of the body region 13 located between the drift region 12 and the source region 15, and low channel resistance is realized. In order to obtain such an effect, a low-resistance conductor may be provided in the upper portion of the trench 30T, and for example, a metal may be used instead of the high-concentration gate electrode 34a.

FIG. 7 shows a modified semiconductor device 3. The gate separation region 16 of the semiconductor device 3 is configured as a diffusion region. The gate separation region 16 is formed by forming a trench 30T on the surface layer portion of the semiconductor substrate 10 and then introducing aluminum or boron into the bottom surface of the trench 30T by using an ion implantation technique. The gate separation region 16 configured as a diffusion region covers the drain side end portion of the gate insulating film 32 that covers the side surface of the trench 30T. Therefore, the electric field concentration of the gate insulating film 32 in this portion can be relaxed, and the dielectric breakdown of the gate insulating film 32 in this portion can be suppressed. The semiconductor device 3 can have higher reliability. Further, since the gate separation region 16 can be formed in the same process as the connection region 17, it is also useful in terms of reducing the manufacturing cost.

(Second Embodiment) As shown in FIG. 8, the semiconductor device 4 is a power semiconductor element called a MOSFET, and is a semiconductor substrate 100, a drain electrode 122 that covers a part of the surface of the semiconductor substrate 100, and a semiconductor. A source electrode 124 that covers a part of the surface of the substrate 100 and a planar type insulating gate 130 that is a part of the surface of the semiconductor substrate 100 and is arranged between the drain electrode 122 and the source electrode 124 are provided.

The semiconductor substrate 100 is a substrate made of silicon carbide (SiC), and has an n ⁺ type drain region 111, an n ^- type drift region 112, a p-type body region 113, and a p ⁺ type body contact region 114. It has an n ⁺ type source region 115 and a p ⁺ type gate separation region 116. The drain region 111, the drift region 112, the body region 113, and the source region 115 are arranged in this order along the plane direction of the semiconductor substrate 10.

The drain region 111 is arranged on the surface layer portion of the semiconductor substrate 100 and is exposed on the surface of the semiconductor substrate 100. The drain region 111 is formed by introducing nitrogen or phosphorus into the surface layer portion of the semiconductor substrate 100 by utilizing the ion implantation technique. The drain region 111 makes ohmic contact with the drain electrode 122 that coats the surface of the semiconductor substrate 100.

The drift region 112 is provided between the drain region 111 and the body region 113, and is exposed on the surface of the semiconductor substrate 100. The drift region 112 is in contact with the lower surface of the insulated gate portion 130. The drift region 112 is configured as a remainder forming another semiconductor region of the semiconductor substrate 100. The drift region 112 is an example of the first semiconductor region.

The body region 113 is arranged on the surface layer portion of the semiconductor substrate 10, is provided between the drift region 112 and the source region 115, and is exposed on the surface of the semiconductor substrate 100. The body region 113 is in contact with the lower surface of the insulated gate portion 130. The body region 113 is formed by introducing aluminum or boron into the surface layer portion of the semiconductor substrate 100 by utilizing ion implantation technology. The body region 113 is an example of the second semiconductor region.

The body contact region 114 is provided on the body region 113, is arranged on the surface layer portion of the semiconductor substrate 100, and is exposed on the surface of the semiconductor substrate 100. The body contact region 114 is formed by introducing aluminum or boron into the surface layer portion of the semiconductor substrate 100 by utilizing ion implantation technology. The body contact region 114 makes ohmic contact with the source electrode 124 that coats the surface of the semiconductor substrate 100.

The source region 115 is provided on the body region 113, is arranged on the surface layer portion of the semiconductor substrate 100, and is exposed on the surface of the semiconductor substrate 100. The source region 115 is separated from the drift region 112 by the body region 113. The source region 115 is in contact with the lower surface of the insulated gate 130. The source region 115 makes ohmic contact with the source electrode 124 that coats the surface of the semiconductor substrate 100. The source region 115 is formed by introducing nitrogen or phosphorus into the surface layer portion of the semiconductor substrate 100 by utilizing the ion implantation technique. The source region 115 is an example of the third semiconductor region.

The insulating gate portion 130 is provided on the surface of the semiconductor substrate 100, and has a gate insulating film 132 and a gate electrode 134. The gate insulating film 132 covers the surface of the semiconductor substrate 100 and is made of silicon oxide. The gate electrode 134 is separated from the source region 115, the body region 113, and the drift region 112 by a gate insulating film 132, and is made of n-type polysilicon. The gate electrode 134 has a high concentration gate electrode 134a having a relatively high impurity concentration and a low concentration gate electrode 134b having a relatively low impurity concentration. It is desirable that the boundary between the high-concentration gate electrode 134a and the low-concentration gate electrode 134b is the same as the boundary between the drift region 112 and the body region 113 or located on the drain side of the boundary. In other words, the high-concentration gate electrode 134a faces the entire range of the body region 113 located between the drift region 112 and the source region 115 via the gate insulating film 132, and the low-concentration gate electrode 134b is gate-separated. It is arranged between the region 116 and the high concentration gate electrode 134a.

The gate separation region 116 is provided on the drift region 112, is arranged on the surface layer portion of the semiconductor substrate 100, and is exposed on the surface of the semiconductor substrate 100. The gate separation region 116 is arranged corresponding to the drain side end portion of the insulated gate portion 130, is arranged on the drain electrode 122 side of the gate insulating film 132, and is arranged on the drain electrode 122 side by the drift region 112. It is separated from 113. The gate separation region 116 is arranged between the drift region 112 and the gate electrode 134, is in contact with the drift region 112 and the gate electrode 134, and separates the drift region 112 from the gate electrode 134. In this way, the n ^- type drift region 112, the p ⁺ type gate separation region 116, and the n ^- type gate electrode 134 are continuously arranged. As a result, the drift region 112 and the gate separation region 116 form one pn diode, the gate separation region 116 and the gate electrode 134 form one pn diode, and these pn diodes are arranged in opposite directions. ing. Further, the gate separation region 116 is electrically connected to the source electrode 124. The gate separation region 116 extends from the insulated gate portion 130, for example, in the depth direction of the paper surface, and can make ohmic contact with the source electrode 124 at that portion. The gate separation region 116 is formed as a semiconductor layer containing aluminum or boron that spreads over the surface layer of the semiconductor substrate 100 by using crystal growth technology or ion implantation technology, and then the drift region 112 is formed by using etching technology. It is formed so as to remain on a part of the surface of the.

Next, the operation of the semiconductor device 4 will be described. When a positive voltage is applied to the drain electrode 122, the source electrode 124 is grounded, and the gate electrode 134 of the insulated gate 130 is grounded, the semiconductor device 4 is turned off. At this time, in the semiconductor device 4, since the reverse bias is applied to the diode composed of the drift region 112 and the gate separation region 116, the depletion layer extends from the pn junction between the drift region 112 and the gate separation region 116. Therefore, the drain electrode 122 and the gate electrode 134 are insulated from each other, and the leakage current is suppressed from flowing between the drain electrode 122 and the gate electrode 134. Therefore, the semiconductor device 4 can perform a stable off operation. Further, the depletion layer extending from the pn junction between the drift region 112 and the gate separation region 116 relaxes the electric field at the drain side end of the insulated gate portion 130. In particular, in the semiconductor device 4, the gate insulating film 132 is not provided at the drain side end of the insulated gate portion 130. The drain side end of the insulated gate 130 is a place where electric field concentration is likely to occur. In the semiconductor device 4, since the gate insulating film 132 does not exist in the place where the electric field concentration is likely to occur, the dielectric breakdown of the gate insulating film 132 is suppressed. In this way, the semiconductor device 4 can have high reliability by suppressing dielectric breakdown of the gate insulating film 132 of the insulating gate portion 130. Further, in the semiconductor device 4, since the gate separation region 116 is electrically connected to the source electrode 124, the gate separation region 116 is fixed to the ground potential. As a result, when the semiconductor device 4 is off, the width of the depletion layer extending from the pn junction between the drift region 112 and the gate separation region 116 is large, so that the above-mentioned effects of suppressing the leak current and relaxing the electric field are great.

When a positive voltage is applied to the drain electrode 122, the source electrode 124 is grounded, and a voltage that is more positive than the source electrode 124 is applied to the gate electrode 134 of the insulated gate portion 130, the semiconductor device 4 is turned on. At this time, in the semiconductor device 4, since the reverse bias is applied to the pn diode composed of the gate separation region 116 and the gate electrode 134, the depletion layer extends from the pn junction between the gate separation region 116 and the gate electrode 134. Therefore, the drain electrode 122 and the gate electrode 134 are insulated from each other, and the leakage current is suppressed from flowing between the drain electrode 122 and the gate electrode 134. Therefore, the semiconductor device 4 can perform a stable on-operation.

As described above, the semiconductor device 4 can perform stable on and off operations, suppresses dielectric breakdown of the gate insulating film 132, and can have high reliability. Further, similarly to the semiconductor device 2 shown in FIG. 6, since the gate electrode 134 has the high density gate electrode 134a and the low density gate electrode 134b, the body region 113 located between the drift region 112 and the source region 115. A high-density inversion layer is formed over the entire range of the above, and low channel resistance is realized.

In the above, the techniques disclosed in the present specification have been described by taking MOSFET as an example. The technique disclosed in the present specification is applicable not only to MOSFETs but also to other semiconductor devices, and can be applied to, for example, IGBTs. In particular, the technique disclosed herein can reduce the forward voltage of the built-in diode when applied to a reverse conduction IGBT, similar to the above.

Although specific examples of the present invention have been described in detail above, these are merely examples and do not limit the scope of claims. The techniques described in the claims include various modifications and modifications of the specific examples illustrated above. In addition, the technical elements described in the present specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the techniques illustrated in the present specification or drawings can achieve a plurality of purposes at the same time, and achieving one of the purposes itself has technical usefulness.

1: Semiconductor device 10: Semiconductor substrate 11: Drain region 12: Drift region 13: Body region 14: Body contact region 15: Source region 16: Gate separation region 17; Connection region 22: Drain electrode 24: Source electrode 30: Insulated gate Part 30T: Trench 32: Gate insulating film 34: Gate electrode

Claims (6)

It has a first conductive type first semiconductor region, a second conductive type second semiconductor region, a first conductive type third semiconductor region, and a second conductive type gate separation region, and the first semiconductor region A semiconductor substrate in which the second semiconductor region and the third semiconductor region are arranged in this order along the first direction, and
The first main electrode in contact with the third semiconductor region and
A second main electrode that is separated from the first main electrode along the first direction,
Equipped with an insulated gate
The insulating gate portion is
A gate insulating film in contact with the first semiconductor region, the second semiconductor region, and the third semiconductor region.
It has at least a first conductive type gate electrode facing the portion of the second semiconductor region located between the first semiconductor region and the third semiconductor region via the gate insulating film.
The gate separation region has at least a portion arranged on the second main electrode side of the gate insulating film, is in contact with the first semiconductor region and the gate electrode, and is in contact with the gate electrode. A semiconductor device that separates the gate electrode from the above and is electrically connected to the first main electrode. The gate electrode has a high-concentration gate electrode having a relatively high impurity concentration and a low-concentration gate electrode having a relatively low impurity concentration.
The high-concentration gate electrode faces the entire range of the portion of the second semiconductor region located between the first semiconductor region and the third semiconductor region via the gate insulating film.
The semiconductor device according to claim 1, wherein the low-concentration gate electrode is provided between the gate separation region and the high-concentration gate electrode. The first direction is the thickness direction of the semiconductor substrate.
The first main electrode is provided on the surface of the semiconductor substrate, and the first main electrode is provided on the surface of the semiconductor substrate.
The second main electrode is provided on the back surface of the semiconductor substrate.
The insulating gate portion is provided in a trench that penetrates the third semiconductor region and the second semiconductor region from the surface of the semiconductor substrate and penetrates into the first semiconductor region.
The gate insulating film covers the side surface of the trench.
The gate electrode is exposed on the bottom surface of the trench.
The semiconductor device according to claim 1 or 2, wherein the gate separation region is in contact with the gate electrode exposed on the bottom surface of the trench. It extends along the thickness direction of the semiconductor substrate and further has a connection region in contact with the gate separation region.
The connection region is arranged outside the end portion of the insulating gate portion in the longitudinal direction when observed from a direction orthogonal to the surface of the semiconductor substrate.
The semiconductor device according to claim 3, wherein the gate separation region is electrically connected to the first main electrode via the connection region. The semiconductor device according to claim 4, wherein the connection region is a second conductive type semiconductor. The first semiconductor region is a drift region, the second semiconductor region is a body region, the third semiconductor region is a source region, the first main electrode is a source electrode, and the second main electrode is a drain electrode. The semiconductor device according to any one of claims 1 to 5.

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