JP7334638B2 - semiconductor equipment - Google Patents

Description

The technology disclosed in this specification relates to a semiconductor device.

The semiconductor device disclosed in Patent Document 1 has a source electrode, an interlayer insulating film, and a gate wiring. A source electrode is disposed on the semiconductor substrate and connected to the source of the transistor. The interlayer insulating film is arranged on the semiconductor substrate. The gate wiring is arranged on the interlayer insulating film and connected to the gate of the transistor. The semiconductor substrate has a p-type region in contact with the interlayer insulating film under the gate wiring. The p-type region is in contact with the source electrode. Therefore, the p-type region has approximately the same potential as the source electrode. By arranging the p-type region having substantially the same potential as the source electrode under the gate wiring, the voltage applied to the interlayer insulating film under the gate wiring can be reduced, and deterioration of the interlayer insulating film can be suppressed.

JP 2013-239554 A

In the semiconductor device of Patent Document 1, current may flow into the p-type region below the gate wiring. The current flowing into the p-type region flows to the source electrode. Then, the potential of the p-type region under the gate wiring rises. Therefore, a high voltage is applied to the gate wiring, and the deterioration of the interlayer insulating film progresses. This specification proposes a technique for more preferably suppressing deterioration of an interlayer insulating film.

A semiconductor device disclosed in this specification includes a semiconductor substrate having a transistor, a source electrode arranged on the semiconductor substrate and connected to the source of the transistor, and an interlayer electrode arranged on the semiconductor substrate. It has an insulating film and a gate wiring arranged on the interlayer insulating film and connected to the gate of the transistor. The semiconductor substrate has a first p-type region, an n-type region and a second p-type region. The first p-type region is in contact with the interlayer insulating film under the gate wiring. The n-type region is in contact with the first p-type region. The second p-type region contacts the n-type region, is separated from the first p-type region by the n-type region, and contacts the source electrode.

In this semiconductor device, an n-type region and a second p-type region are arranged around the first p-type region under the gate wiring. When no current flows through the second p-type region, the n-type region and the first p-type region have approximately the same potential as the second p-type region (that is, approximately the same potential as the source electrode). Therefore, no high voltage is applied to the interlayer insulating film. Also, current may flow into the second p-type region. The current flowing into the second p-type region flows to the source electrode. Also, part of the current flowing into the second p-type region flows to the source electrode via the n-type region. Therefore, when a current flows through the second p-type region, the potentials of the second p-type region and the n-type region below the gate wiring rise. However, even in this case, current does not flow from the n-type region to the first p-type region, so the potential of the first p-type region does not change much. That is, even when a current flows into the second p-type region, the potential of the first p-type region in contact with the interlayer insulating film below the gate wiring does not change much, and a high voltage is not applied to the interlayer insulating film. Thus, in this semiconductor device, application of a high voltage to the interlayer insulating film can be suppressed, and deterioration of the interlayer insulating film can be suppressed.

FIG. 2 is a cross-sectional view of the semiconductor device of Example 1; Sectional drawing of the semiconductor device of a comparative example. FIG. 4 is an explanatory diagram of a semiconductor device of Modification 1, which is a modification of Embodiment 1; FIG. 4 is an explanatory diagram of a semiconductor device of Modification 2, which is a modification of Embodiment 1; FIG. 2 is a cross-sectional view of a semiconductor device according to a second embodiment;

A semiconductor device 10 of Example 1 shown in FIG. 1 has a semiconductor substrate 12 . The semiconductor substrate 12 is made of silicon carbide (SiC). A source electrode 14 is provided on the upper surface of the semiconductor substrate 12 . A drain electrode 16 is provided on the lower surface of the semiconductor substrate 12 .

A trench 18 is provided in the upper surface of the semiconductor substrate 12 below the source electrode 14 . Although one trench 18 is shown in FIG. 1 , a plurality of trenches 18 are provided in the upper surface of the semiconductor substrate 12 . A gate insulating film 20 and a gate electrode 22 are arranged in each trench 18 . Gate electrode 22 is insulated from semiconductor substrate 12 by gate insulating film 20 . An upper surface of each gate electrode 22 is covered with an interlayer insulating film 24 . The interlayer insulating film 24 is made of silicon oxide. Each gate electrode 22 is insulated from the source electrode 14 by an interlayer insulating film 24 .

A source region 30 , a body region 32 , a drift region 36 and a drain region 38 are provided in the semiconductor substrate 12 under the source electrode 14 . The source region 30 is a high-concentration n-type region and is in ohmic contact with the source electrode 14 . Source region 30 is in contact with gate insulating film 20 . The body region 32 has a contact region 32a and a low concentration region 32b. The contact region 32 a is a high-concentration p-type region and is in ohmic contact with the source electrode 14 . The low concentration region 32b is a p-type region having a p-type impurity concentration lower than that of the contact region 32a. The low concentration region 32b is in contact with the source region 30 and the contact region 32a. The low concentration region 32 b is in contact with the gate insulating film 20 below the source region 30 . The drift region 36 is a low concentration n-type region. The drift region 36 is arranged below the low concentration region 32b. The drift region 36 is in contact with the gate insulating film 20 below the low concentration region 32b. The drain region 38 is a highly doped n-type region. Drain region 38 is located below drift region 36 . Drain region 38 is in ohmic contact with drain electrode 16 . An FET is configured by the source region 30, the body region 32, the drift region 36, the drain region 38, the gate electrode 22, and the like.

An interlayer insulating film 40 and a gate wiring 42 are provided on a region of the semiconductor substrate 12 not covered with the source electrode 14 . The interlayer insulating film 40 is made of silicon oxide. The interlayer insulating film 40 is arranged on the upper surface of the semiconductor substrate 12 . The gate wiring 42 is made of polysilicon. The gate wiring 42 is arranged on the interlayer insulating film 40 . The gate wiring 42 is insulated from the semiconductor substrate 12 by the interlayer insulating film 40 . The gate wiring 42 is connected to each gate electrode 22 at a position not shown. Also, the gate wiring 42 is connected to a gate pad (not shown). The potential of each gate electrode 22 is controlled via the gate pad and gate wiring 42 . The gate wiring 42 is covered with the interlayer insulating film 24 .

A first p-type region 51 , an n-type region 54 and a second p-type region 52 are arranged in the semiconductor substrate 12 under the gate wiring 42 . The first p-type region 51 is in contact with the interlayer insulating film 40 below the gate wiring 42 . N-type region 54 is arranged around first p-type region 51 and is in contact with first p-type region 51 . The second p-type region 52 is a region continuous with the body region 32 . The second p-type region 52 is arranged around the n-type region 54 and is in contact with the n-type region 54 . The second p-type region 52 is separated from the first p-type region 51 by an n-type region 54 . The second p-type region 52 has a contact region 52a and a low concentration region 52b. The contact region 52a has a p-type impurity concentration higher than that of the low concentration region 52b. Contact region 52 a is in ohmic contact with source electrode 14 . The low concentration region 52b is in contact with the n-type region 54 and the contact region 52a. The drift region 36 is in contact with the low concentration region 52b from below.

The p-type impurity concentration of the first p-type region 51 is higher than the n-type impurity concentration of the n-type region 54 . The n-type impurity concentration of the n-type region 54 is higher than the p-type impurity concentration of the low concentration region 52b. In one example, the p-type impurity concentration of the first p-type region 51 is 1×10 ¹⁹ to 1×10 ²⁰ /cm ³ and the n-type impurity concentration of the n-type region 54 is 1×10 ¹⁹ to 1×10 ²⁰ /cm ³ . , the p-type impurity concentration of the low concentration region 52b can be set to 1×10 ¹⁶ to 1×10 ¹⁷ /cm ³ .

The first p-type region 51, the n-type region 54, and the second p-type region 52 can be formed by ion implantation. In this case, the first p-type region 51, the contact region 52a, and the contact region 32a can be formed by a common ion implantation process. Also, the n-type region 54 and the source region 30 can be formed by a common ion implantation process. Also, the low concentration region 52b and the low concentration region 32b can be formed by a common ion implantation process.

Current flows from the drift region 36 into the second p-type region 52 when the FET is turned off. Otherwise, no current flows through the second p-type region 52 under the gate wiring 42 . The potential of the second p-type region 52 is substantially equal to the potential of the source electrode 14 when no current flows through the second p-type region 52 . Therefore, the potentials of the n-type region 54 and the first p-type region 51 are also substantially equal to the potential of the source electrode 14 . The potential of the gate wiring 42 is controlled by a gate pad (not shown). The potential of the gate wiring 42 fluctuates in a range close to the potential of the source electrode 14 (for example, in the range of 0 to 10 V). Therefore, when no current flows through the second p-type region 52 , a large potential difference does not occur between the gate wiring 42 and the first p-type region 51 , and a high voltage is not applied to the interlayer insulating film 40 .

When the FET is turned off, holes (that is, current) flow from drift region 36 into body region 32 and second p-type region 52 as indicated by dashed arrow 100 . The current flowing into the second p-type region 52 flows through the second p-type region 52 and is discharged to the source electrode 14 as indicated by arrow 102 . Since the current flows in the second p-type region 52 in this way, the potential of the second p-type region 52 rises below the gate line 42 (that is, at the position A). When the potential of the second p-type region 52 rises at position A, a forward voltage is applied to the pn junction 56 at the interface between the second p-type region 52 and the n-type region 54 . This turns on pn junction 56 and allows current to flow into n-type region 54 as indicated by arrow 104 . The current flowing into n-type region 54 is discharged to source electrode 14 as indicated by arrow 104 . Since the current flows in the n-type region 54 in this way, the potential of the n-type region 54 rises below the gate wiring 42 (that is, at the position B). When the potential of n-type region 54 rises at position B, a voltage is applied in the opposite direction to pn junction 58 at the interface between n-type region 54 and first p-type region 51 . Therefore, the pn junction 58 is not turned on, and no current flows into the first p-type region 51 . Therefore, the potential of the first p-type region 51 becomes floating. Therefore, even if the potential of n-type region 54 rises at position B, the potential of first p-type region 51 does not rise much. Therefore, no high voltage is applied to the interlayer insulating film 40 .

As described above, in the semiconductor device 10 of the first embodiment, the inter-layer insulating film 40 has a high voltage in both the state where the current flows through the second p-type region 52 and the state where the current does not flow through the second p-type region 52 . No voltage applied. Therefore, deterioration of the interlayer insulating film 40 can be suppressed.

Also, since the gate wiring 42 and the second p-type region 52 face each other with the interlayer insulating film 40 interposed therebetween, a capacitor is formed in this portion. As shown in FIG. 2, when the second p-type region 52 is in contact with the interlayer insulating film 40 at a position directly below the gate wiring 42, the capacitance between the gate wiring 42 and the second p-type region 52 is extremely large. On the other hand, if there is a first p-type region 51 whose potential is floating between the gate wiring 42 and the second p-type region 52 as shown in FIG. The capacitance is the combined capacitance of the capacitance between the gate wiring 42 and the first p-type region 51 and the capacitance between the first p-type region 51 and the second p-type region 52 (the combined capacitance of the capacitors connected in series). ). Therefore, in FIG. 1, the capacitance between the gate wiring 42 and the second p-type region 52 is small. By providing the first p-type region 51 in this manner, the capacitance between the gate wiring 42 and the second p-type region 52 is reduced, thereby reducing the gate-source capacitance of the FET. .

Note that the n-type region 54 may be in ohmic contact with the source electrode 14 as shown in FIG. With this configuration, the potential of n-type region 54 is more stable, so that the voltage applied to interlayer insulating film 40 can be more effectively suppressed.

Alternatively, as shown in FIG. 4, two source electrodes 14 may be arranged on the semiconductor substrate 12, and the second p-type region 52 may be brought into contact with the source electrodes 14 at a first contact portion 52x and a second contact portion 52y. . In this case, the gate wiring 42 may be arranged between the first contact portion 52x and the second contact portion 52y. According to this configuration, when a current flows through the second p-type region 52, the current is discharged to the source electrode 14 from each of the first contact portion 52x and the second contact portion 52y. Therefore, the electric resistance of the current path in the second p-type region 52 is reduced, and the potential of the second p-type region 52 is less likely to rise at the position below the gate line 42 . Thereby, the voltage applied to the interlayer insulating film 40 can be suppressed more effectively.

In the semiconductor device 200 of Example 2 shown in FIG. 5, the drift region 36 has a high concentration region 36a and a low concentration region 36b. The high-concentration region 36 a is arranged at a depth that includes the lower end of the trench 18 . The low concentration region 36b is arranged below the high concentration region 36a. Semiconductor substrate 12 also includes a bottom p-type region 202 located within drift region 36 below trench 18 . The semiconductor substrate 12 also has a connecting p-type region 204 extending from the top surface of the semiconductor substrate 12 to a position reaching the bottom p-type region 202 . The upper end of the connection p-type region 204 is in ohmic contact with the source electrode 14 .

Further, in the semiconductor device 200 of Example 2, the low-concentration region 52 b of the second p-type region 52 is arranged at the same depth as the bottom p-type region 202 . Also, the contact region 52 a of the second p-type region 52 is arranged at the same depth as the connection p-type region 204 . Also, the n-type region 54 is arranged at the same depth as the high-concentration region 36 a of the drift region 36 . Also, the first p-type region 51 is arranged at the same depth as the low-concentration region 32 b of the body region 32 .

Except for the above, the configuration of the semiconductor device 200 of the second embodiment is the same as the configuration of the semiconductor device 10 of the first embodiment.

When the bottom p-type region 202 and the connection p-type region 204 are provided as in the second embodiment, the withstand voltage of the FET can be improved. Also in the second embodiment, as in the first embodiment, the first p-type region 51, the n-type region 54, and the second p-type region 52 are provided under the gate wiring 42. voltage applied to the interlayer insulating film 40 can be reduced.

In Example 2, the bottom p-type region 202 and the second p-type region 52 and the low-concentration region 52b are formed at the same time by ion-implanting p-type impurities into the semiconductor substrate formed by the low-concentration region 36b of the drift region 36. can be formed. Further, the high-concentration region 36a of the drift region 36 and the n-type region 54 can be simultaneously formed by epitaxial growth on the semiconductor substrate. Moreover, the low-concentration region 32b of the body region 32 and the first p-type region 51 can be simultaneously formed thereon by epitaxial growth. Thereafter, by ion implantation, connecting p-type region 204 and contact region 52a can be formed simultaneously, thereby isolating n-type region 54 from heavily doped region 36a of drift region 36. FIG.

Further, in Example 2, the p-type impurity concentration of the first p-type region 51 is higher than the p-type impurity concentration of the low concentration region 52b, and the p-type impurity concentration of the low concentration region 52b is equal to the n-type impurity concentration of the n-type region 54. higher than In one example, the p-type impurity concentration of the first p-type region 51 is 1×10 ¹⁷ to 1×10 ²⁰ /cm ³ and the p-type impurity concentration of the low concentration region 52b is 1×10 ¹⁷ to 1×10 ¹⁸ /cm ^{3 .} , the n-type impurity concentration of the n-type region 54 can be set to 1×10 ¹⁵ to 1×10 ¹⁷ /cm ³ . Also, the p-type impurity concentration of the contact region 52a and the connection p-type region 204 can be set to 1×10 ¹⁸ to 1×10 ²⁰ /cm ³ .

Also, in the second embodiment, the n-type region 54 may be brought into ohmic contact with the source electrode 14 . In the second embodiment, the source electrodes 14 may be provided on both sides of the gate wiring 42 and the second p-type region 52 may be in ohmic contact with the source electrodes 14 .

In addition, in Examples 1 and 2 described above, the semiconductor substrate 12 is made of silicon carbide. However, semiconductor substrate 12 may be made of other materials such as silicon and gallium nitride. However, when the semiconductor substrate 12 is composed of a compound semiconductor such as silicon carbide or gallium nitride, it is difficult to form a low-resistance p-type region inside the semiconductor substrate 12. The potential in the area is likely to rise. Therefore, by applying the technology disclosed in this specification to a compound semiconductor substrate, higher effects can be obtained.

The technical elements disclosed in this specification are listed below. Each of the following technical elements is independently useful.

In one example of the semiconductor device disclosed in this specification, the n-type region under the gate wiring may be in contact with the source electrode.

With this configuration, the potential of the n-type region is more stable, and as a result, the potential of the first p-type region is more stable.

In one example of the semiconductor device disclosed in this specification, the second p-type region may be in contact with the source electrode at a first contact portion and a second contact portion. The gate wiring may be arranged between the first contact portion and the second contact portion.

With this configuration, the potential of the second p-type region is more stable, and as a result, the potential of the first p-type region is more stable.

Although the embodiments have been described in detail above, they are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. The technical elements described in this specification or in the drawings exhibit technical usefulness either singly or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the techniques exemplified in this specification or drawings simultaneously achieve a plurality of purposes, and achieving one of them has technical utility in itself.

10: semiconductor device 12: semiconductor substrate 14: source electrode 16: drain electrode 18: trench 20: gate insulating film 22: gate electrode 24: interlayer insulating film 30: source region 32: body region 32a: contact region 32b: low concentration region 36: drift region 36a: high-concentration region 36b: low-concentration region 38: drain region 40: interlayer insulating film 42: gate wiring 51: first p-type region 52: second p-type region 52a: contact region 52b: low-concentration region 52x: First contact portion 52y : Second contact portion 54 : N-type region 56 : pn junction 58 : pn junction 100 : Arrow 102 : Arrow 200 : Semiconductor device 202 : Bottom p-type region 204 : Connection p-type region

Claims (3)

A semiconductor device,
a semiconductor substrate having transistors;
a source electrode disposed on the semiconductor substrate and connected to the source of the transistor;
an interlayer insulating film disposed on the semiconductor substrate;
a gate wiring disposed on the interlayer insulating film and connected to the gate of the transistor;
has
The semiconductor substrate is
a first p-type region in contact with the interlayer insulating film under the gate wiring;
an n-type region in contact with the first p-type region;
a second p-type region in contact with the n-type region and separated from the first p-type region by the n-type region and in contact with the source electrode;
A semiconductor device having 2. The semiconductor device according to claim 1, wherein said n-type region is in contact with said source electrode. the second p-type region is in contact with the source electrode at a first contact portion and a second contact portion;
The gate wiring is arranged between the first contact portion and the second contact portion,
3. The semiconductor device according to claim 1 or 2.

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