JPH11214685A - Insulated gate semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an insulated gate semiconductor device, capable of reducing on-resistance and increase the switching speed and, especially in a depletion mode, can be manufactured inexpensively through a simple manufacturing process. SOLUTION: An insulation gate type semiconductor device is provided with a base region 1, that is formed on a semiconductor substrate A in a plate shape having both surfaces consisting of surfaces A1 and A2 and a gate electrode 2, that is covered with a gate insulation film 21 for insulating from the base region 1, and at the same time is provided next to the base region 1 along the direction of the thickness of a semiconductor substrate A, forms a channel region 11 with a depleted layer and an inverted layer at the base region 1, when a gate voltage is applied in each gate electrode 2, and turns on or off a voltage which is applied to both the surfaces of the semiconductor substrate A. In the insulation gate type semiconductor device, each gate electrode 2 is arranged with a specified interval L, so that the depleted layer of the channel region 11 communicates with the depleted layer where the depleted layer of the channel region 11 is adjacent to each other.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an insulated gate semiconductor device having a MOS structure.

[0002]

2. Description of the Related Art Conventionally, as this kind of insulated gate type semiconductor device, there is one having a configuration shown in FIG. This is formed on a plate-shaped semiconductor substrate A having both surfaces consisting of one surface A1 and the other surface A2, and has a base region B of P-type conductivity.
And a plurality of gate electrodes C which are covered with a gate insulating film C1 insulated from the base region B and are juxtaposed in the base region B along the thickness direction of the semiconductor substrate A, and come into contact with the base region B. A source region D having an N-type conductivity provided on one surface A1 side of the semiconductor substrate A, and a drain region E having an N-type conductivity provided on the other surface A2 side of the semiconductor substrate A in contact with the base region B. A source electrode F in contact with both the base region B and the source region D; and a drain electrode G provided on the other surface A2 side of the semiconductor substrate A in contact with the drain region E. Each gate electrode C is buried in the drain region E, and when a gate voltage is applied, a channel region B1 having a depletion layer B11 and an inversion layer B12 is formed in the base region B along the interface of the gate insulating film C1. And turn on between the source electrode F and the drain electrode G,
Drain current flows.

More specifically, this is a so-called enhanced mode insulated gate semiconductor device in which a base region B and a drain region E form a PN junction and can be controlled from an off state to an on state. As compared with a bipolar transistor, the transistor does not have an offset voltage in the on state, and has an extremely large input resistance in the on state because the gate electrode C is insulated from the source electrode F and the drain electrode G, respectively. It has many features such as a short switching time from being applied to being turned on.

Here, a channel region B1 composed of a depletion layer B11 and an inversion layer B12 is necessary for controlling a drain current, and when a gate voltage is applied, the channel region B1 is depleted.
11 and an inversion layer B12 are formed in the base region B at the interface of the gate insulating film C1. In addition, the voltage drop at the time of ON greatly depends on the resistance in the channel region B1, and the switching speed until the gate voltage is applied and turned on depends on the formation speed of the depletion layer B11 and the inversion layer B12 in the channel region B1. Limited.

FIG. 10 shows a cross section of the base region B, and FIG. 1 shows a charge distribution of the channel region B1.
This will be described below with reference to FIG. As shown in FIG. 11, when the gate voltage V1 is applied, the gate electrode C induces a charge Qg1 and a depletion layer B11 is formed in the base region B. However, at this time, the inversion layer B12 is not formed. The width Xd of the depletion layer B11 is represented by the following equation. Here, e is the electron charge amount, and Na is the impurity concentration of the base region B.

Xd = Qg1 / eNa As shown in FIG. 12, when a gate voltage V2 higher than the gate voltage V1 is applied, the charge Qg2 is applied to the gate electrode C.
And a depletion layer B11 is formed in the base region B, and the inversion layer B12, whose conductivity type has been inverted to N-type, has a charge Qn.
1 is formed at the interface between the base region B and the gate insulating film C1. The conditions for forming the inversion layer B12 are represented by the following equations. Where εs is the dielectric constant, V
f is the built-in voltage when the concentration is Na, k is the Boltzmann constant, T is the absolute temperature, and ni is the intrinsic carrier concentration.

[0007]

(Equation 1)

As can be seen from the above equation, once the inversion layer B12 is formed here, the maximum depletion layer width Xdmax does not increase even if the electric charge exceeds Qg2, and the depletion layer B11 is separated from the adjacent depletion layer B11. It is formed with an interval and does not communicate with each other. The charge Qn1 of the inversion layer B12 increases with the increase of the charge Qg2 from the gate electrode C, and reduces the resistance in the channel region B1 when turned on.

[0009]

In the above-mentioned conventional insulated gate type semiconductor device, when a gate voltage is applied to the gate electrode C, a channel region B1 is formed in the base region B, and both surfaces A1 of the semiconductor substrate A are formed. , A2 can be turned on and off.

Here, the voltage drop at the time of ON depends on the resistance in the channel region B1, and the resistance of the channel region B1 depends on the charge Qn1 of the inversion layer B12. It is reduced by increasing the charge Qn1 of B12. However, when the thickness of the gate insulating film C1 is reduced, the insulating property between the gate electrode C and the base region B deteriorates.

Since the switching speed is determined by the formation speed of the depletion layer B11 and the inversion layer B12 in the channel region B1, the higher the hole concentration in the base region B, the higher the switching speed. However, when the hole concentration is reduced, the withstand voltage between the base region B and the drain region E forming a PN junction deteriorates. Therefore, in the conventional device, there is a limit in improving the characteristics of both the voltage drop and the switching speed at the time of ON.

There is a so-called depletion mode in which the base region B and the drain region E are formed of the same conductivity type and controlled from an on state to an off state.
In order to obtain this depletion mode, it is necessary to preliminarily perform shallow impurity diffusion so that the inversion layer B12 is formed at the interface between the base region B and the gate insulating film C1. However, this impurity diffusion complicates the manufacturing process and increases the cost.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to reduce on-resistance and increase switching speed. Particularly, in a depletion mode, it can be manufactured by a simple manufacturing process. An insulated gate semiconductor device is provided.

[0014]

According to a first aspect of the present invention, there is provided a semiconductor device comprising: a base region formed on a plate-shaped semiconductor substrate having one surface and two surfaces; A plurality of gate electrodes that are covered with a gate insulating film that insulates the region and are arranged in parallel with the base region along the thickness direction of the semiconductor substrate. In an insulated gate semiconductor device that forms a channel region having a depletion layer and an inversion layer along the interface of the gate insulating film and controls on / off of a current applied to both surfaces of the semiconductor substrate, each of the gate electrodes includes: The depletion layer of the channel region is arranged at a predetermined interval so as to communicate with the adjacent depletion layer.

According to a second aspect of the present invention, in the first aspect, the base region is of a first conductivity type, and each of the gate electrodes is in contact with the base region and the other side of the semiconductor substrate is provided. Buried in the drain region of the second conductivity type provided at the bottom.

According to a third aspect of the present invention, there is provided the semiconductor device according to the first aspect, wherein the drain region, which is formed to have a P-type conductivity type and has good electric conductivity, is in contact with the base region and is connected to the semiconductor substrate. It is configured to be provided on the surface side.

According to a fourth aspect of the present invention, in the first or second aspect, the source region having a conductivity type opposite to that of the base region is in contact with the base region and on one side of the semiconductor substrate. The configuration is provided for

According to a fifth aspect of the present invention, there is provided the semiconductor device according to the second aspect, wherein the drain layer which is formed to have a P-type conductivity and has good electric conductivity is provided on the other surface side of the semiconductor substrate. The configuration is provided in.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to FIGS. In the first embodiment, a so-called depression mode is used in which the insulated gate semiconductor device is controlled from an on state to an off state.

Reference numeral 1 denotes a base region, which is formed on a semiconductor substrate A having an N-type conductivity, a plate-like shape having both surfaces, one surface A1 and the other surface A2, and an N-type conductivity.

Reference numeral 2 denotes a gate electrode, which is covered with a gate insulating film 21 that insulates the base region 1, and a plurality of gate electrodes are formed in grooves provided in the base region 1. Along the base region 1.
When a gate voltage is applied to each gate electrode 2,
Channel region 11 having depletion layer 11a and inversion layer 11b is formed in base region 1 between gate electrodes 2 along the interface of gate insulating film 21.

Here, as shown in FIG. 4, each gate electrode 2 has a depletion layer 11a in a channel region 11 communicating with an adjacent depletion layer 11a, that is, a base region 1 between gate electrodes 2 has a channel region. 11 are arranged in the base region 1 at a predetermined interval L so as to be closed. This will be described later in detail.

Reference numeral 3 denotes a source region whose conductivity type is a base region 1
And is provided on the one surface A1 side of the semiconductor substrate A in contact with the base region 1 to supply a charge for forming a channel region 11 for depleting or inverting the base region 1. . Reference numeral 4 denotes a source electrode which is in contact with both the base region 1 and the source region 3 to short-circuit each of them.

A drain region 5 is provided on the other surface A2 side of the semiconductor substrate A in contact with the base region 1 and has the same N-type conductivity as the base region 1, and operates in a depletion mode. A drain electrode 6 is provided on the other surface A2 side of the semiconductor substrate A in contact with the drain region 5.

The operation will be described below with reference to FIG. 3 showing a cross section of the base region 1 and FIG. 4 showing a charge distribution of the channel region 11.

As shown in FIG. 4, when gate voltage V1 is applied to gate electrode 2, depletion layer 11a is formed in base region 1 between gate electrodes 2 by charge Qg1 from gate electrode 2. Here, since gate electrodes 2 are arranged in base region 1 at a predetermined interval L, depletion layer 11a of channel region 11 communicates with depletion layer 11a formed by adjacent gate electrode 2, that is, depletion layer 11a
Communicates with the adjacent depletion layer 11a, and as a result,
The base region 1 between each gate electrode 2 is a channel region 11
Blocked by. At this time, the width Xd of the depletion layer 11a
Is the same as the conventional equation, that is, Xd = Qg
1 / eNa.

FIG. 5 shows the relationship between the concentration Na of the base region 1 on the horizontal axis and the maximum depletion layer width Xdmax formed by the gate voltage on the vertical axis. This relationship can be derived by using the mathematical formulas used in the conventional technique, but the effects of the interface state between the gate insulating film 21 and the base region 1 and the work function with the gate electrode 2 are omitted.

From FIG. 5, the maximum depletion layer width Xdmax becomes larger as the concentration Na of the base region 1 becomes thinner. For example, when the concentration Na is 1.0E15, it is about 1 μm (micrometer). Therefore, if the predetermined interval L between the respective gate electrodes 2 is 2 μm or less, the base region 1 between the respective gate electrodes 2 will be closed by the depletion layer 11a.

At this time, since the depletion layer 11a is formed over the base region 1 between the gate electrodes 2, it cannot be extended any further. Formed. In other words, the inversion layer 11b is formed earlier because the formation time of the depletion layer 11a capable of forming the inversion layer 11b is short, that is, the formation speed is higher than in the conventional case, and the conductivity type is reversed more quickly. This means that the current applied between the source electrode 4 and the drain electrode 6, that is, between the two surfaces A1 and A2 of the semiconductor substrate A changes from the on state to the off state, and the switching speed increases.

As described above, unlike the conventional case in which it is necessary to perform shallow impurity diffusion at the interface between the base region 1 and the gate insulating film 21 in order to obtain the depletion mode, the semiconductor is not provided without the impurity diffusion step. The current applied between both surfaces A1 and A2 of the substrate A is controlled to be in an off state.

In the insulated gate semiconductor device of the first embodiment, as described above, the gate electrodes 2 are arranged at predetermined intervals, and when a gate voltage is applied, the gate electrodes 2 Since the depletion layer 11a of the channel region 11 formed in the base region 1 communicates with the adjacent depletion layer 11a, the depletion layer 11a is smaller than in the related art in which each gate electrode 2 is arranged at a predetermined interval. Since the inversion layer 11b is formed when they are communicated with each other, the switching speed for controlling the on / off of the current applied to both sides of the semiconductor substrate A can be increased, and the manufacturing process can be simplified and the cost can be reduced as compared with the related art. Can be.

Since the P-type source region 3 having a conductivity type opposite to that of the base region 1 is provided on the one surface A1 side of the semiconductor substrate A in contact with the base region 1, the source region 3
Supplies a charge for forming a channel region 11 for depleting or inverting the base region 1, thereby forming the inversion layer 11b faster and further increasing the switching speed.

In the first embodiment, the drain region 5
Is formed to be the same N type as that of the base region 1, but the conductivity type of the drain region 5 may be formed to be P type to form a conductivity modulation type insulated gate type having good conductivity. Not limited.

In the first embodiment, the source electrode 4 is connected to one surface A1 of the semiconductor substrate A, and the drain electrode 6 is connected to the other surface A2.
The vertical structure is arranged on each side, but the source electrode 4
In addition, a horizontal structure in which both the drain electrode 6 and the drain electrode 6 are arranged on the one surface A1 side of the semiconductor substrate A may be adopted, and the invention is not limited thereto.

A second embodiment of the present invention will be described below with reference to FIGS. In the second embodiment, functions different from those in the first embodiment will be described, and members having substantially the same functions as those in the first embodiment will be denoted by the same reference numerals and description thereof will be omitted. In the second embodiment, a so-called enhanced mode is used in which the insulated gate semiconductor device is controlled from an off state to an on state.

The base region 1 is formed of a P type having a first conductivity type.
It is formed from a semiconductor substrate A having an N-type conductivity type. The source region 3 has an N-type conductivity type opposite to that of the base region 1 and contacts the base region 1 to form the semiconductor substrate A.
Is provided on one surface A1 side.

The drain region 5 has a conductivity type of the base region 1.
On the contrary, the first drain layer 51 is formed to be the second conductivity type N-type, has a low electron concentration, and has a second electron layer 52 having a high electron concentration. And the second drain layer 52 is
Are provided on the other surface A2 side of the semiconductor substrate A. Then, a PN junction is formed with the base region 1 to operate in the enhanced mode. Here, each gate electrode 2 is embedded in the first drain layer 51 of the drain region 5. A drain electrode 6 is provided on the other surface A2 side of the semiconductor substrate A in contact with the second drain layer 52.

The operation will be described below with reference to FIG. 3 showing a cross section of the base region 1 and FIGS. 4 and 8 showing a charge distribution of the channel region 11.

As shown in FIG. 4, when a gate voltage V1 is applied to the gate electrode 2, the depletion layer 11a is charged by the charge Qg1 from the gate electrode 2 in the same manner as in the first embodiment. It is formed in the base region 1 between them.
Here, since gate electrode 2 is arranged in base region 1 at a predetermined interval L, depletion layer 11a is adjacent to depletion layer 11a.
a and the base region 1 between the gate electrodes 2
Are closed by the channel region 11.

At this time, since the depletion layer 11a is formed over the base region 1 between the gate electrodes 2, the depletion layer 11a cannot be extended any more, and is formed even if the inversion layer 11b inverted to N-type has the charge Qg1. . That is, the inversion layer 11b
Is formed earlier because the formation time of the depletion layer 11a capable of forming the inversion layer 11b is short, that is, the formation speed is faster than in the conventional case, and the conductivity type is reversed more quickly. This means that the current applied between the two surfaces A1 and A2 of the semiconductor substrate A changes from the OFF state to the ON state, and the switching speed increases.

As shown in FIG. 8, the gate voltage V1
When a higher gate voltage V2 is applied to the gate electrode 2, a charge Qg2 is induced to cause a charge (Q
n) becomes Qn2. As can be seen from a comparison between FIG. 8 and the conventional FIG. 12, when the same charge Qg2 is given from the gate electrode 2 to the charge of the inversion layer 11b, the depletion layer 11a of the channel region 11 communicates. , Ie, the charge density of the inversion layer 11b increases. This means that the on-resistance of the channel region 11 is reduced when turned on.

As described above, unlike the prior art in which the hole concentration of the base region 1 is reduced in order to increase the switching speed, it is not necessary to reduce the concentration of the base region 1. 5 does not deteriorate. Also, in order to reduce the on-resistance,
Unlike the conventional case where it is necessary to reduce the thickness of the gate insulating film 21, the insulation between the gate electrode 2 and the base region 1 does not deteriorate.

In the insulated gate semiconductor device of the second embodiment, as described above, the base region 1 is the first region.
A P-type, N-type, second conductivity type drain region 5 is provided on the other surface A2 side of the semiconductor substrate A in contact with the base region 1, and each gate electrode 2 is embedded in the drain region 5. As a result, the base region 1 and the drain region 5
A junction can be formed to control the off state to the on state.
A so-called enhanced mode can be realized. Further, in the enhanced mode, the switching speed for controlling the on / off of the current applied to both sides of the semiconductor substrate A can be increased without deteriorating the breakdown voltage between the base region 1 and the drain region 5, and the high-density charge can be obtained. Inversion layer 1 having
By forming 1b, the on-resistance can be reduced and the voltage drop in the channel region 11 can be reduced without deteriorating the insulation between the gate electrode 2 and the base region 1.

In the second embodiment, the first conductivity type is P
Although the second conductivity type is formed as N-type, the first conductivity type is formed as N-type.
The second conductive type may be formed as a P-type and is not limited.

In the second embodiment, the base region 1 is formed of the first conductivity type, the drain region 5 is formed of the second conductivity type, and a PN junction is formed between the base region 1 and the drain region 5. Although the enhanced mode is used, the depletion mode may be used by forming the base region 1 and the drain region 5 to have the same conductivity type, and there is no limitation.

In the second embodiment, the drain region 5
The second drain layer 52 is formed to have an N-type with a high electron concentration. However, the conductivity type of the second drain layer 52 is formed to be a P-type, and a conductivity-modulated insulated gate type having good conductivity is formed. It may be configured and is not limited.

[0047]

According to the first aspect of the present invention, when each gate electrode is arranged at a predetermined interval and a gate voltage is applied, a depletion layer of a channel region formed in a base region between each gate electrode is formed. Since the depletion layer communicates with the adjacent depletion layer, an inversion layer is formed when the depletion layer communicates with the depletion layer. In the case of the depletion mode, the manufacturing process can be simplified and the cost can be reduced.

According to the second aspect, in addition to the effect of the first aspect, if the base region is of the first conductivity type,
Since the drain region of the second conductivity type is provided on the other surface side of the semiconductor substrate in contact with the base region and each gate electrode is embedded in the drain region, the base region and the drain region form a PN junction. As a result, a so-called enhanced mode that can be controlled from the off state to the on state can be realized, and in the enhanced mode, the switching speed can be increased without deteriorating the breakdown voltage between the base region and the drain region, and the high-density charge can be achieved. Is formed, the on-resistance can be reduced and the voltage drop in the channel region can be reduced without deteriorating the insulating property between the gate electrode and the base region.

According to a third aspect of the present invention, in addition to the effect of the first aspect, a drain region having a P-type conductivity is provided on the other surface of the semiconductor substrate in contact with the base region. In addition, the electrical conductivity of the drain region is improved, and the on-resistance can be further reduced.

According to a fourth aspect of the present invention, in addition to the effects of the first or second aspect, the source region having the opposite conductivity type to the base region is brought into contact with the base region to form one side of the semiconductor substrate. Thus, the source region supplies charges for forming the channel region to the base region, the inversion layer can be formed quickly, and the switching speed can be further increased.

According to a fifth aspect of the present invention, in addition to the effect of the second aspect, the drain layer having the P-type conductivity is provided in the drain region on the other surface of the semiconductor substrate. And the on-resistance can be further reduced.

[Brief description of the drawings]

FIG. 1 is a front sectional view (XX section in FIG. 2) showing a first embodiment of the present invention.

FIG. 2 is a plan view of the same.

FIG. 3 is a cross-sectional view of a base region (channel region) between the same gate electrodes.

FIG. 4 is a charge distribution diagram in a base region (channel region) when a gate voltage is V1 and an inversion layer is formed by communication of a depletion layer.

FIG. 5 is a correlation diagram showing a relationship between a concentration of a base layer and a maximum depletion layer width.

FIG. 6 is a front sectional view (YY sectional view in FIG. 8) showing a second embodiment of the present invention.

FIG. 7 is a plan view of the same.

FIG. 8 is a charge distribution diagram in a base region (channel region) when the gate voltage is V2 and an inversion layer is formed.

FIG. 9 is a front sectional view showing a conventional example.

FIG. 10 is a cross-sectional view of a base region (channel region) between the same gate electrodes.

FIG. 11 is a charge distribution diagram in a base region (channel region) when a gate voltage is V1 and a depletion layer is formed.

FIG. 12 is a charge distribution diagram in a base region (channel region) when the gate voltage is V2 and an inversion layer is formed.

[Explanation of symbols]

 A1 One surface A2 Other surface A Semiconductor substrate 1 Base region 11 Channel region 11a Depletion layer 11b Inversion layer 2 Gate electrode L Predetermined interval 21 Gate insulating film 3 Source region 5 Drain region 52 Second drain layer (drain layer)

Claims (5)

[Claims] 1. A base region formed on a plate-shaped semiconductor substrate having both surfaces including one surface and another surface, and a gate insulating film that insulates the base region from the base region, and extends in a thickness direction of the semiconductor substrate. A plurality of gate electrodes arranged side by side in the base region, and each gate electrode forms a channel region having a depletion layer and an inversion layer along the interface of the gate insulating film in the base region when a gate voltage is applied. In the insulated gate semiconductor device that controls on / off of a current applied to both surfaces of the semiconductor substrate, the gate electrodes are arranged at predetermined intervals so that a depletion layer of the channel region can communicate with the adjacent depletion layer. An insulated gate semiconductor device, which is disposed. 2. The base region is of a first conductivity type,
2. The insulated gate semiconductor device according to claim 1, wherein each of said gate electrodes is buried in a second conductivity type drain region provided on the other surface side of said semiconductor substrate in contact with said base region. 3. The semiconductor device according to claim 1, wherein a drain region having a P-type conductivity and good electric conductivity is provided on the other surface of said semiconductor substrate in contact with said base region. An insulated gate semiconductor device as described in the above. 4. The semiconductor device according to claim 1, wherein the source region having a conductivity type opposite to that of the base region is provided on one surface side of the semiconductor substrate in contact with the base region. Insulated gate semiconductor device. 5. The semiconductor device according to claim 2, wherein a drain layer having a P-type conductivity and good electric conductivity is provided in the drain region on the other surface of the semiconductor substrate. Insulated gate semiconductor device.