JPS594077A - Field-effect transistor - Google Patents

Abstract

PURPOSE:To reduce a voltage fall loss in a collector, by providing the drain region of FET with a region of conductivity type reverse to that of the drain region, and by short-circuiting the two regions by a drain electrode. CONSTITUTION:A P<+> type region 6 opposite to a P type source 4 is formed on the main surface of an N type drain region 2', and the two regions are short- circuited by a drain electrode. The p-n junction 7 between the layers 6 and 2' is at the same potential on the main surface due to the short circuit by the drain electrode, while it is at a high potential in a deep part near the source 4 and thus a hole is injected from the P<+> region. This hole causes carrier modulation, and thereby the resistance of the drain regions is lowered and the fall of the voltage is reduced. This effect is increased as current switching becomes large. Although a switching time tends to be delayed by a time required for the extinction of the hole, the demand can be met sufficiently in conjunction with a remarkable effect of the reduction of a voltage fall loss.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to field effect transistors, and particularly aims to improve electrical characteristics by improving the structure of the drain region of field effect transistors.

Field effect transistors (hereinafter abbreviated as FETs) have an extremely contradictory relationship between breakdown voltage and ON resistance, and the question is how to reduce the specific resistance and thickness of the drain high resistance layer, which is the most dominant factor in ON resistance, to obtain a high breakdown voltage. This is the key point in the design, and it is necessary to optimize the pressure-resistant design.

Furthermore, although the switching speed of MOS FETs is very fast and switching losses can be significantly reduced, MOS FETs have the drawback of higher saturation voltage and increased power loss than bipolar transistors. In order to reduce the above-mentioned saturation voltage, it is easy to increase the chip area, but this increases the size and does not correspond to the current situation. The ON resistance in the non-saturation region is expressed by the following equation for No5F'ET, which is schematically shown in cross section in FIG.

RoN= Ls + Rch + Rac + RD+
Rsub (where R8 is the source resistance, Rch is the channel resistance, Rac is the storage resistance, RD is the drain resistance, R
(sub indicates the substrate resistance, respectively) In the above equation, the power MO for the switching regulator
Regarding 8PET, there is a problem in that the drain resistance (RD) is the dominant component, and the power consumption due to the 'w1 pressure drop mainly in the high resistance region (N layer) has a large influence.

The present invention has been made to improve the drawbacks of the conventional structure of the slanted FET, and provides a structure that reduces the voltage drop loss at the collector.

The field effect transistor according to the present invention is characterized in that a region of a conductivity type opposite to that of the drain region short-circuited by the drain electrode is formed.

A cross section of an example of a MOS FET is shown in Figure 2, from the source electrode (S) to the source region (1) and drain region (2).
) The distribution of the current that reaches the drain electrode (D) is shown by a broken line. Note that (G) is a gate electrode, (3) is a silicon oxide layer (electrical insulating layer), (4) is a channel forming base region, and (5) is a drain high concentration region.

Next, the invention will be explained in detail using a MOS-PET, an example of which is shown in FIG. The illustrated semiconductor device (hereinafter abbreviated as device) has a drain region (the only difference being two regions).

That is, a material of the opposite conductivity type is diffused from a part of the main surface occupied by the drain region (2) to form the source region (2).
1) opposite conductivity type regions (6), (63...
・is formed. Looking at a part of the current flow path shown in FIG. 2 (particularly in the vicinity of the above-mentioned opposite conductivity type region), there is a PN junction between the P opposite conductivity type region (6) and the N drain region (the two In (7), the drain region is short-circuited at the pole and has an equal potential on the main surface, but the region close to the source region
That is, the potential becomes high in the deep portion, and holes are injected from the P region. The injected holes cause carrier modulation, which lowers the resistance of the drain region and reduces the voltage drop.

Conventional FETs include the vertical MOS-FET shown in Figure 4.
.

Horizontal MOS-FET shown in Fig. 5, vertical junction FET shown in Fig. 6, horizontal junction FET shown in Fig. 7
and so on. In each figure, (1) is the source region, (2
) is the drain region, (3) is the silicon oxide layer, (4) is the channel forming base region, (5), (to), l'le
(8) (+, l is the gate region, f9) is the ld isolation region.

The device shown in FIG. 8 is a vertical MOS-FET, in which the drain region consists of a drain region (12) and a drain high concentration region (+) provided on the drain electrode (D) side, and a Opposite conductivity type regions fle and H− are formed from a part of the main surface to face the source region.

Next, the device shown in FIG. 9 is a horizontal MOS-FET in which the drain high concentration region ffi is formed on the same main surface side as the source region (1) and the channel forming base region (4). Conductivity type regions (a), (2e...) are formed.

Next, FIG. 10 shows a lateral J-FET element. In the figure, (8) is the gate region, C1 is the drain high concentration region, (A) is the opposite conductivity type region according to the present invention, and (9) is the gate region. It is a separate area.

Furthermore, the vertical J-FET shown in FIG. is the gate region.

Note that the opposite conductivity type region according to the present invention forms a junction with the drain region, but in the above embodiments, it is shown as if they were all short-circuited by the drain electrode. but,
If the purpose of short circuiting can be substantially achieved, means such as destroying the junction in the vicinity of the drain electrode may be used.

The phenomenon based on the diagonal structure is such that the larger the current flowing from the source, the larger the injection, so the effect is greater as the switching current becomes larger. In addition, although this structure tends to slow down the switching time by the time the injected holes disappear, it is possible to achieve the effect of significantly reducing voltage drop loss in practical use. Based on this, there is a significant advantage that the size of the semiconductor chip can be reduced.

[Brief explanation of drawings]

Fig. 1 is a cross-sectional view for explaining the ON resistance in a MOS FET, Fig. 2 is a cross-sectional view of a MOS PET, Fig. 3 is a cross-sectional view of a MOS FET element of the first embodiment, Fig. 4, Fig. 5, 6 and 7 are all cross-sectional views of a conventional FFJT element, and FIGS. 8, 9, 1θ, and 11 are cross-sectional views of a FEAT element according to Embodiment K of the present invention. It is. 1 Source region 2.2' Drain region 4 Channel forming base region 5.15, 25
, 35.45 Drain high concentration region 6.16, 26, 36.46 Drain region and opposite conductivity type region D Drain electrode S Source electrode G Gate electrode agent Patent attorney Inoue -M Figure 1 Figure 2 Figure 137 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10

Claims (1)

[Claims] +1) In a field effect transistor, majority carriers are injected into the drain region to provide an opposite conductivity type region that reduces the voltage drop in the drain region, and the opposite conductivity type region is provided by a drain electrode connected to the drain region. A field effect transistor characterized by having a type region short-circuited. (2. The field effect transistor according to claim 1, wherein the opposite conductivity type region extends from a surface short-circuited with the drain region at the drain electrode toward the source region. Insulated gate field effect transistor. (3) In the field effect transistor according to claim 1, the opposite conductivity type region extends toward the source region along a surface short-circuited with the drain region at the drain electrode. A lateral insulated gate field effect transistor characterized in that: (4) In the field effect transistor according to claim 1, the opposite conductivity type region extends from the surface short-circuited with the drain region at the drain electrode toward the source region. (5) In the field effect transistor according to claim 1, the opposite conductivity type region is short-circuited with the drain region by the drain electrode. A lateral junction field effect transistor that extends along the source region.