JPS6381861A - Conductivity modulation mosfet - Google Patents

Abstract

PURPOSE:To prevent the latch-up of a parasitic thyristor and to obtain a great current, by forming the n<+> drain region directly under a p-type base thickly and the n<+>-type drain region directly under a flow path thinly, and by connecting the n<+> drain region to the first drain electrode by means of an n<+>- type well region. CONSTITUTION:A high impurity concentration thick n<+> drain region 11 is formed directly under a p-type base region 4. The n<+>-type drain region 12 directly under the n drain region 16 of a current path is also formed thinner than the thickness of the n<+>type drain region 11 directly under the p-type base region 4. This enables the effective pouring of a hole from a p-type drain region 1 to the n<->-type drain region 16 of the current path and the flow of a great current due to conductivity modulation. Further, the n<+>-type drain regions 11 and 12 are connected to the first drain electrode 10 via an n<+>-type well region 13, the second drain electrode 14 and a wire 18 for leading out an electrode. An electron poured into the current path 16 after a gate signal is made OFF flows in the first drain electrode 10 so the turn-off characteristics are made good.

Description

[Detailed description of the invention] [Industrial field of application] This invention relates to a conductivity modulated MOS FET (hereinafter referred to as ■G
The present invention relates to IGBTs (referred to as BTs), and particularly IGBTs having a structure in which the ruff-up phenomenon of parasitic transistors is less likely to occur and a large current can be obtained.

[Conventional technology]

Conventionally, as a high-power, high-speed semiconductor device, there has been developed an ICRT, in which minority carriers are injected into the drain region of a vertical MO8 field effect transistor to cause conductivity modulation, thereby obtaining a large current. I of
GBT will be briefly explained using FIG.

First, as shown in FIG. 2 (al), a high impurity concentration n-type drain region is formed on a p-type semiconductor substrate 1 which will become a drain region, and then a low impurity concentration n-type drain region is further formed thereon. Subsequently, as shown in FIG. 2 (bl), a p-type base region 4 is formed in the n-type drain region 3, and an n-type source region 5 with a high impurity concentration of 7% is formed in the base region 4. , a polysilicon gate 1 is formed on the portion of the p-type base region 4 that will become the channel region with a gate oxide film 6 interposed therebetween.Subsequently, as shown in FIG. In the process, a source electrode 8 is formed to electrically connect the n-type source region 5 and the p-type base region 4, and a drain electrode 10 is deposited on the back surface of the p-type drain region 1 to obtain the desired I. A GBT is obtained. FIG. 3 shows an equivalent circuit of this IGBT.

As can be seen from FIGS. 2 and 3, the element with this structure basically has a silice structure of npnp4 tank, but in the element with this structure, the p-type drain region 1 to n
The purpose is to effectively obtain a large current by injecting minority carriers into the n-type drain region 3 to cause conductivity modulation of the n-type drain region 3.

[Problem that the invention seeks to solve]

However, as mentioned above, devices with this structure are basically np
Since the thyristor has a four-tank structure, the latch-up phenomenon of the thyristor occurs.The operating range of the IGET is narrow, making it difficult to use.

Therefore, the most important point in the development of IGBTs was how to suppress the thyristor launch-up phenomenon.
As in the conventional example above, the high-temperature n'' type drain region 2 is formed between the p type drain region 1 and the n- type drain region 3, thereby reducing the gain of the parasitic pnp) run risk and suppressing the thyristor's rift swelling phenomenon. There is a method of suppressing this, but this method suppresses the injection of minority carriers from the p-type drain region 1 to the n-type drain region 3, which has the disadvantage that the feature of this device, which is the ability to obtain a large current, is lost. In addition, the high-speed characteristic, which is one of the characteristics of IGBTs, is also affected.In other words, IGBTs are switched to the off state by cutting off the gate signal, but n
- Since the off state is reached only after the carriers injected into the -type drain region 3 are removed, the high concentration n
When the ''-type drain region 2 is formed between the p-type drain region 1 and the n-type drain region 3, electrons injected into the n-'-type drain region 3 are difficult to flow out through the p-type drain region 1, and the state is turned off. It also has the disadvantage that it takes a long time to turn off, that is, its turn-off characteristics are poor.

The present invention has been made in view of the above problems, and an object of the present invention is to provide an IGBT with a wide safe operating range and good turn-off characteristics, which can suppress latch-up of parasitic silicon risks while maintaining low element resistance. shall be.

[Means for solving problems]

In the IGBT according to the present invention, the drain region is formed thick with a high impurity concentration immediately below the p-type base region, and holes are injected from the p-type drain region between the p-type base regions.
A high impurity concentration n' drain region immediately below the drain region is formed thinly, and the n' drain region is further formed into a high impurity concentration n' type well.

It is electrically connected to the first drain 1 via the second drain electrode.

[Effect]

In the present invention, parasitic PNP in the region directly under the p-type base
Since the n3 drain region, which corresponds to the base region of the transistor, is formed thickly, the gain of the parasitic PNP-TH is small, and latch-up of the parasitic thyristor can be suppressed. Since it is formed thinly, hole injection from the p-type drain region to the n-type drain region is not restricted, and large conductivity modulation can occur in the n-type drain region, resulting in a large current. After the gate signal is turned off, the electrons injected into the n-type drain region pass through the n-type well to the drain 1! Since the structure is such that the flow flows toward the pole, the turn-off time can be shortened.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIGS. 1(a) to 1(e) show an IGB according to an embodiment of the present invention.
It is a sectional view showing T in process order, and in the figure, 1°3~
Reference numeral 10 is the same as that in FIG. A thin n-type drain region (a second semiconductor region of the second conductivity type) formed between the drain regions 11 and electrically connecting them; 17 is a high impurity concentration n-type well region (fourth second-conductivity type semiconductor region) formed to penetrate through the third second-conductivity-type semiconductor region 3 and reach the n+-type drain region 11; IGBT chip !3 placed on the external lead wire, 14 is the above n9 type well region 1
3, which is connected to the first drain WailO by an electrode lead wire 18 connected to the external lead.

Next, the manufacturing method will be explained.

First, as shown in FIG. 1(a), a high impurity concentration n-type drain region 11 is formed in a predetermined portion of the p-type semiconductor substrate 1 that will become a drain region, and a gl n +-type drain region 11 is formed.
The n-type drain region 1 is electrically connected to
An n-type drain region 12 with a high impurity concentration is formed earlier than the first step.

Next, as shown in FIG.
After forming an n-type drain region 3 with a low impurity concentration on the entire surface of the p-type semiconductor substrate 1 so as to bury the regions 12 and 12, a high impurity dopant is formed so as to penetrate through the n-type drain region 3 and reach the n-type drain region 11. A concentration n-type well region 13 is formed.

Next, as shown in FIG. 1 (C1), a p-type space region 4 is formed above the thick n-type drain region 11 in the n-type drain region 3, and a high impurity concentration n-type is formed in the p-type base region 4. After forming source region 5, polysilicon gate electrode 7 is formed on p-type base region 4, which will become channel region 15, with gate oxide film 6 interposed therebetween.

Next, as shown in FIG. 1+d), a source electrode 8 is formed on the n + type source region 5 and the p type base region 4 so that they are electrically connected, and a second drain electrode 14 is formed on the n+ type well region 13, and the first drain electrode 10 is formed on the back surface of the p type semiconductor substrate 1, thereby obtaining the IGET chip of the present invention.

Next, as shown in FIG. 1(e), the IGBT chip 17 is mounted on the external lead in an assembly process, and one end of the electrode lead wire 18 is connected to the external lead using wire bonding technology, and the other end is connected to the second drain electrode. 14 to electrically connect the first drain electrode 10 and the second drain electrode 14 to obtain the IGBT of the present invention.

Next, the effects will be explained.

In the IGBT having such a structure, since the thick n-type drain region 11 with high impurity concentration is formed directly under the p-type base region 4, the gain of the parasitic PNP run risk can be suppressed significantly. Therefore, normally, if the sum of the gains of the NPN and PNP run risks constituting a thyristor becomes 1 or more, the parasitic thyristors will cause a latch-up phenomenon, but in the IGBT of this embodiment, it is possible to suppress the occurrence of the launch amplifier. can.

Further, in a normal IGBT, an electron current, which is the main current, flows from the source electrode 8 through the n+ type source region 5, flows laterally through the channel region 15, flows into the n- drain region 3, and further flows from the n- type drain region 3 to the n+ type source region 5. shaped drain region 1
The current flows through the 2p type drain region l to the drain i%10, and by injecting holes from the p type drain region 1 into the current path 16 of the n-type drain region 3, the conductivity of the current path 16 is modulated. However, in this embodiment, the n+ type drain region 12 directly under the n- drain region 16 of the current path is formed thinner than the thickness of the n-type drain region 11 directly under the p-type base region 4. Therefore, holes are effectively injected from the p-type drain region 1 into the n-type drain region 16 of the current path.

As a result, conductivity modulation occurs in the n-type drain region 6, effectively lowering the resistivity and allowing a large current to flow effectively.

Furthermore, in the IGBT of this embodiment, the n-type drain regions 11 and 12 are connected to the first drain electrode via the n-type well region 13, the second drain hole 14, and the electrode extraction wire 18. ff11O, the electrons injected into the current path 16 after the gate signal is turned off are transferred to the n-type well region 13. Since it flows out to the first drain electrode 10 through the second drain electrode 14 and further through the electrode lead wire 18, the turn-off characteristics are improved.

As described above, according to this embodiment, holes are effectively injected from the p-type drain region 1, and the launch-up phenomenon of the parasitic thyristor can be suppressed, and furthermore, high-speed characteristics can be improved.

In the above embodiment, the case of an n-channel IGBT was described, but it may also be a p-channel IGBT.
In this case as well, the same effects as in the above embodiment can be obtained.

〔Effect of the invention〕

As described above, the conductivity modulated MO3FET according to the present invention
According to the authors, by forming the n''' drain region directly under the p-type base thick, it is possible to suppress the occurrence of the latch-up phenomenon of the parasitic thyristor, and by reducing the thickness of the n''' type drain region directly under the current path, it is possible to reduce the thickness of the semiconductor substrate. In addition, since the n゛ drain region is connected to the first drain electrode by the n゛ type well region, when the gate signal is turned off, the n+ Electrons injected into the n-type drain region on the drain region can be flowed out to the first drain electrode in a short time through a low-resistance n-type well region, etc.
As a result, launch-up of the parasitic thyristor can be suppressed, and a large current can be obtained.

[Brief explanation of the drawing]

FIG. 1 shows a conductivity modulated MO3 according to an embodiment of the present invention.
FIG. 2 is a sectional view showing the main manufacturing process of a FET, FIG. 2 is a sectional view showing the manufacturing process of a conventional conductivity modulation MOSFET, and FIG. 3 is an equivalent circuit diagram of a conductivity modulation MO3FET. DESCRIPTION OF SYMBOLS 1...p-type semiconductor substrate, 3...n-type drain region, 4...p-type base region, 5...n-type source region, 6...gate oxide film, 7... Polysilicon gate electrode, 8... Source electrode, 10... First drain electrode, 11... Thick n-type drain region 12...
Thin n°-type drain region 13...n°-type well region, 14... second drain electrode, 15... channel region, 16... current path, 17... conductivity modulation type M
OS FET chip. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] (1) A first conductive layer with a high impurity concentration selectively formed in a predetermined region on the surface of the first conductivity type semiconductor substrate, which becomes a drain region.
a second conductivity type semiconductor region formed on the first conductivity type semiconductor substrate, adjacent to the first second conductivity type semiconductor region and shallower than the second conductivity type semiconductor region;
a third second conductivity type semiconductor region formed on the first conductivity type semiconductor substrate so as to embed the first and second second conductivity type semiconductor regions; a fourth second conductivity type semiconductor region formed to penetrate the third second conductivity type semiconductor region and reach the first or second second conductivity type semiconductor region; a first conductivity type base region formed in a second conductivity type semiconductor region, a second conductivity type source region formed in the base region, and a gate insulating film formed over a channel portion in the base region; a source electrode formed on the source region and the base region and electrically connecting them in a portion away from the channel portion; 1 drain electrode; and a second drain electrode formed on the fourth semiconductor region of the second conductivity type and electrically connected to the first drain electrode. type MOSFET
.