JPS6258678A - Transistor - Google Patents

Abstract

PURPOSE:To prevent the decline of current amplification degree consequent on concentration of current on the side plane of an emitter by providing an annular addition region of the same conductive type as of a collector region which surrounds a connecting part between a base electrode and a base region, in the base region. CONSTITUTION:In a base region 4, an addition region 6 of the same conductive type as of a collector region 2 is formed so that it surrounds a base electrode 7. By this constitution, a P-N junction is formed between said region 6 and the base region 4 and accordingly a depletion layer is produced around the addition region 6 which restrains the current injected into the base region directly from the side wall of an emitter 5. As a result, the main injected current flows out of the lower side of the emitter 5, thereby preventing the concentration of current on the side plane of the emitter and the resulting decline of current amplification degree due to the recombination in the surface condition of the boundary with an oxide film. Also, as the available emitter area on a constant chip area increases, the enhancement of collector saturation voltage and the decline of d.c. current amplification degree of large current can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to transistors, particularly power transistors.

2. Description of the Related Art Conventionally, power transistors suffer from a phenomenon called secondary breakdown, which limits the safe operation area. Therefore, breakdown resistance has been improved by increasing the collector resistance, expanding the emitter region, etc. This manufacturing method can improve breakdown resistance, but the main electrical properties of power transistors are
There are drawbacks such as an increase in collector saturation voltage and an increase in manufacturing cost due to enlargement of the emitter region.

In order to eliminate such drawbacks, attempts have been made to add a resistor to the base region to alleviate current concentration and improve breakdown resistance. For example, when adding a resistor around the emitter of a power transistor, first a collector region and a base region are formed on a semiconductor substrate. Next, an emitter region and an additional region of the same conductivity type as the emitter region are selectively formed in the base region so as to surround the emitter.

In a 1-transistor having such a structure, injection of carriers from the emitter side surface into the base region is prevented, current concentration in the emitter side surface region is alleviated, and the breakdown resistance level is improved.

Problems to be Solved by the Invention In such a conventional structure, since the additional region is formed in the region surrounding the emitter region, the additional region occupies a large area, which reduces the collector saturation voltage, which is one of the essential electrical characteristics of a power transistor. This has the disadvantage that the current increase rate for large currents decreases.

An object of the present invention is to provide a transistor in which the breakdown resistance level can be changed without reducing the collector saturation voltage or the current increase rate of large current.

Means for Solving the Problems The transistor of the present invention has a collector region of a first conductivity type and a second conductivity type opposite to the first conductivity type adjoining and between said collector region l) N A base region forming a junction, and an emitter region of a first conductivity type contacting the base region and forming a PN junction therebetween, and the base region has a base electrode contacting the surface thereof. and an annular additional region of the first conductivity type that is located in the base region and surrounds the connecting portion between the base electrode and the base region.

Effect: According to this configuration, since an additional region of the same conductivity type as the emitter region is formed in the base region so as to surround the base electrode, a PN junction is formed between the base region and the additional region, creating a depletion layer around the additional region. , the current injected directly from the sidewall of the emitter into the base region below the base electrode is limited, and the main injection current flows mainly from the bottom surface of the emitter, resulting in concentration of current on the sidewall of the emitter and the accompanying oxide film. It is possible to prevent a decrease in the current increase ratio due to recombination at the surface state of the interface with Increase in voltage and decrease in DC current amplification rate for large currents can be reduced.

EXAMPLE Next, an example of the present invention will be explained in detail using the process cross-sectional diagram shown in FIG. An N-type 60Ωctn silicon substrate 1 with a thickness of 230μI to which phosphorus has been added is immersed in acid to form an oxide film 3. After removing the oxide film on one side, phosphorus is diffused on that surface to give a surface concentration of 1×10”cm−. 3. Diffusion depth 1
A collector region 2 with a high concentration (N") of 50 μ+a is formed [Fig. 1(a)]. After that, a window for selective base diffusion is formed by photoetching the oxide film 3 on the opposite side, and a window is formed through this window. Diffuse boron, surface concentration 5x
Base region 1 of 10” cm’, diffusion depth 15 μl
(Fig. 1(b)). Thereafter, the oxide film 3 on the base region is etched into the emitter region and the additional region by photoetching again. By diffusing phosphorus through this window, an N1 type emitter region 5 and an additional region 6 with a surface concentration of 2×10'° C1n-' and a diffusion depth of 10 μl are simultaneously formed [Fig. 1(C)]. 10 is a channel. This is a stopper.A conductor 4M7.8.9 is formed in each of the base, emitter, and collector regions on the semiconductor substrate on which the diffusion process has been completed as described above (FIG. 1(d)).
.

Next, the operation and characteristics of this embodiment will be explained.

Since a PN junction is formed between the additional region 6 surrounding the base electrode 7 and the base region, a depletion layer is formed around the additional region 6, and the base electrode 7 is directly connected to the side wall of the emitter region 5. The current injected into the base region below is limited, and the main injection current flows out from the bottom surface of the emitter, leading to concentration of current on the side surface of the emitter and an accompanying increase in the surface of the interface with the oxide film 3. A decrease in the current amplification rate due to recombination in state J3 can be prevented. Also, additional area 6
Compared to the conventional example in which the base electrode 7 is formed by surrounding the emitter region 5, in this embodiment, the base electrode 7 is surrounded, so the required length of the region 6 is shortened, and a constant chip is formed by this amount. The usable emitter area becomes large, the collector saturation voltage increases, and the large DC current increases. Breakdown voltage V S/B, collector saturation voltage VcE (s^T) and large current DC amplification rate (1”I
The experimental results of the collector current characteristics of Fe) are shown in Figure 2 (aL
As shown in (b) and (C), compared to the conventional example described above, the secondary breakdown voltage is increased, the collector saturation voltage is decreased, and the DC current amplification rate at large current values is increased. .

As described in the detailed description of the invention, the transistor according to the present invention has a base region including a base electrode in contact with the surface thereof, and a collector region in a ring shape within the base region and surrounding a connecting portion between the base electrode and the base region. By providing an additional region of the same conductivity type as the collector saturation current f'L, the DC current increase in J3 at large current values [for power use with a wide safe operating range without sacrificing characteristics at jJ rate] can be achieved. It is something that can be done.

[Brief explanation of the drawing]

ω Figure 1 shows the manufacturing TPi of an embodiment of the four transistors of the present invention.
! The sectional view and FIG. 2 are explanatory diagrams for comparing the characteristics of secondary breakdown voltage, collector saturation voltage, and DC current increase Ill rate with respect to collector current when the present invention is applied to a power transistor. 1... Silicon substrate, 2... Collector region, 3...
・Silicon oxide film, 4...Base region, 5...Emitter region, 6...Additional region, 7...Base electrode, 8
...Emitter electrode, 9...Collector electrode, 10...
・Ch 12-channel stopper Figure 2 2.0 4. Q6. Orc (A) FE 2, () a, o 6.0 1c (A) To Illusion

Claims (1)

[Claims] 1. A collector region of a first conductivity type, a base region of a second conductivity type opposite to the first conductivity type and in contact with the collector region to form a PN junction therebetween; An emitter region is provided in contact with the base region to form a PN junction therebetween, and the base region includes a base electrode in contact with the surface thereof, and a connection portion between the base electrode and the base region within the base region. and a first conductivity type additional region surrounding the transistor.