JP3206149B2 - Insulated gate bipolar transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulated gate bipolar transistor (IGBT) having a so-called horizontal structure suitable for an integrated circuit device or the like.

[0002]

2. Description of the Related Art As is well known, an IGBT is a bipolar transistor whose gate can be controlled, and has a feature that it has both a high input impedance of a field effect transistor and a low output impedance of a bipolar transistor. It is widely used as a suitable individual semiconductor device for electric power. Conventionally, the IGBT as an individual element is usually of a vertical structure, but recently, there has been a tendency to use a so-called intelligent element, which is an integrated circuit integrally incorporating a control circuit related to its operation. Due to the growing trend, IGBTs are increasingly adopting horizontal structures that are advantageous for integration. FIG. 5 shows a typical example of the conventional structure of this horizontal IGBT.

FIG. 5 shows an IGBT 40 in a unit structure. A chip or wafer 10 for the IGBT 40 has an n-type epitaxial layer formed on a p-type substrate 11 in the same manner as in a normal integrated circuit.
40 is grown as a semiconductor region 12 to be formed.
First, an n-type buffer layer 41 is diffused from the surface of the semiconductor region 12 to the left and right sides of the figure, and a p-type base layer 42 is diffused at the center of the figure.
In the base layer 42, the base connection layer 44 is diffused in a p-type with a high impurity concentration. Next, a gate 45 is disposed above both ends of the base layer 42 via a thin gate oxide film 45a,
The n-type source layer 46 having a high impurity concentration is shallowly diffused by an ion implantation method using this as a part of a mask. further,
The base layer 44 and the source layer 46 are short-circuited by the electrode film 30 to derive the emitter terminal E, the collector terminal C from the collector layer 43, and the gate terminal G from the gate 45.

The operation of the horizontal IGBT 40 will be described. When a gate potential more positive than the emitter terminal E is applied to the gate terminal G, a channel is conducted to the surface of the base layer 42 below the gate 45, so that electrons, which are majority carriers, are transferred from the source layer 46 to the semiconductor region 12 through the channel. Is injected into. This allows IGBT40
Is turned on, but holes that are minority carriers are then injected into the semiconductor region 12 through the buffer layer 41 by the electrons flowing into the collector layer 43, and the base layer 42 and the collector layer 43 The conductivity of the semiconductor region 12 therebetween increases, and the on-voltage of the IGBT 40 is further reduced. In order to turn off the IGBT 40, the gate potential given to the gate terminal G may be eliminated to make the channel below the gate 45 non-conductive.

As described above, the IGBT 40 has an advantage that the ON voltage can be reduced by utilizing the conductivity modulation at the time of ON, but the OFF operation speed is slow because the carrier needs to be removed from the conductivity modulation region at the time of OFF operation. There is a disadvantage that it is easy to become. By setting the impurity concentration of the buffer layer 41 higher than that of the semiconductor region 12, the buffer layer 41 controls the amount of minority carriers injected from the collector region 43 into the semiconductor region 12, thereby improving the off operation speed of the IGBT 40. Normally, it is not enough, so introducing a lifetime killer such as platinum into the semiconductor region 12 will slightly increase the on-voltage, but usually promote the disappearance of carriers in the conductivity modulation region during the off operation. It is.

[0006]

Although the conventional horizontal IGBT as described above can have a low on-voltage and an appropriate off operation speed almost the same as those of the vertical structure,
There is a problem that latch-up is more likely to occur than in the vertical structure. FIG. 6 shows the cause of the occurrence of the latch-up in the right half of FIG. 5 by the flow path of the carrier. IGBT40
At the time of turning on, the electrons e, which are majority carriers, pass from the source layer 46 to the channel below the gate 45, and then are horizontal, so that the collector layer 43 passes through the surface of the semiconductor region 12 as shown in the figure.
Flows to The hole h which is a minority carrier is the collector layer 43
Then, after entering the base layer 42 through the surface portion of the semiconductor region 12 in the opposite direction, it flows to the electrode terminal 30 for the emitter terminal E through the lower side of the source layer 46 as shown in the figure.

The p-type collector layer 43, the n-type semiconductor region 12, the p-type base layer 42, and the n-type source layer 46 form a pnpn thyristor structure. When a hole current is injected into the pn junction between the source layers 46, the ignition occurs and a latch-up in which a large current flows between the emitter terminal E and the collector terminal C occurs. In the case of the vertical type, the hole current flows upward from the lower side of the figure toward the emitter terminal E, so that almost no current flows in the vicinity of the pn junction described above.
Since the gas flows so as to bypass the lower side of 46, the above-described injection into the pn junction is more likely to occur particularly at the point indicated by A in the figure. Due to the risk of such latch-up, the horizontal IGBT has lower operation reliability than the vertical IGBT, and it is difficult to increase the current capacity. An object of the present invention is to solve such a problem and improve the latch-up resistance of an IGBT having a horizontal structure.

[0008]

According to the IGBT of the present invention,
The base layer is diffused with the other conductivity type from the surface of the semiconductor region having one conductivity type , and a base connection layer having a higher impurity concentration than the base layer is formed on one side of the other side so that the base layer partially overlaps the base layer. diffuse form, shallow diffused source layer on one conductivity type in the base layer and the range including the boundary between the two layers from the surface of the base connection layer, the source on the other side of the base layer
Disposed the gate so as to cover the surface between the layer and the semiconductor region from the upper side, a collector layer from the surface of one side of the semiconductor region of the base layer on which is spread by the other conductivity type, the base connecting layer and the source The above object is achieved by deriving the emitter terminal from the layer, the collector terminal from the collector layer, and the gate terminal from the gate. In addition, the base layer
By making the diffusion depth of the connection layer shallow, the base
Compared to the case where the connection layer is deeper than the base layer,
Current path is wide in the semiconductor region of
I can do it.

In order to maximize the off operation speed of the IGBT of the present invention having such a structure, one collector type short-circuit layer is diffused from the surface of the semiconductor region adjacent to the collector layer so that the collector terminal is formed from both layers. It is advantageous to derive it, and the gate is
Surrounds the gate end of the plane pattern part surrounded by the
Diffusion instead of the collector layer within the range described above is particularly advantageous in increasing the off operation speed of the IGBT and further improving the latch-up resistance.

[0010] The semiconductor layer and the gate constituting the IGBT of the present invention may be arranged in a planar pattern such that the elongated strip-shaped gate is surrounded by a collector layer via an annular emitter region, or the elongated strip-shaped gate. The collector layer may be surrounded by a gate via a ring-shaped emitter region, but the gate and the collector layer may be arranged in a comb-shaped pattern so that the emitter region is meandered between the comb teeth. It is particularly advantageous to arrange in such a way that

In the method of manufacturing an IGBT according to the present invention, the base connection layer and the collector layer are simultaneously formed by diffusion.
Is advantageous in reducing the number of steps.

[0012]

As can be seen from FIGS. 5 and 6, in the conventional IGBT, the emitter region including the base connection layer 44 and the source layer 46 is connected to the collector layer with respect to the channel region which is the surface of the base layer 42 below the gate 45. Although arranged on the side opposite to 41, the present invention arranges this emitter region on the collector layer side from the channel region, and arranges the base connection layer in the emitter region on the collector layer side from the source layer, As described above, the hole current, which is a minority carrier flowing into the emitter region from the collector layer, is drawn out to the base connection layer, and the hole current flows laterally into the base layer below the source layer, which causes latch-up. Is almost completely absent.

That is, in the present invention, as described in the preceding paragraph, for example, a p-type base layer is diffused on the surface of an n-type semiconductor region,
The p-type base connection layer is diffused on one side so as to partially overlap the base layer, and the p-type collector layer is diffused on the surface of the same one-side semiconductor region. By diffusing the n-type source layer shallowly into the range including the boundary and providing a gate so as to cover the surface of the base layer on the other side of the source layer from above, the base connection layer and the source are formed in the channel region below the gate. An emitter region consisting of a layer is arranged on the same side as the collector layer.

Thus, the hole current from the collector layer passes through the closest base connection layer to the emitter terminal, and only a part of the hole current flows from the base layer to the lower side of the source layer via the base connection layer. However, since the lateral component below the source layer in the flow path is generated not in the base layer as in the conventional case but in the base connection layer having an impurity concentration higher by one digit or more than that of the base layer and having a low specific resistance, there is a gap between it and the source layer. Almost no hole injection into the pn junction occurs.
The BT latch-up capability can be improved.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a cross-sectional view showing the structure and operation of the first embodiment of the present invention by a carrier flow path, FIG. 2 is a cross-sectional view of a second embodiment having a collector short layer of the present invention, and FIG. FIG. 4 is a top view of a third embodiment of the present invention in which layers are formed in a comb-like pattern in which the layers are intertwined with each other. FIG. 4 shows a fourth embodiment of the present invention in which a collector short layer is provided in an area surrounding the end of the gate pattern. FIG. 4 is a top view of the example.

FIG. 1A shows the IGBT 20 of the first embodiment in a cross section of the unit structure corresponding to FIG. IGBT20 according to the invention
However, this unit structure is usually repeated plural times in the left-right direction in the figure. The wafer 10 in which the IGBT 20 of this embodiment is manufactured is formed by growing an epitaxial layer to a thickness of several tens of μm as an n-type semiconductor region 12 on a p-type semiconductor substrate 11, for example, as in the prior art. It is preferable that the resistance is relatively high. Since the IGBT 20 of this embodiment uses the buffer layer 21 on the collector side, in the manufacturing process, the n-type buffer layer 21 is first formed from the left and right surfaces of the semiconductor region 12 with an impurity concentration of, for example, 10 ¹⁶ atoms / cm ³ from the left and right surfaces. A gate 22 having a thickness of about 0.5 .mu.m and having a thickness of about 0.1 .mu.m made of polycrystalline silicon is provided at a central portion of the semiconductor region 12 in the figure, which is diffused to a depth of 5 .mu.m, via a very thin gate oxide film 22a of about 0.1 .mu.m.

Next, a p-type base layer 23 is inserted, for example, 10
It diffuses to a depth of 4 μm with an impurity concentration of ¹⁷ atoms / cm ³ .
This base layer 23 is advantageously formed by boron ion implantation using the gate 22 as a part of the mask and thermal diffusion thereof. Next, the collector layer 24 and the base layer in the buffer layer 21
23 and a base connection layer 25 partially overlapping with each other are formed to a depth of about 2 μm at a high impurity concentration of p-type 10 ¹⁸ to 10 ¹⁹ atoms / cm ³ by simultaneous diffusion of boron. Further, arsenic ion implantation using the n-type source layer 26 on both sides of the gate 22 as a part of the mask as usual and thermal diffusion thereof are used.
For example, it is formed to a depth of 0.2 μm with a high impurity concentration of 10 ²⁰ atoms / cm ³ and a pattern including a boundary between the base layer 23 and the base connection layer 25 as shown in the figure. The surface of the base layer 23 below the gate 22 between the source layer 26 and the semiconductor region 12 becomes a channel region.

As described above, the fabrication of the semiconductor layer of the IGBT 20 is completed. Then, an aluminum electrode film 30 for the terminal is provided at a key position as shown in the figure. Base connection layer 25 and source layer
The surface of 26 is short-circuited by an electrode film 30 as shown in the figure to derive an emitter terminal E therefrom, and from the electrode film 30 which is in conductive contact with the gate 22 and the collector layer 24, respectively, a gate terminal G and a collector terminal C respectively. Is derived to obtain the completed state of the horizontal IGBT 20 shown in FIG. Note that the electrode film for the gate 22 is provided at a location other than the illustrated cross section. In addition, a usual insulating film and a protective film are naturally provided in addition to the illustration, but they are omitted from the drawings for simplification.

Next, the operation of the IGBT 20 of the first embodiment will be described with reference to FIG. 1B, which is an enlarged cross section of the right half of FIG. 1A. As can be understood from the above description, in the structure of the IGBT of the present invention, the emitter region composed of the base connection layer 25 from which the emitter terminal E is led out and the source layer 26 is provided with respect to the channel region on the surface of the base layer 23 below the gate 22. Contrary to the conventional structure, it is provided on the same side as the collector layer 24. Accordingly, when a positive potential is applied to the gate terminal G with respect to the emitter terminal E to make the n-type channel below the gate 22 conductive, electrons e, which are majority carriers, are transferred from the source layer 26 to this channel as shown in FIG. After flowing into the semiconductor region 12 through the base layer 23, it flows toward the collector layer 24 through a considerably deeper area under the base layer 23 than before.

In response to the flow of the electrons e into the collector layer 24, the holes which are the minority carriers are conversely formed in the semiconductor region.
In the present invention, as shown in the figure, the flow path of the hole is drawn toward the flow path of the electron e by the Coulomb force and the internal flow path hi that passes through the inside of the semiconductor region 12 as shown in FIG.
It is distributed between the surface flow path hs flowing along the surface of the semiconductor region 12 toward the base connection layer 25 located at the shortest distance from 24. The component near the surface flow path hs in the hole current is extracted from the semiconductor region 12 to the base connection layer 25, and the component near the internal flow path hi passes through the base layer 23 and the base connection layer 25.
When the IGBT 20 is turned on, the latter is slightly larger than the former at the beginning, but it is considered that both are almost the same in the fully-on state where the conductivity modulation is active.

In the present invention, the component near the surface flow path hs of the hole current in the semiconductor region 12 is directly extracted to the base connection layer 25 as described above, so that the risk of latch-up is reduced as compared with the related art. The remaining problem is the component of the hole current passing near the internal flow path hi, which is, as shown, the base layer 23 and the base connection layer.
25, the flow is distributed between the flow paths indicated by hi1 and hi2. In particular, the component near the flow path hi2 has a horizontal current component below the source layer 26. Since the lateral component flows below the source layer 23 in the base connection layer 25, which has much lower specific resistance than the base layer 23, there is very little risk of holes being injected into the pn junction between the source layer 23 and the source layer 23. . As described above, in the present invention, a component near the surface flow path hs of the hole current is extracted to the base connection layer 25, and a component near the internal flow path hi is located below the source layer 26 and has a low specific resistance. Since it passes through the inside, the risk of occurrence of latch-up is greatly reduced as compared with the related art.

When the IGBT 20 is turned off, the potential of the gate terminal G is of course lost and the channel region below the gate 22 is turned off. Thereby, the semiconductor region 12 of the electrons e
Is stopped and the electrons e remaining therein are absorbed by the collector layer 24. However, the density of the electrons e in the semiconductor region 12 decreases, and the hole current of the hole current attracted by the Coulomb force is reduced. The ratio of the component near the internal flow path hi decreases and the ratio of the component near the surface flow path hs increases, and the depletion layer extends into the semiconductor region 12 after all of the latter component is pulled out to the base connection layer 25. IGBT20 is completely turned off. As can be seen from the above, in the IGBT 20 of the present invention, there is little danger of latch-up occurring during the OFF operation, and in particular, the IGBT 20 can improve the latch-up resistance against external noise or the like which easily enters the emitter terminal during the OFF operation.

In the second embodiment shown in FIG. 2, the collector region has a collector short structure in order to increase the off operation speed of the IGBT 20. As shown, n is adjacent to the p-type collector layer 24.
A collector short layer 27 is formed, the surfaces of both layers are short-circuited by the electrode film 30, and the collector terminal C is led out. Also,
In the example shown in the figure, a substrate bonded type wafer in which a substrate 11 and an n-type substrate for a semiconductor region 12 are bonded to each other via an oxide film 11a is used as the wafer 10 for the IGBT 20. Other structures are first
This is the same as the embodiment. In this embodiment, electrons e, which are majority carriers remaining inside the semiconductor region 12 during the off operation of the IGBT 20, are pulled out to the n-type collector short layer 27, thereby reducing the amount of reverse injection of holes and reducing the off operation time. To shorten. The collector short layer 27 is advantageously provided between the collector layers 24 from both sides as shown in the figure.
Further, the collector region may have a composite structure with the buffer layer 21 of the first embodiment.

FIG. 3 shows a third embodiment in which planar patterns of a channel region and a collector region are formed in a comb-like shape in which they are intricate with each other by a top view corresponding to the structure of the first embodiment. The comb teeth are formed to be elongated in the left-right direction in the figure, but the center part is omitted in the figure. As shown, the gate 22 covering the channel region has a comb shape protruding from the left to the right, and the collector region including the buffer layer 21, the collector layer 24 and the electrode film 30 thereon has a comb shape protruding from the right to the left. And the source layer is formed between these intertwined comb teeth.
The exposed surface of the semiconductor region 12 and the emitter region including the base connection layer 25, the base connection layer 25, and the electrode film 30 thereabove are arranged in a meandering pattern.

In the third embodiment, the gate 22 on the left side of FIG.
The gate terminal G is connected from the upper electrode film 30 to the collector layer 24 on the right side.
The collector terminal C can be very easily derived from the upper electrode film 30 as shown in the figure, and the emitter terminal E can be easily derived from an appropriate portion of the electrode film 30 on the emitter region. Further, this embodiment has an advantage that a chip area can be saved when an IGBT is built in an integrated circuit device. Of course, the invention is not limited to this, and the planar pattern of the IGBT of the present invention is not as easy to derive the terminals as in this embodiment.However, for example, the gate is formed in an elongated strip shape and is surrounded by the collector layer via the annular emitter region. Alternatively, an elongated strip-shaped collector layer can be formed so as to be surrounded by a gate via an annular emitter region.

FIG. 4 shows a fourth embodiment in a top view corresponding to the right side of FIG. However, this figure shows the pattern of the semiconductor layer excluding the gate 22 and the electrode film 30 from FIG. The center of the figure is the semiconductor region 12 and the base layer 23 covered by the gate, and the right ends thereof are the ends of the gate. An emitter region composed of the source layer 26 and the base connection layer 25 and the surface of the semiconductor region 12 surround the edge, and a buffer layer
21 is spread. When the p-type collector layer 24 including the right end is diffused outside the buffer layer 21, the current of the hole h injected into the semiconductor region 12 is concentrated at a high density in the emitter region as shown by a fan in the figure. Thus, latch-up is likely to occur there. For this reason, in the fourth embodiment, the n-type collector short layer 28 is diffused instead of the p-type collector layer 24 in the area corresponding to the gate end, and the surfaces of both layers are formed as electrode films for collector terminals. Short circuit. As a result, since there is no injection of holes in the area surrounding the gate end, conductivity modulation does not occur, and the current capacity of the IGBT is slightly reduced accordingly, but the weak point can be eliminated to improve the latch-up resistance.

Although the IGBT of the present invention described above is of a horizontal type, it can simultaneously provide a high withstand voltage of 200 V or more and a current capacity of several A or more, and can be easily built together with related circuits into an integrated circuit device. Further, an IGBT having a low ON voltage of about 2 V and a short OFF operation time of 2 to several μS can be obtained. It should be noted that the values of the conductivity type, impurity concentration, diffusion depth, etc. and the diffusion pattern of each semiconductor layer constituting the IGBT described in the above embodiments are merely examples, and the present invention is not limited to these but includes within its gist. The present invention can be carried out in various modes as necessary or necessary.

[0028]

As described above, in the IGBT of the present invention, the base layer of the other conductivity type is diffused from the surface of the semiconductor region of the one conductivity type, and the other conductivity type is provided on one side thereof so as to partially overlap the base layer. And a source layer of one conductivity type is diffused in a range including a boundary between the base layer and the two layers in the base connection layer, and a surface of the base layer on the other side of the source layer is covered from above. A gate, and a collector layer of the other conductivity type is diffused into the semiconductor region on one side of the base connection layer.
By deriving the collector terminal from the collector layer and the gate terminal from the gate, the following effects can be obtained.

(A) Contrary to the prior art, by disposing the emitter region on the collector layer side with respect to the channel region, the hole current flowing into the emitter region from the collector layer side is directly drawn to the base connection layer and the source layer is formed. The hole current flowing below the source layer, and the hole current component passing laterally below the source layer flows only into the base connection layer having a low specific resistance to prevent injection of holes into the pn junction with the source layer. Thus, the latch-up resistance of the IGBT having the horizontal structure can be improved.

(B) During the off operation of the IGBT, most of the hole current flows to the surface of the semiconductor region and is quickly drawn out to the base connection layer, so that the possibility of latch-up is extremely reduced, and especially in the off operation. As a result, it is possible to improve the latch-up resistance against external noise which easily enters from the emitter terminal. Further, since the absorption speed of the hole current is increased, the off operation time of the IGBT can be reduced as compared with the conventional case.

The present invention is particularly effective when applied to a horizontal IGBT to be incorporated in an integrated circuit device, and has a remarkable effect of improving the latch-up capability and the off-operation characteristic.

[Brief description of the drawings]

FIG. 1 shows the structure of a first embodiment of the insulated gate bipolar transistor according to the present invention. FIG. 1 (a) is a sectional view showing a unit structure thereof, and FIG. It is sectional drawing.

FIG. 2 is a sectional view of a second embodiment of the present invention in which a collector short layer is provided.

FIG. 3 is a top view of a third embodiment of the present invention in which a gate and a collector layer are formed in an intricate comb-like pattern.

FIG. 4 is a top view of a fourth embodiment of the present invention in which a collector short layer is provided in a range surrounding an end of a gate pattern.

FIG. 5 is a sectional view showing a unit structure of a conventional insulated gate bipolar transistor.

6 is a cross-sectional view showing a flow path of a carrier inside the conventional example of FIG.

[Explanation of symbols]

10 Wafer for insulated gate bipolar transistor 11 Substrate of wafer 12 Semiconductor region in which insulated gate bipolar transistor is formed 20 Unit structure of insulated gate bipolar transistor 21 Buffer layer 22 Gate 23 Base layer 24 Collector layer 25 Base connection layer 26 Source layer 27 Collector Short layer 28 Collector short layer 30 Electrode film for terminal C Collector terminal E Emitter terminal e Electron as majority carrier h Hole as minority carrier G Gate terminal

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 29/78

Claims (5)

(57) [Claims] 1. A semiconductor region of one conductivity type, a base layer of the other conductivity type diffused from the surface thereof, and a base layer diffused to one side thereof so as to partially overlap the base layer.
A base connection layer of the other conductivity type having a higher impurity concentration ,
A source layer of one conductivity type that is shallowly diffused from a surface of the base layer and the base connection layer to a range including a boundary between the two layers,
A gate disposed on the other side of the base layer so as to cover the surface of the base layer between the source layer and the semiconductor region from above;
And a base layer one side collector layer surface from conductivity type of the other diffused semiconductor region of the emitter terminal from base connection layer and the source layer, the collector terminal from the collector layer, respectively derived gate terminals from the gate An insulated gate bipolar transistor, comprising: 2. The insulated gate bipolar transistor according to claim 1, wherein the base connection layer is wider than the base layer.
An insulated gate bipolar transistor having a shallow diffusion depth . 3. The insulated gate bipolar transistor according to claim 2, wherein the gate and the collector layer are interdigitated with each other.
An insulated gate bipolar transistor, wherein the insulated gate bipolar transistor is arranged in a planar pattern intermeshing with teeth . 4. The insulated gate bipolar transistor according to claim 3 , wherein the gate is surrounded by a collector layer in a plane pattern area surrounding a gate end.
An insulated gate bipolar transistor, wherein a collector short layer of one conductivity type is diffused therein instead of the collector layer . 5. A method according to claim 1 , wherein the surface of the semiconductor region of one conductivity type is connected to the other.
The step of diffusing the base layer of the conductivity type of
Higher impurity concentration than the base layer on one side so that
Diffuse the base connection layer of the other conductivity type
Process and from the surface of the base layer and the base connection layer,
Diffusion of shallow source layer of one conductivity type within the range including boundary
And a source layer and a semiconductor region on the other side of the base layer.
A gate to cover the surface between
From the surface of the semiconductor region on one side of the base layer to the other side.
Diffusing a conductive type collector layer.
In a method for manufacturing a bipolar transistor, a base
And characterized by simultaneously diffusing form the connection layer and the collector layer
Of manufacturing insulated gate bipolar transistor .