JPH06151838A - Insulated gate bipolar transistor - Google Patents

Abstract

PURPOSE:To improve the amount of latch-up resistance of a horizontal type insulate-gate bipolar transistor suited for incorporation inside an integrated circuit device etc. CONSTITUTION:An emitter region including a p-type base connection layer 25 and an n-type source layer 26 is laid out at the same side as a collector region including an n-type buffer layer 21 and a p-type collector layer 24 for the channel region on the surface of a p-type base layer 23 at the lower side of a gate 22. Then, the current due to holes which are injected into a semiconductor region 12 from a collector region according to the current of an electron e which enters the n-type semiconductor region 12 from the source layer 26 via the channel region and then flows to the collector region is led to the base connection layer 25 via a surface channel (hs) for reducing the current components through an internal channel (hi) and then the current components flowing from the internal channel (hi) to the base layer 23 are led into the base connection layer 25 with a low resistivity at the lower side of the source layer 26, thus preventing latch-up from occurring.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a so-called lateral structure insulated gate bipolar transistor (hereinafter referred to as IGBT) suitable for an integrated circuit device or the like.

[0002]

2. Description of the Related Art As is well known, an IGBT is a bipolar transistor whose gate can be controlled, and is characterized by having both a high input impedance of a field effect transistor and a low output impedance of a bipolar transistor. It is widely used as a suitable power individual semiconductor device. Conventionally, the IGBT as an individual element is usually formed in a vertical structure, but recently, there is a tendency to use it in the form of a so-called intelligent element which is an integrated circuit in which a control circuit related to its operation is integrally incorporated. As the strength is increasing, the number of cases in which the lateral structure, which is advantageous for integration, is adopted for the IGBT is increasing. FIG. 5 shows a typical example of the conventional structure of this lateral IGBT.

FIG. 5 shows an IGBT 40 in its unit structure. A chip or wafer 10 for the IGBT 40 has, for example, an n-type epitaxial layer on a p-type substrate 11 as in an ordinary integrated circuit.
40 is grown as a semiconductor region 12 to be built.
The n-type buffer layer 41 is first diffused on the left and right sides of the figure from the surface of the semiconductor region 12, and the p-type base layer 42 is first diffused in the center of the figure, and then the collector layer 43 is formed in the buffer layer 41.
In the base layer 42, the base connection layer 44 is diffused as a p-type having a high impurity concentration. Next, the gates 45 are arranged above the both ends of the base layer 42 with the thin gate oxide film 45a interposed therebetween.
An n-type source layer 46 having a high impurity concentration is shallowly diffused by an ion implantation method using it as a part of a mask. further,
The base connection layer 44 and the source layer 46 are short-circuited by the electrode film 30 to derive the emitter terminal E, and the collector layer 43 derives the collector terminal C and the gate 45 derives the gate terminal G.

The operation of this lateral IGBT 40 will be described. When a gate potential on the positive side of the emitter terminal E is applied to the gate terminal G, a channel is conducted to the surface of the base layer 42 below the gate 45, so that electrons, which are majority carriers, are transferred from the source layer 46 through the semiconductor region 12 through the channel. Is injected into. This allows IGBT40
Is turned on, but holes that are minority carriers are then injected into the semiconductor region 12 through the buffer layer 41 by electrons flowing into the collector layer 43, and the so-called conductivity modulation action based on this causes the base layer 42 and the collector layer 43 to The conductivity of the semiconductor region 12 in between increases and the ON voltage of the IGBT 40 is further lowered. In order to turn off the IGBT 40, the gate potential applied to the gate terminal G may be erased to bring the lower channel of the gate 45 into a non-conducting state.

As described above, the IGBT 40 has an advantage that the ON voltage can be lowered by utilizing the conductivity modulation at the time of ON, but the OFF operation speed is slow because it is necessary to remove carriers from the conductivity modulation region at the time of OFF operation. There is a drawback that it tends to occur. The buffer layer 41 serves to improve the off-operation speed of the IGBT 40 by controlling the amount of minority carriers injected from the collector region 43 into the semiconductor region 12 by setting the impurity concentration thereof higher than that of the semiconductor region 12. Usually, this is not enough, so by introducing a lifetime killer such as platinum to the semiconductor region 12, it is common to promote the disappearance of carriers in the conductivity modulation region during the OFF operation, although the ON voltage increases slightly. Is.

[0006]

Although the conventional lateral IGBT as described above can have a low on-voltage and an appropriate off-operation speed which are almost the same as those in the vertical structure,
There is a problem that latch-up is more likely to occur than in the vertical structure. FIG. 6 shows the cause of this latch-up in the right half of FIG. IGBT40
When the electron is turned on, the electrons e, which are majority carriers, pass through the channel under the gate 45 from the source layer 46, and are horizontal, so that the collector layer 43 passes through the surface portion of the semiconductor region 12 as shown in the figure.
Flow to. The holes h that are minority carriers are in the collector layer 43.
Then, after entering the base layer 42 through the surface portion of the semiconductor region 12 in the opposite direction, it flows to the electrode film 30 for the emitter terminal E through the lower side of the source layer 46 as shown in the figure.

The p-type collector layer 43, the n-type semiconductor region 12, the p-type base layer 42, and the n-type source layer 46 form a pnpn thyristor structure, and the base layer 42 corresponding to the gate thereof is formed. When a hole current is injected into the pn junction between the source layers 46, it is ignited and a latch-up in which a large current flows between the emitter terminal E and the collector terminal C occurs. In the case of the vertical type, since the hole current flows upward from the lower side of the figure toward the emitter terminal E, it hardly flows in the vicinity of the above pn junction, but in the case of the horizontal type, the current of the hole h is as shown in the figure.
Since the current flows so as to bypass the lower side of 46, the above-mentioned injection into the pn junction is likely to occur particularly at the portion indicated by A in the figure. Due to the risk of such latch-up, the lateral IGBT has lower operational reliability than the vertical IGBT, and it is difficult to increase the current capacity. An object of the present invention is to solve such a problem and improve the latch-up withstanding capability of a lateral IGBT.

[0008]

According to the IGBT of the present invention,
The base layer is diffused from the surface of the semiconductor region having one conductivity type with the other conductivity type, and the base connection layer is diffused with the other conductivity type on one side so that the base layer partially overlaps,
The source layer is shallowly diffused by one conductivity type within the range including the boundary between the base layer and the base connection layer, and the gate is arranged so as to cover the surface of the base layer on the other side of the source layer from above. Then, diffuse the collector layer from the surface of the semiconductor region on one side of the base connection layer to the other conductivity type, and then derive the emitter terminal from the base connection layer and source layer, the collector terminal from the collector layer, and the gate terminal from the gate. By doing so, the above-mentioned object is achieved.

In order to maximize the off-operation speed of the IGBT of the present invention having such a structure, a collector short layer of one conductivity type is diffused from the surface of the semiconductor region adjacent to the collector layer to form collector terminals from both layers. It is advantageous to derive it. Further, diffusion of this collector short layer instead of the collector layer within the range surrounding the end of the gate pattern enhances the off-operation speed of the IGBT and further improves the latch-up withstand capability. Especially advantageous above.

As the pattern of the semiconductor layers and gates constituting the IGBT of the present invention in a plane, a strip-shaped gate is surrounded by a collector layer via an annular emitter region, or a strip-shaped strip. The collector layer may be surrounded by the gate via the annular emitter region, but the gate and collector layers may be arranged in a comb-shaped pattern so that the emitter region meanders between the comb teeth. Is particularly advantageous.

Further, in manufacturing the IGBT of the present invention, the base layer and the source layer are diffused by an ion implantation method in which impurities are introduced using the gate as a mask to improve the accuracy of the diffusion pattern of both layers and reduce the number of steps. Further, it is advantageous to reduce the number of steps by making the collector layer and the base connection layer having the same conductivity type into the same impurity concentration and the same diffusion depth by simultaneous diffusion.
Also in the IGBT of the present invention, it is advantageous to provide the buffer layer with one conductivity type in association with the collector layer for controlling the conductivity modulation as in the conventional case. It is arranged so as to cover the surface of the base layer on the other side of the layer.

[0012]

As can be seen from FIGS. 5 and 6, in the conventional IGBT, the emitter region composed of the base connection layer 44 and the source layer 46 is formed in the collector layer with respect to the channel region which is the surface of the base layer 42 below the gate 45. Although it is arranged on the side opposite to 41, the present invention arranges the emitter region on the collector layer side of the channel region, and the base connection layer in the emitter region on the collector layer side of the source layer. As described above, the hole current, which is minority carriers flowing from the collector layer to the emitter region, is extracted to the base connection layer, and the hole current flowing laterally in the base layer below the source layer, which causes latch-up, is generated. Is almost eliminated.

That is, in the present invention, as described in the preceding paragraph, for example, a p-type base layer is diffused on the surface of an n-type semiconductor region,
A p-type base connecting layer is diffused to one side so as to partially overlap with the base layer, and a p-type collector layer is diffused to the surface of the semiconductor region on the same one side so that both the base layer and the surface of the base connecting layer are diffused. By shallowly diffusing the n-type source layer in the range including the boundary and providing the gate so as to cover the surface of the base layer on the other side of the source layer from above, the base connection layer and the source are provided to the channel region below the gate. The emitter region consisting of layers is arranged on the same side as the collector layer.

As a result, the hole current from the collector layer passes through the base connection layer closest to the emitter terminal, and only a part of the hole current flows from the base layer to the lower side of the source layer via the base connection layer. Although it passes through, the lateral component under the source layer of the flow path is not in the base layer as in the past, but in the base connection layer where the impurity concentration is one digit or more higher and the specific resistance is lower than that in the base layer. Almost no hole injection into the pn junction of the
BT latch-up resistance can be improved.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view showing the structure and operation of the first embodiment of the present invention by a carrier flow path, FIG. 2 is a sectional view of a second embodiment in which a collector short layer of the present invention is provided, and FIG. 3 is a gate and a collector. FIG. 4 is a top view of a third embodiment of the present invention in which the layers and the layers are formed in a comb-shaped pattern intricately interdigitated with each other, and FIG. 4 is a fourth embodiment of the present invention in which a collector short layer is provided in a range surrounding the end of the gate pattern. It is a top view of an example.

FIG. 1A shows the IGBT 20 of the first embodiment in a cross section of its unit structure corresponding to FIG. IGBT 20 according to the invention
However, this unit structure is usually repeated multiple times in the left-right direction in the figure. The wafer 10 in which the IGBT 20 of this embodiment is built is formed by growing an epitaxial layer as an n-type semiconductor region 12 on the p-type semiconductor substrate 11 in a thickness of several tens of μm, similarly to the conventional case, and the semiconductor region 12 is 10 Ωcm. It is preferable that the resistance is relatively high. Since the IGBT 20 of this embodiment uses the buffer layer 21 on the collector side, the n-type buffer layer 21 is first formed from the left and right surfaces in the figure of the semiconductor region 12 at an impurity concentration of, for example, 10 ¹⁶ atoms / cm ^{3 in} the manufacturing process. A gate 22 of polycrystalline silicon having a film thickness of about 0.5 μm is disposed in the central portion of the semiconductor region 12 in the drawing with a depth of 5 μm, and a very thin gate oxide film 22a of about 0.1 μm is provided.

Next, the p-type base layer 23 is sunk from both sides of the gate 22 to the lower side thereof, for example, 10
Diffuse to a depth of 4 μm with an impurity concentration of ¹⁷ atoms / cm ³ .
Advantageously, the base layer 23 is formed by ion implantation of boron using the gate 22 as a part of the mask and its thermal diffusion. Next, the collector layer 24 and the base layer in the buffer layer 21
23 and a part of the base connection layer 25 which partially overlap each other are formed at a depth of about 2 μm with a high impurity concentration of 10 ¹⁸ to 10 ¹⁹ atoms / cm ³ of p-type by simultaneous diffusion of boron. Further, the n-type source layer 26 is formed on both sides of the gate 22 by arsenic ion implantation using the n-type source layer 26 as a part of the mask and the thermal diffusion thereof, as usual.
For example, a high impurity concentration of 10 ²⁰ atoms / cm ³ is formed to a depth of 0.2 μm, and a pattern including the boundary between the base layer 23 and the base connection layer 25 is formed as shown in the drawing. The surface portion of the base layer 23 below the gate 22 between the source layer 26 and the semiconductor region 12 serves as a channel region.

Since the fabrication of the semiconductor layer of the IGBT 20 is completed as described above, the aluminum electrode film 30 for the terminal is then provided at the important place as shown in the figure. Base connection layer 25 and source layer
The surface of the electrode 26 is short-circuited by the electrode film 30 as shown in the drawing to derive the emitter terminal E from them, and the electrode film 30 conductively contacts the gate 22 and the collector layer 24, respectively. By deriving, the drawing of this horizontal IGBT 20 is completed. The electrode film for the gate 22 is provided at a position other than the cross section shown. Further, other than the illustration, a usual insulating film or protective film is of course provided, but it is omitted from the drawing for simplification.

Next, the operation of the IGBT 20 of the first embodiment will be described with reference to FIG. 1 (b) which is an enlarged cross section of the right half of FIG. 1 (a). As can be seen from the above description, in the structure of the IGBT of the present invention, the emitter region including the base connection layer 25 and the source layer 26 from which the emitter terminal E is derived is formed in the channel region on the surface of the base layer 23 below the gate 22. Contrary to the conventional structure, it is provided on the same side as the collector layer 24. Therefore, when a positive potential is applied to the gate terminal G with respect to the emitter terminal E to make the n-type channel under the gate 22 conductive, electrons e which are majority carriers are emitted from the source layer 26 to this channel as shown in the figure. After entering into the semiconductor region 12 through the through, the current flows toward the collector layer 24 through a region deeper than the conventional one below the base layer 23.

In response to the inflow of the electrons e into the collector layer 24, conversely, holes which are minority carriers are changed to the semiconductor region.
In the present invention, as shown in the figure, the hole channel is drawn toward the channel of the electron e by the Coulomb force and passes through the inside of the semiconductor region 12 and the collector layer.
It is distributed between the surface flow path hs flowing along the surface of the semiconductor region 12 toward the base connection layer 25 located at the shortest distance from 24. The component of the hole current in the vicinity of the surface flow path hs is extracted from the semiconductor region 12 to the base connection layer 25, and the component in the vicinity of the internal flow path hi passes through the base layer 23 to the base connection layer 25.
In the beginning, when the IGBT 20 is turned on, the latter is slightly larger than the former, but in the fully on state where conductivity modulation is active, both are considered to be about the same.

In the present invention, the component of the hole current in the semiconductor region 12 in the vicinity of the surface flow path hs is directly extracted to the base connection layer 25 in this way, so that the risk of latch-up is reduced as compared with the conventional case. The remaining problem is the component of the hole current passing near the internal flow path hi, which is the base layer 23 and the base connection layer as shown in the figure.
Flows are distributed in the channel 25 between the flow channels indicated by hi1 and hi2, and the component near the flow channel hi2 has a lateral current component below the source layer 26. Since the lateral component flows to the lower side of the source layer 23 in the base connection layer 25, which has a much lower resistivity than the base layer 23, the risk of holes being injected into the pn junction with the source layer 23 is very small. . As described above, in the present invention, the component of the hole current in the vicinity of the surface flow path hs is extracted to the base connection layer 25, and the component in the vicinity of the internal flow path hi is below the source layer 26 and has a low specific resistance. Since it passes through the inside, the risk of latch-up is greatly reduced compared to the conventional case.

When the IGBT 20 is turned off, the potential of the gate terminal G is of course lost so that the channel region under the gate 22 is made non-conductive. Thereby, the semiconductor region 12 of the electron e is
The flow of electrons into the collector layer 24 is stopped and the electrons e remaining therein are absorbed by the collector layer 24. However, the density of the electrons e in the semiconductor region 12 decreases, and the hole current attracted by the Coulomb force to the electrons e decreases. The proportion of the component in the vicinity of the internal flow channel hi decreases and the proportion of the component in the vicinity of the surface flow channel hs increases, and the depletion layer extends into the semiconductor region 12 after the latter component is completely extracted to the base connection layer 25. The IGBT 20 is completely turned off. As can be seen from the above, in the IGBT 20 of the present invention, the risk of latch-up occurring during the off operation is small, and particularly the latch-up resistance against external noise that easily enters the emitter terminal during the off operation can be improved.

In the second embodiment shown in FIG. 2, the collector region has a collector short structure in order to increase the off-operation speed of the IGBT 20. N adjacent to the p-type collector layer 24 as shown
The collector short layer 27 having a shape is formed, and the surfaces of both layers are short-circuited by the electrode film 30 to derive the collector terminal C. Also,
In the illustrated example, as the wafer 20 for the IGBT 20, a substrate-bonding type wafer is used in which a substrate 11 and an n-type substrate for the semiconductor region 12 are bonded to each other via an oxide film 11a. Other structure is first
Same as the embodiment. In this embodiment, the electrons e, which are the majority carriers remaining inside the semiconductor region 12 during the off operation of the IGBT 20, are extracted to the n-type collector short layer 27 to reduce the amount of reverse injection of holes to reduce the off operation time. To shorten. The collector short layer 27 is advantageously provided by sandwiching the collector layer 24 from both sides as shown in the figure,
Moreover, the collector region may have a composite structure with the buffer layer 21 of the first embodiment.

FIG. 3 is a top view corresponding to the structure of the first embodiment of the third embodiment in which the planar patterns of the channel region and the collector region are formed in a comb-like shape in which they are intricately interdigitated with each other. The comb teeth are formed elongated in the left-right direction in the figure, but the central portion thereof is omitted in the figure. As shown in the figure, the gate 22 covering the channel region has a comb shape protruding from the left side to the right side, and the collector region including the buffer layer 21, the collector layer 24 and the electrode film 30 thereon has a comb shape protruding from the right side to the left side. The source layer is formed between each of these intricate comb teeth.
The exposed regions of the semiconductor region 12 and the emitter region including the base connection layer 25 and the electrode film 30 above the base connection layer 25 are arranged in a meandering pattern.

In the third embodiment, the gate 22 on the left side of FIG.
From the upper electrode film 30 to the gate terminal G, the collector layer 24 on the right side
The collector terminal C can be easily derived from the upper electrode film 30 as shown in the figure, and the emitter terminal E can also be easily derived from an appropriate portion of the electrode film 30 on the emitter region. In addition, this embodiment has an advantage that the chip area can be saved when the IGBT is built into the integrated circuit device. Of course, not limited to this, the planar pattern of the IGBT of the present invention is not as easy to derive the terminal as in this embodiment, but for example, the gate is formed in a long and narrow strip shape and is surrounded by the collector layer via the annular emitter region, Alternatively, the elongated strip-shaped collector layer can be formed so as to be surrounded by the gate via the annular emitter region.

FIG. 4 shows a fourth embodiment in a top view corresponding to the right side of FIG. However, this figure shows the pattern of the semiconductor layer from which the gate 22 and the electrode film 30 have been removed from FIG. The central portion of the figure is the semiconductor region 12 and the base layer 23 covered by the gate, and the right ends thereof are the end portions of the gate. There is a surface of the semiconductor region 12 and the emitter region composed of the source layer 26 and the base connection layer 25 so as to surround this end portion, and the buffer layer is provided outside thereof.
21 are spread. When the p-type collector layer 24 including the right end portion is diffused outside the buffer layer 21, the current of the holes h injected into the semiconductor region 12 from the buffer layer 21 is concentrated in the emitter region at a high density as shown in a fan shape in the figure. Then, latch-up easily occurs there. For this reason, in the fourth embodiment, the n-type collector short layer 28 is diffused in place of the p-type collector layer 24 in the range corresponding to the gate end, and the surfaces of both layers are electrode films for collector terminals. Short circuit. As a result, since there is no injection of holes in the range surrounding the gate end, conductivity modulation does not occur, and the current capacity of the IGBT is slightly reduced by that amount, but the weak point can be eliminated and the latch-up withstand capability can be improved.

Although the IGBT of the present invention described above is a lateral type, it can simultaneously provide a high withstand voltage of 200 V or more and a current capacity of several A or more, and of course can be easily incorporated in an integrated circuit device together with related circuits. Further, an IGBT having a low on-voltage of about 2 V and a short off-operation time of 2 to several μS can be obtained. It should be noted that the numerical values such as the conductivity type, the impurity concentration, the diffusion depth, etc., and the diffusion pattern of each semiconductor layer constituting the IGBT described in the above embodiments are merely examples, and the present invention is not limited to these Can be carried out in various modes depending on the necessity or case.

[0028]

As described above, in the IGBT of the present invention, the base layer of the other conductivity type is diffused from the surface of the semiconductor region of the one conductivity type, and the other conductivity type is provided on one side so as to partially overlap with the base layer. Of the base layer on the other side of the source layer to cover the surface of the base layer on the other side of the source layer from the upper side. The base connection layer and the source layer to the emitter terminal, after disposing a collector layer of the other conductivity type in the semiconductor region on one side of the base connection layer,
The following effects can be obtained by deriving the collector terminal from the collector layer and the gate terminal from the gate.

(A) By arranging the emitter region closer to the collector layer side than the channel region contrary to the conventional case, the hole current flowing from the collector layer side into the emitter region is directly drawn out to the base connection layer thereof, and the source layer is formed. The hole current flowing under the source layer is reduced, and the hole current component passing laterally under the source layer is allowed to flow only in the base connection layer having a low specific resistance to prevent injection of holes into the pn junction with the source layer. As a result, the latch-up resistance of the lateral IGBT can be improved.

(B) When the IGBT is turned off, most of the hole current flows to the surface of the semiconductor region and is quickly extracted to the base connection layer, so that the possibility of latch-up is greatly reduced, and especially in the off operation. As a result, it is possible to improve the latch-up resistance against external noise that easily enters from the emitter terminal. Further, since the hole current absorption speed is increased, the off-operation time of the IGBT can be shortened as compared with the conventional case.

The present invention is particularly effective when applied to a lateral IGBT incorporated in an integrated circuit device to improve its latch-up resistance and off-operation characteristics.

[Brief description of drawings]

FIG. 1 shows a structure of a first embodiment of an insulated gate bipolar transistor according to the present invention, FIG. 1 (a) is a sectional view showing the unit structure, and FIG. 1 (b) shows a flow path of carriers therein. FIG.

FIG. 2 is a sectional view of a second embodiment of the present invention in which a collector short layer is provided.

FIG. 3 is a top view of a third embodiment of the present invention in which a gate and a collector layer are formed in a comb-shaped pattern in which they are intricately interdigitated with each other.

FIG. 4 is a top view of a fourth embodiment of the present invention in which a collector short layer is provided in a range surrounding an end of a gate pattern.

FIG. 5 is a sectional view showing a unit structure of a conventional insulated gate bipolar transistor.

FIG. 6 is a cross-sectional view showing a channel of a carrier inside the conventional example of FIG.

[Explanation of Codes] 10 Wafer for Insulated Gate Bipolar Transistor 11 Wafer Substrate 12 Semiconductor Region for Insulating Gate Bipolar Transistor 20 Unit Structure of Insulated Gate Bipolar Transistor 21 Buffer Layer 22 Gate 23 Base Layer 24 Collector Layer 25 Base Connection Layer 26 source layer 27 collector short layer 28 collector short layer 30 terminal electrode film C collector terminal E emitter terminal e electrons as majority carriers h holes as minority carriers G gate terminal

Claims (5)

[Claims] 1. A semiconductor region of one conductivity type, a base layer of the other conductivity type diffused from the surface of the semiconductor region, and a base of the other conductivity type diffused to one side so as to partially overlap the base layer. Cover the connection layer, the base layer and the source layer of one conductivity type that is shallowly diffused within the range including the boundary between the base layer and the surface of the base connection layer, and the surface of the base layer on the other side of the source layer from above. And a collector layer of the other conductivity type diffused from the surface of the semiconductor region on one side of the base connecting layer, the base connecting layer and the source layer form an emitter terminal, and the collector layer forming a collector terminal. To
An insulated gate bipolar transistor, wherein each gate terminal is derived from the gate. 2. The transistor according to claim 1, wherein
An insulated gate bipolar transistor, characterized in that a collector short layer of one conductivity type is diffused from a surface of a semiconductor region adjacent to the collector layer, and a collector terminal is derived from the collector short layer. 3. The transistor according to claim 2, wherein
An insulated gate bipolar transistor, characterized in that a collector short layer is diffused within a range surrounding an end of a gate pattern. 4. The transistor according to claim 1, wherein
An insulated gate bipolar transistor, characterized in that the gate and the collector layer are arranged in a comb-shaped interdigitated pattern. 5. The transistor according to claim 1, wherein
An insulated gate bipolar transistor, characterized in that a base layer and a source layer are diffused by an ion implantation method in which impurities are introduced using a gate as a mask.