JP2005311212A - High breakdown strength insulated gate bipolar transistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an insulated gate bipolar transistor which can prevent the occurrence of latchup by increasing the lateral resistance of an n-type emitter layer in a small formation area to suppress an increase in voltage of the pn junction formed by the n-type emitter layer and a p-type base layer. <P>SOLUTION: The n-type emitter layer 4 consists of a highly doped diffusion layer 46 and a lightly doped diffusion layer 47. An emitter electrode is in contact with the highly doped diffusion layer 46, but not with the lightly doped diffusion layer 47. The end of the highly doped diffusion layer 46 is formed in a p-type contact layer 3. By not forming a channel in the end of the highly doped diffusion layer 46 to increase the lateral resistance of the n-type emitter layer 4, tolerance to latchup can be increased while forming the n-type emitter layer 4 in a small area. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an insulated gate bipolar transistor (hereinafter abbreviated as IGBT).

As is well known, IGBT is widely used in various fields as a power device having both high input impedance characteristics and low output impedance characteristics.
Initially, IGBTs have been actively developed as individual devices having a vertical structure as motor control devices in home appliances, transportation, and industrial fields. Recently, with the expansion of the so-called power IC market in which a control circuit for controlling the operation of the IGBT is mounted on the same chip as the IGBT, development of a lateral IGBT intended for mounting in a power IC has become active.
FIG. 11 is a cross-sectional view of a main part of a general high breakdown voltage n-channel type lateral IGBT. Note that a p-channel lateral IGBT is obtained by reversing the conductivity type. The figure also shows an electron current Ie and a hole current Ih for explaining the operation.
An n-type buffer layer 11 and a p-type base layer 2 are formed at a certain distance on the surface of an n-type semiconductor layer 1 such as an n-type semiconductor substrate or an n-type epitaxial layer. This distance is determined according to the breakdown voltage required for the element. Then, the collector layer 12 is formed in the n-type buffer layer 11 and the p-type contact layer 3 is formed in the p-type base layer 2, both of which are p-type diffusion layers having a high impurity concentration. An n-type emitter layer 4 is formed on the surface layer of the p-type base layer 2 as a diffusion layer having a high impurity concentration.

A gate insulating film 8 is formed of an oxide film across the surface of the n-type semiconductor layer 1 from the n-type emitter layer 4 through the p-type base layer 2. A gate electrode 7 is provided on the gate insulating film 8. From the end of the gate insulating film 8 to the collector region 14, the LOCOS oxide film 10 is formed of an oxide film thicker than the gate insulating film 8. Further, the gate electrode 7 is disposed so as to partially cover the LOCOS oxide film 10 as shown. The gate electrode 7 at this point functions as a field plate. In the figure, 17 is an n-type drift layer, 6a is an emitter electrode end, 9 is an emitter / gate region comprising the n-type emitter layer 4, emitter electrode 6 and gate electrode 7, and 14 is a p-type collector layer and collector electrode. This is the collector area.
A collector electrode 13 is connected to the p-type collector layer 12, and an emitter electrode 6 is connected to part of the p-type contact layer 3 and the n-type emitter layer 4. An emitter terminal E is connected to the emitter electrode 6, a collector terminal C is connected to the collector electrode 13, and a gate terminal G is connected to the gate electrode 7.

Next, the operation of the n-channel lateral IGBT will be described.
When a voltage equal to or higher than the threshold voltage is applied to the gate terminal G with respect to the emitter terminal E, a channel 5 is formed on the surface of the p-type base layer 2 immediately below the gate insulating film 8, and a majority carrier is formed from the n-type emitter layer 4 through this. Are injected into the n-type semiconductor layer 1 and an electron current Ie flows. Then, holes that are minority carriers are injected into the n-type semiconductor layer 1 through the n-type buffer layer 11 by the electron current flowing into the p-type collector layer 12, and the hole current Ih flows. Conductivity modulation. This is the ON operation of the IGBT.
On the other hand, when the gate voltage applied to the gate terminal G is lowered below the threshold voltage, the channel 5 immediately below the gate insulating film 8 disappears, and the injection of the electron current Ie is stopped. Thereby, IGBT can be turned off.

As described above, the IGBT is a device having a high-speed switching characteristic by MOS driving and a large current driving capability by bipolar operation, and exhibits excellent performance in various applications. However, the IGBT has a parasitic thyristor, and there is a big problem that a latch-up phenomenon in which the parasitic thyristor operates must be prevented.
FIG. 12 is a diagram for explaining the latch-up phenomenon of the n-channel lateral IGBT of FIG.
When the IGBT is turned on, holes which are minority carriers are injected from the collector region 14 into the n-type semiconductor layer 1 and a hole current Ih flows. This hole current Ih flows to the emitter terminal E through the path of the n-type semiconductor layer 1 -p-type base layer 2 -p-type contact layer 3 -emitter electrode 6. When the hole current Ih flows through the p-type base layer 2, a voltage drop is generated by the lateral resistance Rb of the p-type base layer 2 immediately below the n-type emitter layer 4, and this voltage drop causes the n-type emitter layer 4 and the p-type The pn junction of the base layer 2 is forward biased. When the forward bias voltage becomes 0.6 V or more, electrons are injected from the n-type emitter layer 4 to the p-type base layer 2, and the electron current ILe passes through the n-type emitter layer 4-p-type base layer and forms an n-type semiconductor. The parasitic thyristor composed of the p-type collector layer 12 / n-type semiconductor layer 1 / p-type base layer 2 / n-type emitter layer 4 is turned on. This is the latch-up phenomenon of the IGBT.

Once latch-up occurs, the current control function by the MOS gate is lost, and there is a risk that the device will be destroyed depending on the voltage application state of the device. Therefore, in the development of IGBT, regardless of the horizontal structure or the vertical structure, how to suppress the occurrence of this latch-up becomes a major issue.
In order to prevent the occurrence of latch-up, the voltage drop due to the lateral resistance Rb of the p-type base layer 2 is suppressed, so that the pn junction between the n-type emitter layer 4 and the p-type base layer 2 is not forward biased to 0.6V or more. It is necessary to. There is a method of optimizing the pattern of the n-type emitter layer 4 as a method for suppressing an increase in forward bias electricity at the pn junction between the n-type emitter layer 4 and the p-type base layer 2. This will be described below.
FIG. 13 is a diagram showing a planar pattern of a high breakdown voltage lateral IGBT. The n-type drift layer 17 is composed of straight portions and curved portions, and has a meandering pattern. The curved portion includes an emitter corner 15 in which the emitter / gate region 9 is surrounded by the drain region 14 and a collector corner 16 in which the drain region 14 is surrounded by the emitter / gate region 9. FIG. 11 is a cross-sectional view of the main part taken along the line XX.

FIG. 14 is a detailed enlarged view of part A of FIG. A p-type collector layer 12 is formed at the center, n-type buffer layers 11 are formed on both sides thereof, and an n-type drift layer 17, a p-type base layer 2, an n-type emitter layer 4, and a p-type contact layer are formed on the outer sides. 3 are formed. FIG. 11 is a cross-sectional view of the main part taken along the line XX in the figure. In this detailed enlarged view, the gate insulating film 8, the emitter electrode 6 and the gate electrode 7 are omitted, and a diffusion layer formed on the surface of the n-type semiconductor layer 1 is shown.
In this pattern, the n-type emitter layer 4 is formed in a stripe shape with a high concentration diffusion layer. The p-type contact layer 3 is formed up to the lower region of the n-type emitter layer 4 so as to overlap the n-type emitter layer 4. The pattern of the n-type emitter layer 4 is the most common. In this pattern, latch-up is likely to occur due to the increase of the forward bias voltage of the pn junction. Therefore, an example in which a latch-up countermeasure is taken is described in Patent Document 1, and a pattern in a case where it is applied to the horizontal IGBT of FIG. 14 will be described.

15 and 16 are configuration diagrams of a lateral IGBT with a latch-up countermeasure, FIG. 15 is a plan view of the main part, FIG. 16A is a cross-sectional view of the main part taken along line XX in FIG. (B) is the principal part sectional drawing cut | disconnected by the YY line | wire of FIG. 15, FIG.16 (c) is principal part sectional drawing cut | disconnected by the ZZ line | wire of FIG. FIG. 15 omits the gate oxide film 8, the emitter electrode 6, and the gate electrode 7, and shows only the diffusion layer formed on the surface of the n-type semiconductor layer 1.
In this lateral IGBT, the n-type emitter layer 4 is composed of a high-concentration diffusion layer 44 and a high-concentration diffusion layer 45, and the high-concentration diffusion layer 45 is divided and formed between the divided high-concentration diffusion layers 45. A layer 44 is formed. The emitter electrode 6 contacts the high concentration diffusion layer 44 and does not contact the high concentration diffusion layer 45. In addition, the planar shape of the p-type contact layer 3 is not a straight line but is interdigitated, and is formed so that the tip of the high-concentration diffusion layer 44 is surrounded by the tip of the p-type contact layer 3. The high concentration diffusion layer 44 and the high concentration diffusion layer 45 are formed under the same conditions.

With such a configuration, the p-type contact layer 3 between the high-concentration diffusion layer 44 and the base layer 2 has a high impurity concentration, so that the threshold voltage increases and a channel is not formed. On the other hand, the p-type base layer 45 that is in contact with the tip of the high-concentration diffusion layer 45 that is not in contact with the emitter electrode 6 has a low impurity concentration, so that a channel is formed.
The feature of this pattern is that the electron current flows only in the high-concentration diffusion layer 45 constituting the n-type emitter layer 4 not in contact with the emitter electrode 6, and at that time, the high-concentration diffusion layer is caused by the lateral resistance Re of the high-concentration diffusion layer 45. The potential at the tip of 45 is raised. Due to this potential increase, the increase in the pn junction voltage between the p-type base layer 2 and the n-type emitter layer 4 is suppressed, and latch-up is unlikely to occur. Further, since this pattern has an emitter follower structure, there is an effect of suppressing the saturation current of the IGBT.

As a different pattern of the n-type emitter layer 4, a method of forming the n-type emitter layer 4 in a strip shape in the p-type base layer 2 is described in Patent Document 2, which is applied to the lateral IGBT of FIG. The pattern will be described.
17 and 18 are configuration diagrams of a lateral IGBT with a latch-up measure, FIG. 17 is a plan view of the main part, FIG. 18A is a cross-sectional view of the main part taken along line XX of FIG. (B) is the principal part sectional drawing cut | disconnected by the YY line | wire of FIG. 17, FIG.18 (c) is principal part sectional drawing cut | disconnected by the ZZ line | wire of FIG. FIG. 17 omits the gate oxide film 8, the emitter electrode 6, and the gate electrode 7, and shows only the diffusion layer formed on the surface of the n-type semiconductor layer 1.
An n-type emitter layer 4 formed of a high-concentration diffusion layer 44 is formed in a strip shape in the p-type base layer 2, and the n-type emitter layer 4 is divided by the p-type contact layer 3. The interval between the divided n-type emitter layers 4 is adjusted according to the required characteristics. In this pattern, since the p-type contact layer 3 is arranged in parallel to the n-type emitter layer 4 with respect to the gate electrode 7, holes accumulated in the n-type drift layer are effectively extracted from the protruding p-type contact layer 3. And the occurrence of latch-up can be suppressed.

Further, in this pattern, since there is a region where the n-type emitter layer 4 is not formed, the lateral resistance Re of the n-type emitter layer 4 is somewhat increased, and the pn junction voltage between the p-type base layer 2 and the n-type emitter layer 4 is increased. The rise is suppressed, and the latch-up is less likely to occur. Further, since this pattern has an emitter follower structure, there is an effect of suppressing the saturation current of the IGBT.
For example, in Patent Document 3, a low-concentration diffusion layer is formed on the channel side of the n-type emitter layer in order to improve the avalanche resistance and the latch-up resistance without increasing the on-resistance of the insulated gate semiconductor device. It has been reported that parasitic transistors are difficult to turn on.
Japanese Patent Laid-Open No. 6-13620 FIG. JP-A-5-206469 JP, 8-186254, A FIG. 1, FIG.

The IGBT is a device having a high-speed switching characteristic by MOS driving and a large current driving capability by bipolar operation, and exhibits excellent performance in various applications. However, the IGBT has a parasitic thyristor, and there is a big problem that a latch-up phenomenon in which the parasitic thyristor operates must be prevented.
In order to prevent the occurrence of latch-up, as described above, the key is how to suppress the potential increase of the junction formed by the n-type emitter layer and the p-type base layer. For this reason, a method has been devised in which the pattern of the n-type emitter layer is devised to provide lateral resistance in this region. However, in these methods, since the n-type emitter layer is formed by high concentration diffusion, it is necessary to increase the non-contact area with the emitter electrode in order to increase the lateral resistance. This increases the pattern area of the n-type emitter layer, resulting in an increase in the element area.

  The object of the present invention is to solve the above-mentioned problems, increase the lateral resistance of the n-type emitter layer with a small formation area, and suppress the increase in the pn junction voltage between the n-type emitter layer and the p-type base layer. An object of the present invention is to provide a high breakdown voltage insulated gate bipolar transistor capable of preventing the occurrence of an increase.

  To achieve the above object, the second conductivity type base layer selectively formed on the surface layer of the first conductivity type semiconductor layer and the second conductivity type base layer selectively formed on the surface layer of the second conductivity type base layer. A first conductivity type emitter layer; and a gate electrode formed on the second conductivity type base layer sandwiched between the first conductivity type emitter layer and the first conductivity type semiconductor layer via a gate insulating film. In the insulated gate bipolar transistor, the first conductivity type emitter layer is formed of two diffusion layers, a high concentration diffusion layer and a low concentration diffusion layer having an impurity concentration lower than that of the high concentration diffusion layer, and the high concentration diffusion layer includes the diffusion layer. The emitter electrode is in contact, and the emitter electrode is not in contact with the low concentration diffusion layer. The high-concentration diffusion layer and the low-concentration diffusion layer have the gate electrode side end portions alternately arranged with respect to the gate electrode, and the base layer between the high-concentration diffusion layer and the semiconductor layer It is preferable to have a second conductivity type anti-inversion layer adjacent to the high-concentration diffusion layer on the surface layer.

And a second conductivity type contact layer selectively formed on the surface layer of the base layer adjacent to the emitter layer and on the opposite side of the gate electrode. It covers the bottom of the concentration diffusion layer and extends to the surface of the base layer between the emitter layer and the semiconductor layer.
A second conductivity type collector layer formed on the surface layer of the first conductivity type semiconductor layer away from the second conductivity type base layer; and a collector electrode in contact with the second conductivity type collector layer. Good.
A first conductivity type buffer layer formed on a surface layer of the first conductivity type semiconductor layer apart from the second conductivity type base layer; and the first conductivity type buffer layer formed on a surface layer of the first conductivity type buffer layer. It is good to have a 2 conductivity type collector layer and a collector electrode which contacts this 2nd conductivity type collector layer.

Moreover, it is good to have the 2nd conductivity type collector layer formed in the surface layer of the back surface side of the said 1st conductivity type semiconductor layer, and the collector electrode which contacts this 2nd conductivity type collector layer.
A first conductivity type buffer layer formed on a surface layer on a back surface side of the first conductivity type semiconductor layer; and a second conductivity type collector layer formed on the surface layer of the first conductivity type buffer layer; It is preferable to have a collector electrode in contact with the second conductivity type collector layer.
In order to prevent the latch-up of the IGBT, it is necessary to suppress an increase in the potential of the junction formed by the n-type emitter layer and the p-type base layer. As a method for realizing this, a method of increasing the resistance of the n-type emitter layer There is. Therefore, in the present invention, in order to increase the resistance of the n-type emitter layer, the n-type emitter layer is composed of two diffusion layers, a low concentration diffusion layer and a high concentration diffusion layer. That is, a high-concentration diffusion layer is formed in and near the portion in contact with the emitter electrode, and the other portions are formed of the low-concentration diffusion layer. As a result, the lateral resistance of the n-type emitter layer can be increased with a small formation area. In addition, since the portion where the latch-up occurs in the n-type emitter layer is formed by the low concentration diffusion layer, the voltage drop in this portion also increases as the MOS current increases. Therefore, an increase in junction potential between the n-type emitter layer and the p-type base contact layer can be effectively suppressed according to an increase in device current. As described above, it is possible to improve the latch-up resistance of the IGBT.

According to the present invention, in order to increase the resistance of the IGBT n-type emitter layer, the n-type emitter layer is composed of two diffusion layers, a high-concentration diffusion layer and a low-concentration diffusion layer having a lower impurity concentration than the high-concentration diffusion layer. The high-concentration diffusion layer is formed in and near the portion that contacts the emitter electrode, and the portion that does not contact the emitter electrode is formed by the low-concentration diffusion layer. A region where no channel is formed is formed between the high-concentration diffusion layer and the base layer by forming a high-concentration p-type contact layer therebetween and forming a p-type inversion prevention layer. As a result, an electron current flowing through the n-type emitter layer is allowed to flow through the low-concentration diffusion layer having a large lateral resistance, thereby suppressing an increase in the pn junction voltage between the n-type emitter layer and the p-type base layer and suppressing the occurrence of latch-up. .
With this configuration, the lateral resistance of the n-type emitter layer can be increased with a small formation area, and as a result, the latch-up resistance can be improved with a small formation area.

In the embodiment of the present invention, an n-type emitter layer is formed of a high-concentration diffusion layer and a low-concentration diffusion layer having a lower impurity concentration than the high-concentration diffusion layer, and the emitter electrode and the high-concentration diffusion layer are brought into contact with each other. The structure is not in contact with the layer. A p-type inversion prevention layer is formed between the gate electrode side tip of the high-concentration diffusion layer and the base layer, and a channel is not formed in the p-type inversion prevention layer, so that the lateral direction of the n-type emitter layer Increasing the resistance prevents latch-up from occurring. With this configuration, the latch-up resistance is improved while the n-type emitter layer is formed with a small area.
In the following description, the same reference numerals are assigned to the same parts as those of the conventional structure.

1 and 2 are configuration diagrams of a high breakdown voltage lateral IGBT according to a first embodiment of the present invention. FIG. 1 is a plan view of a main part, and FIG. 2 (a) is a cross-sectional view taken along line XX of FIG. FIG. 2B is a fragmentary sectional view taken along line YY of FIG. 1, FIG. 2C is a fragmentary sectional view taken along line Z1-Z1 of FIG. 1, and FIG. ) Is a cross-sectional view of the main part taken along the line Z2-Z2 of FIG. FIG. 1 corresponds to FIG.
An n-type buffer layer 11 having an impurity concentration of about 10 ¹³ cm ⁻² and an impurity concentration of 3 × 10 ¹³ cm are formed on the surface of an n-type semiconductor layer 1 having a specific resistance of about 5 to 10 Ω · cm, such as an n-type semiconductor substrate or an n-type epitaxial layer. A p-type base layer ^{2 of} about ⁻² is formed at a certain distance. This distance is determined according to the breakdown voltage required for the element. Then, a collector layer 12 having an impurity concentration of about 3 × 10 ¹⁵ cm ⁻² is formed in the n-type buffer layer 11, a p-type contact layer 3 is formed in the p-type base layer 2, and both p-type diffusions having a high impurity concentration. Form with layers. On the surface layer of the p-type base layer 2, the n-type emitter layer 4 is formed by a high-concentration diffusion layer 46 and a low-concentration diffusion layer 47 having a lower impurity concentration than the high-concentration diffusion layer 46. The high concentration diffusion layer 46 is formed with an impurity concentration of about 5 × 10 ¹⁵ cm ⁻² , and the low concentration diffusion layer 47 is formed with an impurity concentration of about 10 ¹³ cm ⁻² . The low-concentration diffusion layer 47 is divided, and a high-concentration diffusion layer 46 is formed by being sandwiched between the divided low-concentration diffusion layers 47, and the tip of the high-concentration diffusion layer 46 on the gate electrode side is a p-type contact layer. 3 is formed. Since the p-type contact layer 3 has a higher impurity concentration than the p-type base layer 2 and is not inverted even when a gate voltage is applied, the p-type contact layer 3 is formed between the high-concentration diffusion layer 46 and the p-type base layer 2. The p-type contact layer 3 serves as an anti-inversion layer. A side surface of the high concentration diffusion layer 46 adjacent to the low concentration diffusion layer 47 is formed so as to be connected to the low concentration diffusion layer 47.

A gate insulating film 8 is formed of an oxide film across the surface of the n-type semiconductor layer 1 from the n-type emitter layer 4 through the p-type base layer 2. A gate electrode 7 is provided on the gate insulating film 8. From the end of the gate insulating film 8 to the collector region 14, the LOCOS oxide film 10 is formed of an oxide film thicker than the gate insulating film 8. Further, the gate electrode 7 is disposed so as to partially cover the LOCOS oxide film 10 as shown. The gate electrode 7 at this point functions as a field plate.
An emitter electrode 6 is connected to a part of the p-type contact layer 3 and the n-type emitter layer 4, and a collector electrode 13 is connected to the p-type collector layer 12. An emitter terminal E is connected to the emitter electrode 6, a collector terminal C is connected to the collector electrode 13, and a gate terminal G is connected to the gate electrode 7.

Note that the high-concentration diffusion layers 46 on the emitter electrode 6 side opposite to the channel forming portion 5 may be connected. The n-type buffer layer 11 may not be formed when the breakdown voltage is relatively low. In the figure, 17 is an n-type drift layer, and 6a is an emitter electrode end.
FIGS. 3 and 4 are diagrams for explaining a state of suppressing the occurrence of latch-up in the high breakdown voltage lateral IGBT of FIGS. 1 and 2, and FIG. 3 is a cross-sectional view of a principal part taken along line aa in FIG. FIG. 4 is an enlarged view of the n-type emitter layer, the p-type contact layer, and the p-type base layer of FIG.
3 differs from FIG. 11 in that the n-type emitter layer 4 is formed of two diffusion layers, a high concentration diffusion layer 46 and a low concentration diffusion layer 47. The hole current Ih serving as a latch-up trigger current flows through the lateral resistance Rb of the p-type base layer 2 and flows into the emitter electrode 6 via the p-type contact layer 3.

Since a part of the n-type emitter layer 4 is formed of the low-concentration diffusion layer 47, the lateral resistance Re in this region is only the high-concentration diffusion layers 44 and 45 as in the prior art shown in FIGS. Larger than when formed with Therefore, the electron current Ie flows from the emitter electrode 6 to the channel 5 through the low concentration diffusion layer 47 constituting the n-type emitter layer 4, thereby increasing the voltage drop due to the lateral resistance Re of the low concentration diffusion layer 47. . As a result, the voltage drop due to the lateral resistance Rb of the p-type base layer 2 and the hole current Ih is canceled out, and the increase in the pn junction voltage between the n-type emitter layer 4 and the p-type base layer 2 can be suppressed. It becomes possible.
As compared with the case where the n-type emitter layer 4 is formed only by the high-concentration diffusion layers 44 and 45 as in the prior art, the voltage drop in the n-type emitter layer 4 can be further increased, and the lateral resistance There is no need to increase the pattern area for increasing Re. This brings about the effect which suppresses the increase in an element area.

The ion implantation process for forming the low concentration diffusion layer 47 may be introduced immediately before the ion implantation process for forming the high concentration diffusion layer 46. The heat treatment step may be the same as that of the high concentration diffusion layer 46.
When the present invention is applied to a high breakdown voltage lateral IGBT applied to a power IC, the low-concentration diffusion layer 47 can be formed simultaneously with the formation of a CMOS LDD (Light Doped Drain) layer constituting the control circuit. .
As described above, the n-type emitter layer is formed of the high-concentration diffusion layer 46 and the low-concentration diffusion layer 47 in the pattern as shown in FIG. 1, thereby increasing the lateral resistance Re of the n-type emitter layer 4 and increasing the pattern area. Can be enlarged without Further, the voltage drop of the n-type emitter layer 4 can be increased more effectively with the increase of the MOS current, and the latch-up of the element can be prevented.

5 and 6 are configuration diagrams of a high breakdown voltage lateral IGBT according to a second embodiment of the present invention. FIG. 5 is a plan view of a main part, and FIG. 6 (a) is a cross-sectional view taken along line XX of FIG. FIG. 6B is a fragmentary sectional view taken along line YY of FIG. 5, FIG. 6C is a fragmentary sectional view taken along line Z1-Z1 of FIG. 5, and FIG. ) Is a cross-sectional view of the main part taken along the line Z2-Z2 of FIG. FIG. 5 corresponds to FIG.
The difference from FIG. 1 is that the p-type contact layer 3 is not intricate and the tip of the high concentration diffusion layer 46 constituting the n-type emitter layer 4 is formed in the p-type inversion prevention layer 33. is there.
In this case as well, since no channel is formed in the p-type inversion preventing layer 33 at the tip of the high concentration diffusion layer 46, the electron current Ie flows to the channel 5 through the low concentration diffusion layer 47, so that it is the same as in the first embodiment. The effect is obtained.

  In the case of FIG. 1, since the p-type contact layer 3 is complicated, the high concentration diffusion layer 46 and the low concentration diffusion layer 47 may not contact each other due to misalignment of the mask. In such a case, the side surface of the high concentration diffusion layer 46 and the low concentration diffusion layer 47 can be reliably brought into contact with each other.

7 and 8 are configuration diagrams of a high breakdown voltage lateral IGBT according to a third embodiment of the present invention. FIG. 7 is a plan view of a main part, and FIG. 8 (a) is a cross-sectional view taken along line XX of FIG. FIG. 8B is a fragmentary sectional view taken along line YY of FIG. 7, FIG. 8C is a fragmentary sectional view taken along line Z1-Z1 of FIG. 7, and FIG. ) Is a sectional view of the principal part taken along the line Z2-Z2 of FIG. FIG. 7 corresponds to FIG.
The difference from FIG. 1 is that the high concentration diffusion layer 46 is recessed from the low concentration diffusion layer 47. In this case, the same effect as that of the first embodiment can be obtained.
Compared with FIG. 1, the length of the tip is increased and the on-resistance is somewhat reduced by the amount that the corner of the tip of the low-concentration diffusion layer 47 is not hidden by the p-type contact layer 3.

FIGS. 9 and 10 are configuration diagrams of a high breakdown voltage vertical IGBT according to a fourth embodiment of the present invention. FIG. 9 is a plan view of a main part, and FIG. 10 (a) is a cross-sectional view taken along line XX of FIG. FIG. 10B is a partial cross-sectional view taken along line YY in FIG. 9. The main part sectional view cut along the Z1-Z1 line in FIG. 9 and the main part sectional view cut along the Z2-Z2 line in FIG. 9 are the same as FIG. 2 (c) and FIG. 2 (d), respectively. The same effect as that of the horizontal IGBT can be obtained for the vertical IGBT.
In the case of the vertical IGBT, as in the case of the horizontal IGBT, the n-type buffer layer may not be formed if the breakdown voltage is relatively low. In this embodiment, the first embodiment is applied to a high breakdown voltage vertical IGBT. However, the second and third embodiments can also be applied to a high breakdown voltage vertical IGBT.

The principal part top view of the high voltage | pressure-resistant lateral IGBT of 1st Example of this invention (A) is a cross-sectional view of the main part cut along line XX in FIG. 1, (b) is a cross-sectional view of the main part cut along line Y-Y in FIG. 1, and (c) is a Z1-Z1 line in FIG. Cutaway main part sectional view, (d) is a sectional view taken along the line Z2-Z2 of FIG. FIG. 2 is a diagram for explaining a state of suppressing the occurrence of latch-up in a high breakdown voltage lateral IGBT, and is a cross-sectional view of a main part cut along a line aa in FIG. Enlarged view of the n-type emitter layer, p-type contact layer and p-type base layer of FIG. The principal part top view of the high voltage | pressure-resistant lateral IGBT of 2nd Example of this invention 5A is a cross-sectional view of main parts cut along line XX in FIG. 5, FIG. 5B is a cross-sectional view of main parts cut along line YY in FIG. 5, and FIG. Cutaway principal part sectional view, (d) is a principal part sectional view cut along line Z2-Z2 of FIG. The principal part top view of the high voltage | pressure-resistant lateral IGBT of 3rd Example of this invention 7A is a cross-sectional view of main parts cut along line XX in FIG. 7, FIG. 7B is a cross-sectional view of main parts cut along line YY in FIG. 7, and FIG. Cutaway principal part sectional view, (d) is a principal part sectional view cut along line Z2-Z2 of FIG. The principal part top view of the high voltage | pressure-resistant vertical IGBT of 4th Example of this invention 9A is a cross-sectional view of main parts cut along line XX in FIG. 9, and FIG. 9B is a cross-sectional view of main parts cut along line Y-Y in FIG. Cross section of the main part of a general high breakdown voltage n-channel lateral IGBT The figure explaining the latch-up phenomenon of the n-channel type lateral IGBT of FIG. The figure which shows the plane pattern of a high voltage | pressure-resistant horizontal type IGBT Detailed enlarged view of part A in FIG. Plan view of main part of horizontal IGBT with latch-up countermeasure (A) is a cross-sectional view of the main part cut along the line XX in FIG. 15, (b) is a cross-sectional view of the main part cut along the line YY in FIG. 15, and (c) is a ZZ line in FIG. Cutaway main part sectional view Plan view of main part of horizontal IGBT with latch-up countermeasure 17A is a cross-sectional view of main parts cut along line XX in FIG. 17, FIG. 17B is a cross-sectional view of main parts cut along line YY in FIG. 17, and FIG. Cutaway main part sectional view

Explanation of symbols

1 n-type semiconductor layer 2 p-type base layer 3 p-type contact layer 3a p-type contact layer end 4 n-type emitter layer 5 channel / channel formation place 6 emitter electrode 6a emitter electrode end 7 gate electrode 8 gate insulating film 10 LOCOS oxide film 11 n-type buffer layer 12 p-type collector layer 13 collector electrode 17 n-type drift layer 33 p-type inversion prevention layer 46 high-concentration diffusion layer 47 low-concentration diffusion layer E emitter terminal G gate terminal C collector terminal Ie electron current ILe electron current Ih Hole current Rb lateral resistance (p-type base layer)
Re lateral resistance (n-type emitter layer)

Claims (7)

A second conductivity type base layer selectively formed on the surface layer of the first conductivity type semiconductor layer; a first conductivity type emitter layer selectively formed on the surface layer of the second conductivity type base layer; In an insulated gate bipolar transistor having a first conductivity type emitter layer and a gate electrode formed on the second conductivity type base layer sandwiched between the first conductivity type semiconductor layers via a gate insulation film,
The first conductivity type emitter layer is formed of two diffusion layers, a high concentration diffusion layer and a low concentration diffusion layer having a lower impurity concentration than the high concentration diffusion layer, and the emitter electrode is in contact with the high concentration diffusion layer, An insulated gate bipolar transistor, wherein the emitter electrode is not in contact with the low concentration diffusion layer. The high-concentration diffusion layer and the low-concentration diffusion layer have the gate electrode side end portions alternately arranged with respect to the gate electrode, and the surface of the base layer between the high-concentration diffusion layer and the semiconductor layer 2. The insulated gate bipolar transistor according to claim 1, further comprising a second conductivity type inversion prevention layer adjacent to the high concentration diffusion layer. A second conductivity type contact layer selectively formed on a surface layer of the base layer adjacent to the emitter layer and opposite to the gate electrode;
3. The anti-inversion layer, wherein the contact layer covers the bottom of the high-concentration diffusion layer and extends on the surface of the base layer between the emitter layer and the semiconductor layer. An insulated gate bipolar transistor as described in 1. A second conductivity type collector layer formed on the surface layer of the first conductivity type semiconductor layer apart from the second conductivity type base layer, and a collector electrode in contact with the second conductivity type collector layer. The insulated gate bipolar transistor according to any one of claims 1 to 3. A first conductivity type buffer layer formed on the surface layer of the first conductivity type semiconductor layer apart from the second conductivity type base layer; and the second conductivity type formed on the surface layer of the first conductivity type buffer layer. 5. The insulated gate bipolar transistor according to claim 4, further comprising a collector layer and a collector electrode in contact with the second conductivity type collector layer. 4. A second conductivity type collector layer formed on a surface layer on the back surface side of the first conductivity type semiconductor layer, and a collector electrode in contact with the second conductivity type collector layer. An insulated gate bipolar transistor according to any one of the above. A first conductivity type buffer layer formed on a surface layer on a back surface side of the first conductivity type semiconductor layer; a second conductivity type collector layer formed on a surface layer of the first conductivity type buffer layer; 7. The insulated gate bipolar transistor according to claim 6, further comprising a collector electrode in contact with the two-conductivity collector layer.

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