JP2949001B2 - Gate insulated semiconductor device and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to, for example, an insulated gate bipolar transistor.
The present invention relates to a gate-insulated semiconductor device such as an IGBT (hereinafter abbreviated as IGBT) and a method of manufacturing the same, and particularly to improvement of short-circuit withstand capability.

[0002]

2. Description of the Related Art FIG. 40 is a plan view showing the structure of a conventional N-channel IGBT 100. Generally, the IGBT 100 has a structure in which a number of IGBT elements (hereinafter, referred to as IGBT unit cells) 110 are connected in parallel. FIG. 40 shows an emitter electrode 7 and an oxide film 8, which will be described later, removed. FIG. 40 also shows the shapes of various mask patterns used in the manufacturing process of the IGBT 100. FIG. 41 is a cross-sectional view of one IGBT unit cell 110 taken along line AA shown in FIG. FIG. 42 shows one IGBT unit cell 110 along the line BB shown in FIG.
FIG. FIG. 41 shows an IGBT unit cell 11.
A circuit diagram showing an equivalent circuit of 0 is also shown at the same time.

As shown in FIGS. 41 and 42, this IG
BT100 is a p-type collector layer 1 made of a p-type semiconductor substrate.
An n-type epitaxial layer 2 is formed on the semiconductor substrate 1
20. A p-type base region 3 is formed by selectively diffusing a p-type impurity into the upper main surface of the n-type epitaxial layer 2, that is, a partial region of the upper main surface of the semiconductor substrate 120. Further, an n-type emitter region 4 is formed in a partial region of the upper main surface of the semiconductor substrate 120 by selectively diffusing an n-type impurity. A gate insulating film 5 is formed on an upper surface of p-type base region 3 sandwiched between an upper surface of n-type epitaxial layer 2 and an upper main surface of n-type emitter region 4. Gate insulating film 5 is formed on the upper surface of n-type epitaxial layer 2 so as to be integrated between adjacent IGBT unit cells 110. On the gate insulating film 5, a gate electrode 6 made of, for example, polycrystalline silicon (hereinafter referred to as polysilicon) is formed. An emitter electrode 7 made of, for example, aluminum is formed so as to be electrically connected to both the p-type base region 3 and the n-type emitter region 4. The gate electrode 6 and the emitter electrode 7 are mutually an interlayer insulating film,
For example, all IGBTs insulated through oxide film 8
It has a structure in which the unit cells 110 are electrically connected commonly to each other. In the p-type base region 3, a high-concentration p-type semiconductor region 31 in which p-type impurities are diffused at a high concentration is formed so as to surround the n-type emitter region 4. On the lower main surface of the p-type collector layer 1, a collector electrode 9 made of metal is formed integrally through all the IGBT unit cells 110.

[0004] As shown in FIG.
Area with a relatively large width as viewed from above (near the line AA)
And a relatively narrow area (near the BB line). FIG.
The mask pattern 51 used when forming the gate electrode 6 in the manufacturing process, the high-concentration p-type semiconductor region 3
1 are shown by dotted lines, and a mask pattern 52 used when forming the n-type emitter region 4 is shown by dotted lines.

<Operation of Conventional Apparatus> Referring to FIG.
The operation of the GBT 100 will be described. The IGBT unit cell 110 includes an insulated gate field effect transistor (hereinafter, referred to as a MOSFET) MOS, a pnp bipolar transistor Tr1, an npn bipolar transistor Tr2, and a resistor Rb as shown in the equivalent circuit diagram in FIG. , Are equivalently formed and are connected to each other.

When a gate voltage V _GE is applied between the gate electrode 6 and the emitter electrode 7 with the collector voltage V _CE applied between the collector electrode 9 and the emitter electrode 7, the n-type emitter region 4 and the n-type epitaxial The upper surface of the p-type base region 3 between the layers 2 is inverted from a p-type semiconductor to an n-type semiconductor, an n-type channel is formed, and the n-type epitaxial layer 2 corresponding to the drain of the MOS and the n-type corresponding to the source The conduction between the n-type emitter regions 4 becomes conductive, and an electron current flows from the n-type emitter region 4 into the n-type epitaxial layer 2 through the n-type channel. This electron current becomes the base current of Tr1. At this time, holes are injected from the p-type collector layer 1 to the n-type epitaxial layer 2, a part of the injected holes are recombined with carrier electrons of the n-type epitaxial layer 2, and the rest is p-type base region 3. , And flows into the emitter electrode 7 as a hole current.
The GBT 100 is in a conductive state (ON), that is, a state in which the collector electrode 9 and the emitter electrode 7 are conductive.

The IGBT 100 is similar to the MOSFET,
Since it is a voltage controlled transistor having an insulated gate (MOS gate), it has an advantage that a drive circuit can be simplified compared to a bipolar transistor, and has a lower collector / emitter than a MOSFET. There is an advantage that an inter-saturation voltage (ON voltage) can be realized. The latter advantage is that, as described above, the holes are injected from the p-type collector layer 1 into the n-type epitaxial layer 2 to cause conductivity modulation, thereby effectively reducing the resistance of the n-type epitaxial layer 2. Brought by.

Applying a zero voltage to the gate voltage V _GE , ie, applying a zero bias or applying a negative voltage,
That is, by setting the negative bias, the MOS is cut off, and the electron current stops flowing. As a result, the IGB
T100 is turned off (off). However, at the time when the transition from on to off is started, the accumulated holes remain in the n-type epitaxial layer 2, and the accumulated holes during the transition from on to off disappear at a certain rate. It takes time (turn-off time), during which the hole current continues to flow while attenuating. The accumulated holes are effective for realizing a low saturation voltage when the IGBT 100 is on, but when turning off (turning off), it causes a longer turn-off time as described above. The optimization of the injection amount or the lifetime is performed.

The IGBT unit cell 110 has a parasitic thyristor formed from four layers of an n-type emitter region 4, a p-type base region 3, an n-type epitaxial layer 2, and a p-type collector layer 1. . When the parasitic thyristor is turned on during the operation of the IGBT 100 (parasitic effect), the original function of the IGBT 100 may be lost. Therefore, it is necessary to suppress this parasitic effect. One effective method for suppressing the parasitic effect is to lower the lateral resistance Rb of the p-type base region 3 immediately below the n-type emitter region 4. Conventionally,
As shown in FIGS. 41 and 42 to lower Rb,
Immediately below the n-type emitter region 4, a high-concentration p-type semiconductor region 31
(For example, disclosed in Japanese Patent Application Laid-Open No. 60-196974). As shown in FIGS. 41 and 42, the high-concentration p-type semiconductor region 31 is formed inside the n-type emitter region 4 for the purpose of not affecting the gate threshold voltage. That is, the high-concentration p-type semiconductor region 31 is formed so that the high-concentration p-type semiconductor region 31 itself does not constitute a part of the n-channel formed in the p-type base region 3 when the gate voltage _VGE is applied. You.

[0010]

<Problems of Conventional Device> The IGBT 100 is often used mainly for inverter devices and the like. Therefore, when the inverter device is short-circuited, that is, when the IGBT 100 is applied with a short-circuit voltage. It is required that the IGBT 100 not be destroyed even when the IGBT 100 is turned on in a state where the IGBT 100 is turned on. The short-circuit strength (short-circuit tolerance) of the IGBT 100 is determined by a product of a short-circuit voltage, a short-circuit current, and a short-circuit time. Particularly in the IGBT 100 having a small chip area, the short-circuit withstand capability becomes severe.

The short circuit voltage and short circuit time are as follows:
It is determined by the conditions for using the IGBT 100, for example, the operating conditions of the inverter. When the IGBT 100 is short-circuited, it enters a saturation state.
This is nothing but the saturation current I _CE (sat) of the BT100. Therefore, by setting the saturation current I _CE (sat) of the IGBT 100 low, the short-circuit withstand capability can be improved. The saturation current I _CE (sat) is determined by Equation 1.

[0012]

(Equation 1)

On the other hand, in order to reduce the loss when the IGBT 100 is applied as a switching element to an inverter or the like, it is necessary to reduce the collector-emitter saturation voltage V _CE (sat). To reduce the collector-emitter saturation voltage V _CE (sat), the IGBT unit cell 1
The portion corresponding to the MOSFET in FIG.
One effective method is to improve the electrical characteristics of OS) and reduce the voltage drop when the MOS is turned on. For example, in the diffusion step of forming the p-type base region 3, the channel length L of the MOS is shortened by making the diffusion shallow, or the width of the p-type base region 3 (see the drawing of the p-type base region 3 in FIGS. 41 and 42). IGB
There is a method of increasing the total sum of the channel width W of the entire IGBT 100 by miniaturizing and increasing the density of the T unit cell 110.

However, to reduce the channel length L or increase the channel width W in order to reduce the collector-emitter saturation voltage V _CE (sat), as can be understood from Eq. In order to increase the saturation current I _CE (sat), the parasitic thyristor causes latch-up and breaks down, or even if latch-up does not occur, the product of the voltage and current at the time of short-circuit increases, and the short-circuit withstand capability Causes a drop in Thus, the conventional IGBT 1
In the case of 00, there is a problem that a loss as a switching element is low and characteristics with high short-circuit withstand capability cannot be obtained.

<Object of the present invention> The present invention has been made to solve the above-mentioned problems, and has a high short-circuit withstand capability even when the loss is set low, and a gate with improved latch-up withstand capability. It is an object of the present invention to obtain an insulated semiconductor device, and further to obtain a gate insulated semiconductor device capable of reducing a loss accompanying a switching operation. It is another object of the present invention to provide a manufacturing method suitable for this device.

[0016]

Means for Solving the Problems Claim 1 according to the present invention.
The gate-insulated semiconductor devices described in (a) to (a) below
(E). That is, (a) the upper main surface and the lower main surface
Defined by the semiconductor substrate comprises the following from (a-1) (a- 4): (a-1) is exposed on said main surface of said semiconductor substrate, a first semiconductor region of a first conductivity type; ( a-2) a second semiconductor region of a second conductivity type selectively formed on the upper surface of the first semiconductor region and selectively exposed on the upper main surface of the semiconductor substrate; (a-3) The semiconductor substrate is selectively formed on an upper surface portion of the second semiconductor region.
On the upper main surface, inside the peripheral portion of the exposed surface of the second semiconductor region, parallel and strip-shaped apart from each other.
A pair of first portion extend, each of the pair of the first portion
(A-4) a second semiconductor region of the first conductivity type having a second portion protruding toward the other from each other ;
A conductivity type, a second concentration of impurities for forming the conductivity type is higher than the second semiconductor regions selectively formed in said upper surface portion of the semiconductor body so as to encompass said third semiconductor region A region sandwiched between the pair of first portions.
In the central area is a region excluding said second portion in the band, while exposed to the upper main surface of said semiconductor body,
Each of the first portions is directed outwardly of the pair of first portions.
Area protruding from each other, and the protruding position is the second area.
A fourth semiconductor region exposed on the upper main surface of the semiconductor substrate in an outer area matching the projecting position of the portion ; (b)
An insulating layer selectively formed on the upper main surface of the semiconductor substrate and having an opening on a predetermined region covering at least a part of the second part and at least a part of the central area; c) a control electrode layer buried in the insulating layer and facing a section between the pair of first portions and the exposed surface of the first semiconductor region; and (d) formed in the opening. A first main electrode layer electrically connected to a portion of the upper main surface of the semiconductor substrate exposed to the opening;
(E) wherein the lower main surface and the second main electrode layer electrically connected to the semiconductor substrate.

According to a second aspect of the present invention, in the gate insulating type semiconductor device according to the first aspect, the second portion is the pair of first portions.
Are connected in a cross-linking manner, whereby the pair of first
The part and the second part are formed in a ladder-like pattern as a whole.
It is in a state.

According to a third aspect of the present invention, in the gate insulating semiconductor device according to the first or second aspect , the area of the opening is smaller than the area of the opening.
Of the third semiconductor region exposed in the opening,
The ratio of the required area is 50% or less .

[0019] In an insulated gate semiconductor equipment according to claim 4 according to the present invention, the gate insulating type half according to claim 3
In the conductor device, the ratio is 5% to 25%.
You .

According to a fifth aspect of the present invention, there is provided the gate-insulated semiconductor device according to any one of the first to fourth aspects.
5. The semiconductor device according to claim 1, wherein
Outside the pair of first portions on the upper main surface of the body substrate
Occupied by the area adjacent to the outer area in the side margin
Is 20% or more .

According to a sixth aspect of the present invention, there is provided the gate-insulated semiconductor device according to any one of the first to fifth aspects.
In an insulated gate semiconductor device according to either the third
To the value of the sheet resistance of the semiconductor region is 40Ω / □ 1 to 5
0Ω / □.

According to a seventh aspect of the present invention, there is provided a gate insulating semiconductor device according to any one of the first to sixth aspects.
In the gate insulating semiconductor device according to any one of the above,
The sheet resistance of the electrode layer is 250Ω / □ or less .

According to a eighth aspect of the present invention, there is provided a method of manufacturing a gate insulating semiconductor device , comprising the steps of :
( O ). That is, (a) the upper main surface and the lower main surface
A first half of a first conductivity type defined and exposed on said upper main surface.
Obtaining a semiconductor substrate provided with a conductive region;
Forming an insulating film on the upper main surface of the conductor base; (c)
A strip-shaped first opening is selectively provided on the insulating film;
Forming a control electrode layer; (d) forming the first opening
An impurity of the second conductivity type on the upper main surface of the semiconductor substrate via
To form a second semiconductor region of the second conductivity type.
(E) the step introduced in the step (d).
Selectively diffusing a pure substance into the first semiconductor region;
Thereby, the second semiconductor region is connected to the control electrode layer.
(F) only a part of the open end is
A second opening selectively located within the first opening is provided.
And a shielding film for preventing the introduction of impurities is formed in the first opening.
Provided on the insulating film and the control electrode layer in the portion
Step; (g) the semiconductor substrate through the second opening
The upper main surface of
Select impurities of the second conductivity type higher than the concentration of the pure substance
By introducing the third semiconductor of the second conductivity type
Forming a region; (h) removing the shielding film
(I) removing the impurities introduced in the step (g)
Selectively diffusing into the semiconductor substrate, thereby
While maintaining a higher impurity concentration than the second semiconductor region.
A part of the third semiconductor region, the control electrode layer
And spread it out so that it extends below
In the upper main surface of the body substrate, directly below the first opening portion
Exposing to a region including the corresponding region; (j)
The first opening of the upper main surface of the semiconductor substrate;
In the area just below
And a pair of first portions extending in a band shape, and the pair of first portions.
Part protruding from each part toward the other
Therefore, the projecting position is controlled by the third semiconductor region.
A second portion aligned with a position protruding below the electrode layer
Wherein the gap present below the first opening is
By selectively removing the peripheral membrane, the pair of first
Upper part of the semiconductor substrate in the part and the second part.
A region exposed between the pair of first portions exposing a surface
In the central area, which is the area excluding the second part,
Leaving the insulating film; (k) before remaining in the central area
The insulating film and the insulating film present below the control electrode layer;
Is used as a mask, and a second
The third semiconductor is selectively introduced by introducing impurities of one conductivity type;
Forming a fourth semiconductor region of the first conductivity type in the body region
(L) removing the insulating film remaining in the central area.
(M) removing the upper main surface of the semiconductor substrate.
And at least a part of the second portion and the central area
A third opening over at least a portion of
Forming an insulating layer covering side and top surfaces of the control electrode layer
(N) the front of the upper main surface of the semiconductor substrate
A first portion electrically connected to a portion exposed to the third opening;
Providing the main electrode layer in the third opening;
(O) electrically connecting to the lower main surface of the semiconductor substrate;
Forming a second main electrode layer on a lower main surface of the semiconductor substrate;
Process .

According to a ninth aspect of the present invention, there is provided a method of manufacturing a gate-insulated semiconductor device according to the eighth aspect.
In the method of manufacturing an insulated semiconductor device, the second part
Are connected in a cross-linked manner between the pair of first portions.
Thus, the pair of the first portion and the second portion are entirely
And has a ladder-like pattern shape .

According to a tenth aspect of the present invention, in a method of manufacturing a gate-insulated semiconductor device , the eighth aspect or the fifth aspect of the present invention provides a method of manufacturing a gate-insulated semiconductor device.
Item 10. In the method for manufacturing a gate insulating semiconductor device according to Item 9, the third opening with respect to the area of the third opening.
The ratio of the area occupied by the fourth semiconductor region exposed to the portion is
In the step (j), the content is set to 50% or less.
Selectively removing the insulating film; and removing the insulating film in the step (m).
An edge layer is formed .

According to a method of manufacturing a gate-insulated semiconductor device according to claim 11 of the present invention, the method according to claim 10 is provided.
In the method for manufacturing a gate insulating semiconductor device , the ratio
Is adjusted to 5% to 25% in the step (j).
Selectively removing the insulating film in the step (m).
And forming the insulating layer .

According to the method of manufacturing a gate insulating semiconductor device according to the twelfth aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to the eighth aspect.
Item 12. The gate insulating semiconductor device according to any one of items 11
The method of manufacturing a semiconductor substrate,
And the third outer part of the pair of first portions is located within the outer edge.
Where the semiconductor region protrudes below the control electrode layer
So that the ratio of adjacent parts is 20% or more,
The selective diffusion of the impurity in the step (i) is performed.
It is .

The gate according to claim 13 of the present invention.
In the method of manufacturing an insulation type semiconductor device, claims 8 to
Item 13. The manufacturing of the gate insulating semiconductor device according to any one of Items 12.
The first conductive material introduced in the step (k).
The impurity in the form of a sheet resistance of the fourth semiconductor region
Introduced so that the value is between 40Ω / □ and 150Ω / □
Is done . The gate insulation according to claim 14, according to the present invention.
14. A game device according to claim 13, wherein:
In the method for manufacturing an insulated semiconductor device, the step
The control electrode layer formed in (c) comprises a polycrystalline semiconductor.
Wherein the manufacturing method comprises the step of:
Of the step (j) after the step (i).
Before blocking the introduction of impurities and covering the first opening;
Providing a second shielding film on the insulating film; (q)
By using the second shielding film as a mask,
Selectively introducing impurities of the first conductivity type into the control electrode layer
And (r) before the step (j),
Removing the second shielding film;
The impurity of the first conductivity type introduced in (k) is
It is simultaneously introduced into the control electrode layer, and is introduced in the step (q).
The impurity of the first conductivity type to be used is subjected to the step (q) and the
And after both step (k) and the control electrode
Conducting so that the sheet resistance of the layer is 250Ω / □ or less
Is entered. The gate disconnection according to claim 15 of the present invention.
The method for manufacturing an edge-type semiconductor device according to claim 13, wherein
In the method for manufacturing a heat insulating semiconductor device, the step
The control electrode layer formed in (c) comprises a polycrystalline semiconductor.
The first conductivity type introduced in step (k)
Is also introduced into the control electrode layer at the same time,
The manufacturing method comprises the steps of: (p) combining the shielding film with a first shielding film;
And after step (k) and before step (l),
A second shield for preventing the introduction of an object and covering the first opening
Forming a film on the semiconductor substrate exposed in the first opening;
Providing on a surface portion and the insulating film portion;
(Q) using the second shielding film as a mask
Thus, the value of the sheet resistance of the control electrode layer is 250Ω / □.
As described below, the control electrode layer is not provided with the first conductivity type.
Selectively introducing a pure substance; and (r) the step
Removing the second shielding film before (l).
Ru with La. The gate according to claim 16, according to the present invention.
The method for manufacturing an insulated semiconductor device according to claim 13, wherein
In the method for manufacturing a gate insulating semiconductor device, the step
(C) is (c-1) the control electrode layer on the insulating film.
To form a layered material containing polycrystalline semiconductor
Step (c-2): introducing an impurity of the first conductivity type into the material
Step; and (c-3) forming a strip-shaped first opening in the material.
Forming the control electrode layer.
The first conductivity type introduced in the step (k).
Is also introduced into the control electrode layer at the same time,
The impurities of the first conductivity type introduced in the step (c-2)
After both the step (c-2) and the step (k)
The sheet resistance of the control electrode layer is 250Ω /
□ Introduced as follows. Claims according to the invention
In the method for manufacturing a gate insulating semiconductor device according to item 17,
A method for manufacturing a gate insulating semiconductor device according to claim 13.
In the step (c), the step (c) includes the step of:
Control electronics including polycrystalline semiconductor with pre-introduced pure
Forming a layer material on the insulating film in a layered manner;
And (c-2) a substantially band-shaped first opening in the material.
A step of forming the compound, and introduced in the step (k).
The impurity of the first conductivity type is simultaneously applied to the control electrode layer.
And the material formed in the step (c-1)
Concentration of impurities of the first conductivity type introduced in advance into the material
After both the step (c-1) and the step (k)
The sheet resistance of the control electrode layer is 250Ω /
□ Set to be as follows.

[0029]

In the gate insulating type semiconductor device according to the present invention, the first semiconductor region and the third semiconductor region, which are the two semiconductor regions of the first conductivity type, are exposed on the upper main surface of the semiconductor substrate. In some sections between planes,
Only the second semiconductor region of the conductivity type is exposed over its entire width, otherwise the concentration of the impurity of the second conductivity type is
The fourth semiconductor region having a high height is exposed as an outer area including at least the entire width thereof. A control electrode layer is opposed to the section, and when a voltage is applied to the control electrode layer, an inversion layer is formed in the section to conduct between the first semiconductor region and the third semiconductor region. In the second semiconductor region, the impurity concentration of the second conductivity type is relatively low.
Is relatively high in the semiconductor region, the gate threshold voltage V _GE (th) to be added to the control electrode layer to form the inversion layer
Is relatively low in a portion where only the second semiconductor region occupies the entire width of the section, and relatively high in a portion including the fourth semiconductor region.

As described above, in the device of the present invention, the section where the inversion layer is to be formed has a structure in which the low and high portions of the gate threshold voltage V _GE (th) are connected in parallel in an electric circuit. doing. The gate threshold voltage of the device according to the present invention mainly depends on the portion where the gate threshold voltage V _GE (th) is low, and the portion where the gate threshold voltage V _GE (th) is high does not change much. The collector-emitter saturation voltage V _CE (sat) has no significant effect even if a high gate threshold voltage V _GE (th) is provided. On the other hand, the saturation current I _CE (sat) strongly depends on the ratio occupied by the high portion of the gate threshold voltage V _GE (th), and decreases as the ratio increases. Therefore, the saturation current I _CE (s
at) can be reduced by providing a portion having a high gate threshold voltage V _GE (th). Therefore, while miniaturizing or increasing the density of the device, the gate threshold voltage V _GE (th)
By optimizing the distribution of high and low parts of
It is possible to obtain a device having a high short-circuit tolerance by reducing the loss by reducing the collector-emitter saturation voltage V _CE (sat) and reducing the saturation current I _CE (sat). Only
Also, the third semiconductor region has a first portion and a second portion.
Alternatively, the first main electrode layer is formed in the central area of the fourth semiconductor region.
And a portion protruding inside the third semiconductor region.
Connected to the second part. This allows the first
The connection between the main electrode layer and the third semiconductor region is
Guarantees high accuracy in turn alignment
Thus, miniaturization of the device is facilitated. First main electrode layer
Is connected to the third semiconductor region through the second portion
Therefore, the first layer is formed through the inversion layer formed in the section.
Carrier flowing between the semiconductor region and the third semiconductor region
Further includes, through the second portion, the first main electrode layer and the third main electrode layer.
Between the semiconductor regions. Therefore, through the inversion layer
The flowing carrier concentrates on the second part. But
Outside area where the gate threshold voltage V _GE (th) is selectively high
Is provided at a position matching the second portion,
The concentration of the carrier on the second portion is effectively alleviated. So
As a result, the short-circuit tolerance due to the provision of the second portion
Is suppressed. Thus, the fourth semiconductor region
The advantage of projecting into the outer area is that the second part
Effectively withdrawn without being reduced by
As a result, a high short-circuit tolerance can be obtained effectively.

In particular, the gate insulating type semiconductor according to claim 2
In the body device, the second portion connects the pair of first portions to each other.
And the first part and the second part have a ladder-like pattern as a whole.
The first main electrode and the third semiconductor layer
Mask pattern required to guarantee the connection between
In this case, the accuracy of the alignment of the patterns is further reduced. in addition
Accordingly, miniaturization of the device is further facilitated. further,
For the insulated gate semiconductor device according to claim 3, in which the optimized third semiconductor regions electrically connected to the first main electrode layer and the ratio of the fourth semiconductor regions, the saturation current I _CE (sat) is small and can therefore have a large short-circuit withstand capability.

Further, in the gate insulating type semiconductor device according to the fifth aspect , a ratio of a portion of the pair of strip-shaped areas bordering the outer area, that is, a relatively high gate threshold voltage V _GE.
Since the ratio of the inversion layer having (th) is optimized, the saturation current I _CE (sat) is small, and therefore, it can have a large short-circuit tolerance.

According to the manufacturing method of the eighth to tenth and twelfth aspects , it is possible to manufacture a gate insulating semiconductor device having the above advantages.

According to the present invention, the collector-emitter saturation voltage V _CE (sat) does not largely depend on the effective resistance in the third semiconductor region, and the short-circuit withstand capability strongly depends on the third semiconductor region.
That the effective resistance short-circuit capacity higher increases, which was made based on the discovery (claim 4, 6, 11 -
17 ).

This finding was made by the present inventor .

In the gate insulating semiconductor device according to the present invention,
The value of the sheet resistance of the third semiconductor region is 40Ω / □ to 1
It is in the range of 50Ω / □. Therefore, the short-circuit withstand capability of 10 μsec or more required for practical use is guaranteed, and a practical value is obtained for the collector-emitter saturation voltage V _CE (sat).

In the gate insulating type semiconductor device according to the present invention,
The sheet resistance value of the control electrode layer is 250Ω / □ or less. As the sheet resistance of the control electrode layer is lower, the switching operation of the device is faster, and the loss accompanying the switching operation is gradually reduced. Since the sheet resistance value is 250Ω / □ or less, it is possible to realize a switching loss low enough to satisfy practical requirements (claim 7) .

In the gate insulating semiconductor device according to the present invention,
The emitter contact (emitter bypass) ratio, that is, the area of the opening to which the first main electrode layer is connected on the upper main surface of the semiconductor substrate is occupied by a pair of band-shaped areas exposed to the opening, that is, the third semiconductor region. The area ratio is 5% to 25%. The lower the emitter contact ratio, the higher the effective resistance of the third semiconductor region, so that the short-circuit withstand capability is improved. Emitter contact ratio is 2
Since it is 5% or less, a practical 1
A short-circuit tolerance of 0 μsec or more is guaranteed. Since the emitter contact ratio is 5% or more, practically low values are obtained for the collector-emitter saturation voltage V _CE (sat) (claim 4).

According to the manufacturing method of the present invention ,
7 can be effectively manufactured (claims 11, 13 to 17 ).

[0040]

[Embodiment 1] <Structure of Device of First Embodiment> FIG. 1 is a plan view illustrating the structure of an N-channel IGBT 200 of the first embodiment. This IGBT 200 is a conventional IGBT 1 shown in FIG.
As in the case of 00, a large number of IGBT unit cells 210 are connected in parallel. FIG. 1 shows the emitter electrode 7 and the oxide film 8 removed. FIG. 1 also shows the shapes of various mask patterns used in the manufacturing process of the IGBT 200. FIG. 2 is a sectional view of one IGBT unit cell 210 along the line A1-A1 shown in FIG. FIG. 3 shows B1-B shown in FIG.
FIG. 4 is a cross-sectional view of one IGBT unit cell 210 along one line. Since the structure of each IGBT unit cell 210 is substantially the same as each other, the IGBT unit cells 210 shown in FIGS.
It is possible to understand the configuration of the entire BT 200. In the following drawings, the portions denoted by the same reference numerals as those of the conventional device shown in FIGS. 40 to 42 indicate the same portions as those of the conventional device.

As shown in FIGS. 2 and 3, this IGBT
The semiconductor substrate 220 includes an n-type epitaxial layer 2 formed on a p-type collector layer 1 made of a p-type semiconductor substrate.
Is composed. The upper main surface of the n-type epitaxial layer 2, that is, a part of the upper main surface of the semiconductor substrate 220 has p
The p-type base region 3 is formed by selectively diffusing the type impurities. Further, an n-type impurity is selectively diffused into a part of the upper main surface of the semiconductor substrate 220 to expose a pair of strip-shaped areas BA arranged substantially in parallel with a predetermined central area CA. An n-type emitter region 4 is formed. A gate insulating film 5 is formed on an upper surface of p-type base region 3 sandwiched between an upper surface of n-type epitaxial layer 2 and an upper main surface of n-type emitter region 4. Gate insulating film 5 is formed on the upper surface of n-type epitaxial layer 2 so as to be integrated between adjacent IGBT unit cells 210. A gate electrode 6 made of, for example, polysilicon is formed on the gate insulating film 5. An emitter electrode 7 made of, for example, aluminum is formed so as to be electrically connected to both the p-type base region 3 and the n-type emitter region 4. The gate electrode 6 and the emitter electrode 7 are insulated from each other via an interlayer insulating film, for example, an oxide film 8, and have a structure in which all the IGBT unit cells 210 are electrically connected in common to each other. ing. The oxide film 8 has an opening WD on a predetermined region covering a part of the band-shaped area BA and at least a part of the central area CA as shown in the figure. In the p-type base region 3, a high-concentration p-type semiconductor region 3 in which p-type impurities are diffused at a high concentration so as to surround the n-type emitter region 4
2 are formed. On the lower main surface of the p-type collector layer 1, a collector electrode 9 made of metal is formed integrally through all the IGBT unit cells 210.

As shown in FIG. 1, there are a relatively wide area (near the A1-A1 line) and a relatively narrow area (near the B1-B1 line) as viewed from above the n-type emitter region 4. FIG. 1 shows a mask pattern 51 used when forming the gate electrode 6 and a mask pattern 53 used when forming the n-type emitter region 4 in the manufacturing process.
A mask pattern 54 used when forming the high-concentration p-type semiconductor region 32 and an oxide film 8 for electrically connecting both the p-type base region 3 and the n-type emitter region 4 to the emitter electrode 7 are formed. The mask pattern 55 used in the contact step to be removed is shown by a dotted line.

As shown in FIG. 1 and FIG.
The type semiconductor region 32 protrudes outside the n-type emitter region 4 in a region having a relatively large width (near the line A1-A1) as viewed from above the n-type emitter region 4, and the p-type base region 3 Is formed over a wide region so as not to reach the region of the n-type epitaxial layer 2. In order to form the high-concentration p-type semiconductor region 32 in this manner, the mask pattern 54 is wider in the vicinity of the A1-A1 line than in other parts.

<Operation and Characteristics of the Device of the First Embodiment>
The operation of the BT 200 will be described. When the collector voltage V _CE is applied between the collector electrode 9 and the emitter electrode 7, the gate voltage V _CE is applied between the gate electrode 6 and the emitter electrode 7.
_{When GE} is positively applied, the upper surface of the p-type base region 3 between the n-type emitter region 4 and the n-type epitaxial layer 2 becomes p-type.
N-type semiconductor is inverted from the n-type semiconductor to form an n-type channel. An n-type epitaxial layer 2 corresponding to the drain of the MOSFET and an n-type emitter region corresponding to the source are equivalently formed in the IGBT unit cell 210. 4, and the electron current flows from the n-type emitter region 4 into the n-type epitaxial layer 2 through the n-type channel. This electron current becomes a base current of a pnp bipolar transistor equivalently formed by the p-type collector layer 1, the n-type epitaxial layer 2, and the p-type base region 3. At this time, holes are injected from the p-type collector layer 1 to the n-type epitaxial layer 2, a part of the injected holes are recombined with carrier electrons of the n-type epitaxial layer 2, and the rest is p-type base region 3. And flows into the emitter electrode 7 as a hole current through the IGBT.
Reference numeral 200 denotes a conductive state (ON), that is, a state in which the collector electrode 9 and the emitter electrode 7 are conductive.

Applying a zero voltage to the gate voltage V _GE , ie, applying a zero bias or applying a negative voltage,
That is, by applying a negative bias, the equivalently formed MOSFET is turned off, and the electron current does not flow. As a result, the IGBT 200 is turned off (off).

As shown in FIG. 1 and FIG.
In a region where the width as viewed from above the n-type emitter region 4 is relatively wide (in the vicinity of the line A1-A1), the type semiconductor region 32 extends outside the n-type emitter region 4 and the p-type base region 3 Is formed over a wide region so as not to reach the region of the n-type epitaxial layer 2. Therefore, by applying a positive voltage to the gate voltage V _GE , the n-type channel formed between the n-type emitter region 4 and the n-type epitaxial layer 2 has a p-type base near the A1-A1 line. The inversion layer in the region 3 and the inversion layer in the high-concentration p-type semiconductor region 32 are both connected in series. On the other hand, in the vicinity of the B1-B1 line, the high-concentration p-type semiconductor region 32 is formed inside the n-type emitter region 4 when viewed from above. It is formed only by the inversion layer.

The gate threshold voltage V _GE (th), which is the height of the gate voltage necessary for forming the inversion layer, has a higher value in the high-concentration p-type semiconductor region 32 than in the p-type base region 3. . Therefore, the gate threshold voltage V _GE (th) is A1-
A relatively high value V _GE (th-High) near the A1 line
In the vicinity of the line B1-B1, a relatively low value V _GE (t
h-Low). This means that the n-type channel formed between the n-type emitter region 4 and the n-type epitaxial layer 2 is different from the n-type channel having a relatively high gate threshold voltage V _GE (th-High). The gate threshold voltage V _GE (t
h-Low) in parallel connection with an n-type channel.

The gate threshold voltage V _{GE of the} entire IGBT 200
(th), the collector current Ic (a current flowing from the collector electrode 9 to the emitter electrode 7) is a gate voltage V _GE when starts to rise from zero with an increase in the gate voltage V _GE, in other words when the collector current Ic given by the gate voltage V _GE when reaches a certain predetermined value which is set considerably lower than its rated value (maximum value in normal use). Therefore, the gate threshold voltage V _GE (th) is mainly determined by the relatively low gate threshold voltage V _GE (th-Low), and substantially equals the gate threshold voltage V _GE (th-Low). That is,
The provision of an n-type channel having a relatively high gate threshold voltage V _GE (th-High) in the device of this embodiment
The gate threshold voltage V _GE (th) of the entire IGBT 200 is hardly affected. Further, in the structure shown in FIGS. 1 to 3, an n-type channel having a relatively high gate threshold voltage V _GE (th-High) even at the collector-emitter saturation voltage V _CE (sat) is provided. The effect due to is only slight.
On the other hand, the influence on the saturation current I _CE (sat) appears relatively strongly as described below.

The IGBT 200 has a relatively high gate threshold voltage V _GE (th-High) lower than a predetermined gate voltage V _GE when the IGBT 200 is turned on, that is, as shown in Expression 2. The high-concentration p-type semiconductor region 32
Is selected.

[0050]

(Equation 2)

[0051] When configured number 2, when the applied voltage value at the ON time to the gate threshold voltage V _GE (th), n-type channels having the relatively low gate threshold voltage V _GE (th-Low) Has a strong inversion, and the relatively high gate threshold voltage V _GE
In the high concentration p-type semiconductor region 32 in the n-type channel having (th-High), weak inversion occurs. As an example,
The gate threshold voltage V _GE (th-High) is about 5 V. If the gate voltage V _GE at the time of ON is set to 15 V, the gate threshold voltage V _GE (th-High) is selected to be, for example, about 10 V. I
The saturation current I _CE (sa
t) is derived from Equation 1,

[0052]

(Equation 3)

From the relationship, the channel width W of the n-type channel
Relatively high gate threshold voltage V _GE (th-High)
, The higher the ratio, the lower the saturation current I _CE (sat).

Therefore, the device of this embodiment has a relatively high gate threshold voltage V _GE (th-High) occupying the n-type channel even if the IGBT unit cell 210 is miniaturized and densified.
By optimizing the proportion of n-type channels with
Lowering the collector-emitter saturation voltage V _CE (sat)
Moreover, the saturation current I _CE (sat) can be kept low, and a high short-circuit withstand capability can be realized.

The device of this embodiment has a relatively wide area (near the line A1-A1) and a relatively narrow area (near the line B1-B1) as viewed from above the n-type emitter region 4. I have. This assures a withstand voltage between the gate electrode 6 and the emitter electrode 7 and also guarantees electrical connection between the n-type emitter region 4 and the high-concentration p-type semiconductor region 32 to the emitter electrode 7. IGBT unit cell 2
There is an advantage that 10 miniaturization can be performed.

Further, in the device of this embodiment, as described above, the high-concentration p-type semiconductor region 32 is formed widely in a region having a relatively large width (near the A1-A1 line) as viewed from above the n-type emitter region 4. Therefore, there is an advantage that the parasitic thyristor effect is more effectively suppressed.

<Measured Values of the Characteristics of the Device of the First Embodiment> The electrical characteristics based on the actually measured values of the IGBT 200 as the device of the first embodiment are shown below. In order to reduce the collector-emitter saturation voltage V _CE (sat) of the IGBT 200, it is effective to improve the characteristics of the MOSFET region equivalently formed in the IGBT unit cell 210 as described above. . As one means, the p-type base region 3
Is made as small as possible and the IGBT unit cell 210 is miniaturized, that is, densified, thereby increasing the channel width W of the MOSFET region. In order to reduce the width of the p-type base region 3, in the region where the width of the n-type emitter region 4 is wide (in the vicinity of the line A1-A1), the opposing n-type emitter regions 4 are connected, as shown in FIG. It is preferable to have a structure having a simple ladder-like n-type emitter pattern.

FIG. 4 schematically shows the pattern of the p-type base region 3 and the n-type emitter region 4 on the upper main surface of the semiconductor substrate 220 when the same miniaturization is performed in the IGBT unit cell 210. It is illustrated. As with the IGBT unit cell 210 shown in FIG. 1, many IGBT unit cells 210a shown in the figure are connected in parallel to form an IGBT 200a. The n-type emitter region 4a, the high-concentration p-type semiconductor region 32a, the mask pattern 53a, and the mask pattern 54a
In the GBT unit cell 210, the n-type emitter region 4, the high-concentration p-type semiconductor region 32, the mask pattern 53,
And the mask pattern 54. In the IGBT unit cell 210a, a portion where two n-type emitter regions 4a arranged in a band shape are connected to each other (C1a-C1a) even in a region other than the region where the high-concentration p-type semiconductor region 32a is wide (in the vicinity of the A1a-A1a line). (Near the line).

FIGS. 5 and 6 show A1a-A1a, respectively.
FIG. 4 is a cross-sectional view of the IGBT unit cell 210a taken along line C1a-C1a. The cross-sectional structures illustrated in these figures are different from the cross-sectional structures illustrated in FIGS. 2 and 3, respectively.
The structure is the same except that the n-type emitter region 4a is not divided into two right and left regions. The cross-sectional structure taken along the line B1a-B1a is the same as the structure shown in the cross-sectional view of FIG.

In the n-type emitter pattern shown in FIG. 4, the width of the n-type
The width of a region other than the type emitter region 4, that is, a region of the p-type base region 3 exposed on the upper main surface of the semiconductor substrate 220 is represented by Y. At this time, the emitter bypass ratio e is defined by Expression 4.

[0061]

(Equation 4)

As shown in FIG. 4, the length of a portion where high concentration p-type semiconductor region 32a is interposed between n-type emitter region 4a and n-type epitaxial layer 2 on the upper main surface of semiconductor substrate 220 is H. The length of a portion isolated only by the p-type base region 3 without the high-concentration p-type semiconductor region 32a interposed therebetween is represented by L. Based on these H and L, the high gate threshold voltage region ratio g is defined by Expression 5.

[0063]

(Equation 5)

The length H or L is respectively set to a relatively high gate threshold voltage V _GE (th-High) or a low gate threshold voltage V _GE (t-High).
h-Low). When the emitter bypass ratio e increases, the area of the n-type emitter region 4a increases, and the sheet resistance of the n-type emitter region 4a decreases. This is equivalent to a decrease in the source resistance equivalently connected in series in the MOSFET region, which causes an increase in the electron current in the MOSFET region. This increases the short-circuit current of the IGBT,
As a result, short-circuit withstand capability decreases.

FIG. 7 shows the structure of the I shown in FIGS.
For GBT200a, collector-emitter saturation voltage V _CE with respect to the emitter bypass ratio e (sat), is a graph illustrating the measurement results of the saturation current I _CE (sat), and short-circuit tolerance t _w. In the figure, the actual measurement values plotted by the curves are obtained when the high gate threshold voltage region ratio g is g = 20%. The figure shows that the emitter bypass ratio e is e
= 36%, and the high gate threshold voltage area ratio g is g = 0.
The measured value when the value is% is also shown. It is to be noted that the short-circuit tolerance t _w, is the time required to reach to the destruction at the time of short-circuiting the output of the IGBT.

In FIG. 7, when e = 36%,
Comparing the measured value at g = 0% with the measured value at g = 20%, a noticeable difference in the collector-emitter saturation voltage V _CE (sat) due to the provision of the high-concentration p-type semiconductor region 32a. The saturation current I _CE (sa
t) is greatly suppressed, it can be understood that the short-circuit tolerance t _w has been greatly improved accordingly. This supports the qualitative explanation described above.

[0067] short-circuit tolerance t _w required when using the IGBT inverter device is about t _w ≧ 10 .mu.sec. Further, to detect a short circuit current flowing in the event of a short circuit, even IGBT having a circuit for performing a short-circuit protection, short-circuit tolerance t _w required for the IGBT device itself is approximately t _w ≧ 5 .mu.sec. In order to satisfy this, it is necessary from the measurement results shown in FIG. 7 that the emitter bypass ratio e is e ≦ 50% and the high gate threshold voltage region ratio g is g ≧ 20%. is there.

The above-mentioned actual measurement results are obtained for the IGBT 200a shown in FIGS. 4 to 6 for convenience of actual measurement. Is defined as a ratio occupied by the n-type emitter region 4 in the total area of the n-type emitter region 4 and the high-concentration p-type semiconductor region 32 in contact with FIG.
It can be sufficiently predicted that similar results are obtained for the IGBT 200 shown in FIG.

<Manufacturing Process of Apparatus of First Embodiment> FIGS.
1 is an IG in each stage of the manufacturing process of the IGBT 200.
FIG. 3 is a front sectional view of a BT unit cell 210. With reference to these figures, IGBT200 which is the device of this embodiment
Will be described.

First, a p-type silicon substrate SB corresponding to the p-type collector layer 1 is prepared (FIG. 8). Next, an n-type epitaxial layer 2 is formed thereon by epitaxial growth. The p-type collector layer 1 and the n-type epitaxial layer 2 form a semiconductor substrate 220. In the following FIGS. 9 to 19 and FIG.
Only above the type epitaxial layer 2 is shown.

In the step of FIG. 9, a silicon oxide film 71 is formed on n-type epitaxial layer 2, that is, on the upper main surface of semiconductor substrate 220.

Next, polysilicon is converted to a silicon oxide film 71.
And a resist layer is provided on the entire surface.
Photolithography of the resist layer is performed using a mask 72 having a pattern corresponding to the mask pattern 51 shown in FIG. 1, thereby obtaining a resist pattern 73 corresponding to the mask pattern 51. Then, the polysilicon is selectively etched using the resist pattern 73 as a mask, thereby forming the gate electrode 6 on the silicon oxide film 71. Further, using the resist pattern 73 and the gate electrode 6 as a mask, boron is selectively implanted into the n-type epitaxial layer 2 to obtain a p-type semiconductor region 74 (FIG. 10).

Thereafter, the resist pattern 73 is removed, and boron in the p-type semiconductor region 74 is diffused to below the gate electrode 6 by a driving process, thereby obtaining the p-type base region 3 shown in FIG.

FIG. 12 (cross-sectional view taken along line A1-A1 in FIG. 1) and FIG. 13 (cross-sectional view taken along line B1-B1 in FIG. 1)
In the step shown in (1), a resist layer is first provided on the entire surface of the gate electrode 6 and the silicon oxide film 71. Mask 7 having a pattern corresponding to mask pattern 54 shown in FIG.
5, photolithography of the resist layer is performed, thereby forming a resist pattern 76 corresponding to the mask pattern 54.
Get. Further, relatively high-concentration boron is selectively implanted into the p-type base region 3 using the resist pattern 76 and the gate electrode 6 as a mask, and the high-concentration p-type semiconductor region 7 is formed.
Get 7.

Next, the resist pattern 76 is removed,
Boron in the high-concentration p-type semiconductor region 77 is diffused by the driving step, and the high-concentration p-type semiconductor region 77 is diffused as shown in FIG. A p-type semiconductor region 32 is obtained. The mask pattern 54 used in the steps shown in FIGS.
As shown in FIG. 1, it is wider near the line A1-A1.
Due to the narrower shape near the line B1-B1, the high-concentration p-type semiconductor region 32 extends below the gate electrode 6 near the line A1-A1 (FIG. 1).
4) On the other hand, in the vicinity of the B1-B1 line, its spread remains inside the opening 6a of the gate electrode 6 (FIG. 1).
5). The diffusion step of the high concentration p-type semiconductor region 77 described above includes:
The high-concentration p-type semiconductor region 32 formed thereby has A
The process is performed so as not to reach the region of the n-type epitaxial layer 2 beyond the region of the p-type base region 3 in the vicinity of the line 1-A1.

Next, in the steps shown in FIGS. 16 (a sectional view taken along line A1-A1 in FIG. 1) and FIG. 17 (a sectional view taken along line B1-B1 in FIG. 1), first, the gate electrode 6 and the silicon oxide film 71 A mask 78 having a pattern corresponding to the mask pattern 53 by providing a resist layer on the entire upper surface
This resist layer is patterned by photoengraving using, to obtain a resist pattern 79. By selectively etching the silicon oxide film 71 using the resist pattern 79 and the gate electrode 6 as a mask, the gate insulating film 5 and the oxide film pattern 80 are obtained.

Subsequently, as shown in FIG. 18 (cross-sectional view taken along line A1-A1 in FIG. 1) and FIG. 19 (cross-sectional view taken along line B1-B1 in FIG. 1), after removing the resist pattern 79, the oxide film is removed. Using the pattern 80, the gate insulating film 5, and the gate electrode 6 as a mask, the high-concentration p-type semiconductor region 32
Arsenic is selectively implanted into the upper main surface of the substrate. As a result, n is added to the region near the upper main surface of the high-concentration p-type semiconductor region 32.
A mold emitter region 4 is formed. The mask pattern 53 used in the steps shown in FIGS. 16 and 17 has a wide shape near the line A1-A1 and a narrow width near the line B1-B1 as shown in FIG. The n-type emitter region 4 forms a wider area inside the opening 6a of the gate electrode 6 in the vicinity of the line A1-A1 (FIG. 18), while its spread increases in the vicinity of the line B1-B1. It remains inside the opening 6a of the electrode 6 and near the opening end 6b of the gate electrode 6 (FIG. 19).

FIG. 20 (cross-sectional view taken along line A1-A1 in FIG. 1) and FIG. 21 (cross-sectional view taken along line B1-B1 in FIG. 1)
In the step shown in (1), first, a relatively thick silicon oxide film is provided on the entire upper surface of the structure after the previous step, and the silicon oxide film is selectively etched by using a mask 81 having a pattern corresponding to the mask pattern 55. Remove. Thus, oxide film 8 having opening 8a is obtained. The opening end 8b of the oxide film 8 is located above the n-type emitter region 4 near the line A1-A1 (FIG. 20), while above the high concentration p-type semiconductor region 32 near the line B1-B1. (FIG. 21).

An aluminum film is formed on the entire upper surface of the structure obtained in this manner, and is used as an emitter electrode 7 shown in FIGS. A portion of the emitter electrode 7 existing inside the opening 8a electrically short-circuits the p-type base region 3 and the n-type emitter region 4. Further, the semiconductor substrate 22
0, a Ti—Ni—Au film is formed on the entire lower main surface S1,
The collector electrode 9 shown in FIGS. 2 and 3 is obtained.

Embodiment 2 <Structure of Apparatus of Second Embodiment> FIG. 22 is a plan view illustrating the structure of an N-channel IGBT 300 of the second embodiment.
The IGBT 300 has a structure in which many IGBT unit cells 310 are connected in parallel, similarly to the IGBT 200 which is the device of the first embodiment shown in FIG. FIG.
In FIG. 3, the emitter electrode 7 and the oxide film 8 are removed. FIG. 22 shows the shapes of various mask patterns used in the manufacturing process of the IGBT 200 by dotted lines.
The mask pattern 56 is a mask pattern used when forming the high-concentration p-type semiconductor region 32. FIG. 23 shows one IGBT on the line A2-A2 shown in FIG.
FIG. 3 is a cross-sectional view of a unit cell 310.

As shown in FIG. 22, the line A2-A2 is the same as the line A1-A1 in the device of the first embodiment, and the width in the vicinity thereof is relatively large as viewed from above the n-type emitter region 4. , B2-B2, like the B1-B1 line in the device of the first embodiment, have a relatively small width in the vicinity thereof as viewed from above the n-type emitter region 4. IG
In the BT unit cell 310, the high-concentration p-type semiconductor region 33 in which the p-type impurity is diffused at a high concentration so as to surround the n-type emitter region 4 exceeds the p-type base region 3 near the line A2-A2. , N-type epitaxial layer 2. High concentration p-type semiconductor region 33
Meanwhile, near the line B2-B2, the high concentration p in FIG.
It is the same as the p-type semiconductor region 32 or the high-concentration p-type semiconductor region 31 in FIG. 42, and is formed so as not to spread outside the n-type emitter region 4. A sectional view taken along line B2-B2 is shown in FIG.
Is replaced with a high-concentration p-type semiconductor region 33, and is not shown.

<Characteristics of Device of Second Embodiment> In the IGBT 300 of the device of the second embodiment, the n-type channel formed between the n-type emitter region 4 and the n-type epitaxial layer 2 is
In the vicinity of the line A2-A2, the gate threshold voltage V _GE (th) increases under the influence of the high-concentration p-type semiconductor region 32,
In addition, the channel length L is long. This inversion layer has a larger channel length than the n-type channel formed by the inversion layer of the high-concentration p-type semiconductor region 31 near the line A1-A1 of the IGBT 200 of the first embodiment. Therefore, Embodiment 1
There is an advantage that the effect of reducing the saturation current I _CE (sat) is higher than that of the device of the above.

<Manufacturing Process of Device of Second Embodiment> FIGS. 24 and 25 are cross-sectional views of the IGBT unit cell 310 taken along line A2-A2 at a certain stage in the manufacturing process of the IGBT 300. The manufacturing process of the IGBT 300 which is the device of this embodiment will be described with reference to these drawings.

First, the IGBT 200 shown in FIGS.
Steps similar to step 1 are performed. Next, FIG.
First, a resist layer is provided on the entire surface of the gate electrode 6 and the silicon oxide film 71. Photolithography of the resist layer is performed using a mask 82 having a pattern corresponding to the mask pattern 56 shown in FIG. 1, thereby obtaining a resist pattern 83 corresponding to the mask pattern 56. Further, using this resist pattern 83 as a mask, high-concentration, high-energy boron is selectively implanted into the p-type base region 3 and the n-type epitaxial layer 2 to obtain a high-concentration p-type semiconductor region 84.

Next, proceeding to the step shown in FIG. 25, the resist pattern 83 is removed, and boron in the high-concentration p-type semiconductor region 84 is diffused by a driving step to obtain the high-concentration p-type semiconductor region 33. . As shown in FIG. 22, the mask pattern 56 used in the process shown in FIG.
The shape is wider near the line -A2 and narrower near the line B2-B2. For this reason, the high-concentration p-type semiconductor region 33 has a gate electrode 6 near the line A2-A2.
Is extended to the region of the n-type epitaxial layer 2 below. On the other hand, in the vicinity of the line B2-B2, the extension of the high-concentration p-type semiconductor region 33 is similar to that of the high-concentration p-type semiconductor region 32 in the device of the first embodiment shown in FIG. Staying inside. Subsequent steps are the same as the steps shown in FIGS. 16 to 22 in the apparatus of the first embodiment.

[Embodiment 3] <Structure of Apparatus According to Third Embodiment> FIG. 26 is a plan view illustrating the structure of an N-channel IGBT 400 according to the third embodiment.
The IGBT 400 has a structure in which a number of IGBT unit cells 410 are connected in parallel, similarly to the IGBT 200 which is the device of the first embodiment shown in FIG. FIG.
In FIG. 3, the emitter electrode 7 and the oxide film 8 are removed. FIG. 26 further shows the shapes of various mask patterns used in the manufacturing process of the IGBT 400 by dotted lines. The mask pattern 57 is a mask pattern used when forming the high-concentration p-type semiconductor region 34. FIG.
7 is one IG in the A3-A3 line shown in FIG.
FIG. 28 is a cross-sectional view of the BT unit cell 410, and FIG. 28 is also a cross-sectional view taken along line B3-B3.

As shown in FIG. 26, similar to the line A1-A1 in the device of the first embodiment, the line A3-A3 has a relatively large width in the vicinity thereof as viewed from above the n-type emitter region 4. Line B3-B3 is B1 in the apparatus of the first embodiment.
Similar to the -B1 line, the width in the vicinity thereof as viewed from above the n-type emitter region 4 is relatively narrow.

In the device of the first or second embodiment, the high concentration p-type semiconductor region 32 or 33 formed to obtain an n-type channel having a relatively high gate threshold voltage V _GE (th-High)
Is also diffused and formed immediately below the n-type emitter region 4, and also has a function of suppressing the effect of the above-mentioned parasitic thyristor. In the IGBT 400 of this embodiment, as shown in FIG. 27, the high-concentration p-type semiconductor region 35 formed to obtain an n-type channel having a relatively high gate threshold voltage V _GE (th-High) Separately from the high-concentration p-type semiconductor region 34 provided for suppressing the effect of the parasitic thyristor,
The diffusion is shallow as shown in FIGS. As shown in FIG. 26, the shape of the high-concentration p-type semiconductor region 35 as viewed from the top main surface is the same as the shape of the high-concentration p-type semiconductor region 32 in the device of the first embodiment shown in FIG. on the other hand,
Since the high-concentration p-type semiconductor region 34 is intended to suppress the parasitic thyristor effect, the high-concentration p-type semiconductor region 34 is formed to be deeper than the high-concentration p-type semiconductor region 35 immediately below the n-type emitter region 4.
Further, as shown in FIGS. 27 and 28, the high-concentration p-type semiconductor region 34 does not affect the gate threshold voltage V _GE (th) in the vicinity of the A3-A3 line as in the vicinity of the B3-B3 line. Is formed inside the n-type emitter region 4.

The high-concentration p-type semiconductor region 35 is
It may not be formed near the line B3.

<Characteristics of Apparatus of Third Embodiment> The IGBT 400 of the third embodiment has the above-described configuration.
The shape and boron concentration of the high-concentration p-type semiconductor region 34 are optimized to be suitable for suppressing the parasitic thyristor effect, while the shape and boron concentration of the high-concentration p-type semiconductor region 35 are reduced to reduce the saturation current I _CE (sat). It can be optimized to suit. That is, it is possible to select a configuration that is optimal for each of the two purposes independently, so that there is an advantage that a higher effect can be obtained for each purpose.

<Manufacturing Process of Apparatus of Third Embodiment> FIGS.
FIG. 4 is a front sectional view of the IGBT unit cell 410. With reference to these figures, IGBT4 which is the device of this embodiment
00 manufacturing process will be described.

First, the IGBT 200 shown in FIGS.
Steps similar to step 1 are performed. Next, FIG.
In the process shown in (cross-sectional views taken along lines A3-A3 and B3-B3), a resist layer is first provided over the entire surface of the gate electrode 6 and the silicon oxide film 71. Photolithography of the resist layer is performed using a mask 85 having a pattern corresponding to the mask pattern 57 shown in FIG. 26, whereby a resist pattern 86 corresponding to the mask pattern 57 is obtained. Further, using this resist pattern 86 as a mask, high-concentration boron is selectively implanted into the p-type base region 3 to obtain a high-concentration p-type semiconductor region 87.

Next, FIG. 30 (A3-A3 line and B3-B
(A cross-sectional view taken along line 3), the resist pattern 86 is removed, and boron in the high-concentration p-type semiconductor region 87 is diffused by a driving process to form a high-concentration p-type semiconductor region 87.
A type semiconductor region 88 is obtained. The mask pattern 57 used in the step shown in FIG.
Since both the A3 line and the B3-B3 line have the same cross-sectional shape, there is no difference in these steps between the two cross-sections. The shape of the mask pattern 57 and the high-concentration p-type semiconductor region 87 are such that the high-concentration p-type semiconductor region 88 occupies the position inside the opening 6a of the electrode 6 (FIG. 30).
Is appropriately selected.

The steps shown in FIG. 31 (cross-sectional view taken along line A3-A3) and FIG. 32 (cross-sectional view taken along line B3-B3) are the same as the steps shown in FIGS. Be executed. That is, a resist pattern 76 is formed using the mask pattern 54, and relatively high-concentration boron is selected in the p-type base region 3 and the high-concentration p-type semiconductor region 88 using the resist pattern 76 and the gate electrode 6 as masks. Implanted to obtain a high-concentration p-type semiconductor region 89.

In the steps shown in FIGS. 33 (cross-sectional view taken along line A3-A3) and FIG. 34 (cross-sectional view taken along line B3-B3), the resist pattern 76 is removed, and the high-concentration p-type semiconductor region 89 is formed by a driving step. Is diffused to obtain a high-concentration p-type semiconductor region 35 shown in FIGS. At this time, the boron in the high-concentration p-type semiconductor region 88 is simultaneously diffused, so that the high-concentration p-type semiconductor region 34 is obtained.

Steps subsequent to the above steps are the same as the steps shown in FIGS. 16 to 22 in the apparatus of the first embodiment.

Embodiment 4 <Structure of Apparatus According to Fourth Embodiment> FIG. 35 is a plan view illustrating the structure of an N-channel IGBT 500 which is the apparatus according to the fourth embodiment. This IGBT 500 has a structure in which a number of IGBT unit cells 510 are connected in parallel, as in the other embodiments. FIG. 35 shows the emitter electrode 7 and the oxide film 8 removed. FIG. 35 further shows this IG
The shapes of various mask patterns used in the manufacturing process of the BT500 are shown by dotted lines. FIG. 36 shows one IGBT unit cell 51 along the line A4-A4 shown in FIG.
0 is a sectional view.

As shown in FIGS. 35 and 36, the apparatus of this embodiment combines the features of the apparatus of the second embodiment and the apparatus of the third embodiment. That is, the third embodiment
As in the device of the prior art, the relatively high gate threshold voltage V _GE (th-Hi
gh) is formed separately from the high-concentration p-type semiconductor region 34 provided to suppress the effect of the parasitic thyristor. . Further, the high-concentration p-type semiconductor region 36
In the vicinity of the A4-A4 line, which is relatively wide as viewed from above the n-type emitter region 4, the n-type epitaxial layer 2 It is formed so as to penetrate the area. B4-
The cross-sectional structure taken along line B4 is B3-B3 of the device of the third embodiment.
This is the same as the cross-sectional structure taken along the line. That is, B4-B4
The cross-sectional view (not shown) taken along the line is that the high-concentration p-type semiconductor region 35 is
6 is the same as that described above.

<Characteristics of Apparatus of Fourth Embodiment> With such a configuration, the IGBT 500 of the fourth embodiment
The characteristics of the device of the second embodiment and the characteristics of the device of the third embodiment are combined. That is, the channel length of the n-type channel having the relatively high gate threshold voltage V _GE (th-High) formed by the high-concentration p-type semiconductor region 36 is the same as that of the device of the first or second embodiment. 3 has an advantage that the effect of reducing the saturation current I _CE (sat) is higher than those of these devices. Further, similarly to the device of the third embodiment, the formation of the high-concentration p-type semiconductor region 34 for reducing the saturation current I _CE (sat) and the high-concentration p-type semiconductor region 36 for suppressing the parasitic thyristor effect are independent of each other. Therefore, there is an advantage that a higher effect can be obtained for both of these purposes.

<Manufacturing Process of Device of Embodiment 4> FIGS. 37 and 38 are cross-sectional views of the IGBT unit cell 510 taken along the line A4-A4 at a certain stage in the manufacturing process of the IGBT 500. With reference to these drawings, a description will be given of a manufacturing process of the IGBT 500 which is the device of this embodiment.

First, the IGBT 40 according to the third embodiment is used.
The same processes as those in the manufacturing process No. 0 are performed up to the process illustrated in FIG. Subsequently, the process proceeds to the step shown in FIG. 37, and a resist layer is first provided on the entire surface of the gate electrode 6 and the silicon oxide film 71. Photolithography of the resist layer is performed using a mask 82 having a pattern corresponding to the mask pattern 56 shown in FIG. 35, whereby a resist pattern 83 corresponding to the mask pattern 56 is obtained. Further, using this resist pattern 83 as a mask, high-concentration, high-energy boron is applied to the high-concentration p-type semiconductor region 8.
8, selectively implanted into the p-type base region 3 and the n-type epitaxial layer 2 to obtain a high-concentration p-type semiconductor region 90.

Next, proceeding to the step shown in FIG. 38, the resist pattern 83 is removed, and boron in the high-concentration p-type semiconductor region 90 is diffused by a driving step to obtain the high-concentration p-type semiconductor region 36. . At this time, boron in the high concentration p-type semiconductor region 88 is also diffused at the same time,
A high concentration p-type semiconductor region 34 is obtained. As shown in FIG. 35, the mask pattern 56 used in the step shown in FIG. 37 has a shape that is wider near the line A4-A4 and narrower near the line B4-B4. Therefore, the high-concentration p-type semiconductor region 36 extends to the region of the n-type epitaxial layer 2 below the gate electrode 6 near the line A4-A4. On the other hand, the cross-sectional structure taken along line B4-B4 after this step is the same as the cross-sectional structure taken along line B3-B3 in the device of the third embodiment shown in FIG. The high concentration p-type semiconductor region 34 and the high concentration p
The extension of the type semiconductor region 36 corresponds to the opening 6a of the gate electrode 6.
Stays inside. The subsequent steps are the same as the steps following the steps shown in FIGS. 33 and 34 in the apparatus of the third embodiment.

[Modifications of Embodiments 1 to 4] (1) In each of the above-described embodiments, the height at which an n-type channel having a relatively high gate threshold voltage V _GE (th-High) is to be formed is set. Concentration p-type semiconductor regions 32, 33, 35, or 36,
The n-type emitter region 4 is provided in a region having a relatively large width when viewed from above. This is for the purpose that the high-concentration p-type semiconductor region 32 and the like effectively function to suppress the parasitic thyristor effect. The width of the high-concentration p-type semiconductor region where an n-type channel having a relatively high gate threshold voltage V _GE (th-High) is to be formed as viewed from above the n-type emitter region 4 is relatively wide. It may be provided in an area other than the area. Also in this case, the saturation current I _CE
The effect of reducing (sat) is obtained.

(2) All of the devices of the above embodiments are
Although an n-channel IGBT has been exemplified, the present invention can be similarly implemented in a p-channel IGBT in which the polarity of the semiconductor layers forming the IGBT are all opposite to these. FIG. 39 shows an example of a device in which the polarity of the semiconductor is opposite to that of the device of the first embodiment. FIG. 39 is a front sectional view of the IGBT unit cell at a position corresponding to FIG.
In the figure, the semiconductor layers 1a to 4a and 31a are opposite in polarity to the semiconductor layers 1 to 4 and 31 in FIG. 2, respectively.

(3) In the above embodiment, the relationship between the gate threshold voltage V _GE (th-High) and the gate voltage V _GE is as follows.
Although the case where V _GE (th-High) <V _GE has been described,
The impurity concentration of the high-concentration p-type semiconductor regions 32, 33, etc. may be increased to form the high-concentration p-type semiconductor regions 32, 33, etc., so that V _GE (th-High) ≧ V _GE . At this time, the effect of reducing the collector-emitter saturation voltage V _CE (sat) is somewhat reduced, but the effect of reducing the saturation current I _CE (sat) is higher and there is an advantage that a higher short-circuit withstand capability can be obtained. .

(4) Gate threshold voltage V _GE in the present invention
The region with a high (th) may not be arranged uniformly in all the IGBT unit cells, but may be arranged in a specific place in the IGBT chip. For example, a similar improvement effect can be obtained by disposing the collector current Ic on the IGBT chip pattern so as to suppress concentration of the collector current Ic.

(5) The present invention is not limited to IGBTs, and is not limited to IGBTs.
FET, EST, MCT, etc.) can be generally implemented.

[Embodiment 5] <Characteristics of IGBT> Here, in the IGBT having the same cross-sectional structure as the IGBTs 200 to 500 and 200a shown in each of the above embodiments, the emitter contact ratios e and n
Example 5 in which the sheet resistance and the like of the emitter region 4 are optimized
IGBT will be described.

FIG. 43 is a plan view showing the structure of an IGBT 200a actually measured for studying these optimizations. The IGBT unit cell 210a shown in FIG.
Like the IGBT unit cell 210 shown in FIG. 1, many are connected in parallel to form an IGBT 200a. n-type emitter region 4a, high-concentration p-type semiconductor region 32
a, mask pattern 53a, and mask pattern 54a
Correspond to the n-type emitter region 4, the high-concentration p-type semiconductor region 32, the mask pattern 53, and the mask pattern 54 in the IGBT unit cell 210, respectively. IG
In the BT unit cell 210a, the IGBT shown in FIG.
Unlike the unit cell 210a, except for the region where the high-concentration p-type semiconductor region 32a has a wide width (near the line A1a-A1a), a portion where two n-type emitter regions 4a arranged in a band are connected to each other (FIG. 4 near the C1a-C1a line) does not exist. The sectional structure of the IGBT unit cell 210a along the line A1a-A1a and the line B1a-B1a is as follows.
They are as shown in the sectional views of FIGS. 5 and 3, respectively.

In the n-type emitter pattern shown in FIG. 43, as shown in FIG.
The width of a region that is not the n-type emitter region 4, that is, a region of the p-type base region 3 that is exposed on the upper main surface of the semiconductor substrate 220 is defined as Y. At this time, the emitter contact ratio (emitter bypass ratio) e is given by Equation 4 as described above.

As shown in FIG. 43, the semiconductor substrate 220
On the upper main surface of the first embodiment, the length of the portion where the high-concentration p-type semiconductor region 32a is interposed between the n-type emitter region 4a and the n-type epitaxial layer 2 is H, without the high-concentration p-type semiconductor region 32a. Let L be the length of the part isolated only by the p-type base region 3. As described above, the high gate threshold voltage area ratio g
Is given by Equation 5 based on these H and L.

When the emitter contact ratio e is reduced, the area of the n-type emitter region 4a is reduced, so that the emitter resistance of the n-type emitter region 4a is reduced. This is equivalent to an increase in the source resistance equivalently connected in series in the MOSFET region.
This is a factor that suppresses the electron current in the FET region. As a result, it is expected that the short-circuit current of the IGBT is reduced, and as a result, the short-circuit withstand capability is improved. On the other hand, when the high gate threshold voltage region ratio g is increased, the short-circuit current is suppressed as described above, and the short-circuit withstand capability is improved.

In the IGBT 200a shown in FIG.
When the mutual ratio of the widths X and Y is changed, the mutual ratio of the lengths H and L also changes in substantially the same manner. That is,
When the emitter contact ratio e is increased, the high gate threshold voltage region ratio g is increased in substantially the same manner. That is, by measuring the short-circuit tolerance of the IGBT 200a while changing the ratio of the widths X and Y and the ratio of the lengths H and L accordingly, the emitter contact ratio e decreases and the high gate threshold voltage region ratio g increases. It is possible to determine which one more effectively contributes to the improvement of the short-circuit withstand capability between the increase in.

FIG. 44 shows the IGBT 200a shown in FIG.
7 is a graph showing the results of actual measurements on the dependence of the collector-emitter saturation voltage V _CE (sat), the saturation current density (load short-circuit current density) J _CE (sat), and the short-circuit tolerance tw on the emitter contact ratio e in FIG. Although not shown in the figure, as described above, the high gate threshold voltage region ratio g similarly increases and decreases as the emitter contact ratio e increases and decreases. Note that the collector-emitter voltage V _CE and the collector current I
The rated values of _CE are 600 V and 100 A, respectively.

As the emitter contact ratio e increases, the collector-emitter saturation voltage V _CE (sat) has a minimum value, and the saturation current density J _CE (sat) has a maximum value. on the other hand,
As the emitter contact ratio e increases, the short-circuit withstand capability tw monotonously decreases while showing a saturation tendency. In the region where the emitter contact ratio e is high, the emitter contact ratio e
, The saturation current density J _CE (sat) decreases. That is, in this region, the high gate threshold voltage region ratio g is stronger than the emitter contact ratio e, and the saturation current density J _CE (sat)
It can be understood that it governs the size of. However, it should be noted that, even in this region, the short-circuit tolerance tw shows a decreasing tendency with an increase in the emitter contact ratio e. This indicates that the emitter contact ratio e has a greater effect on the short-circuit tolerance tw than the high gate threshold voltage region ratio g. Therefore, in order to obtain the required short-circuit tolerance tw, it is more effective to set the emitter contact ratio e lower than to increase the high gate threshold voltage region ratio g.

The magnitude of the short-circuit withstand capability tw required for practical use is 10 μsec or more. With an allowance of 2 μsec for this value, 12 μsec is a practical lower limit value of the short-circuit tolerance tw. In the graph of FIG. 44, tw = 12 μ
sec corresponds to e = 25%. Therefore, if the emitter contact ratio e is 25% or less, a practically required short-circuit withstand capability tw can be obtained. On the other hand, the value of the collector-emitter saturation voltage V _CE (sat) also has a practically preferable upper limit, which is about 2.4 V. In the graph of FIG. 44, the emitter contact ratio e corresponding to the value of the collector-emitter saturation voltage V _CE (sat) is 5%. Therefore, the practically required lower limit of the emitter contact ratio e is 5%.

The result shown in FIG. 44 that the emitter contact ratio e strongly affects the short-circuit tolerance tw predicts a more general conclusion that the emitter resistance strongly affects the short-circuit tolerance tw. FIG. 45 is a graph showing actual measurement results that proved this. That is, FIG.
In contrast to the IGBT 200a having a constant structure in which the collector-emitter saturation voltage V _CE (sat) shown in FIG. Area 4
The measurement result of each characteristic amount when the value of the sheet resistance in a is variously changed is shown. As predicted above, the short-circuit tolerance tw
Strongly depends on the sheet resistance. That is, as the sheet resistance of the n-type emitter region 4a increases, the short-circuit tolerance tw increases in a substantially directly proportional relationship. The saturation current density J _CE (sat) also shows a decreasing tendency as expected. On the other hand, the collector-emitter saturation voltage V _CE (sat) hardly depends on the sheet resistance. Therefore, by setting the sheet resistance of the n-type emitter region 4a high, it is possible to reduce the short-circuit withstand capability tw to a required level without substantially affecting the loss during normal operation of the device.

In the graph of FIG. 45, the value of the sheet resistance corresponding to 10 μsec, which is the value of the short-circuit withstand capability tw required practically, is 40 Ω / □. The sheet resistance corresponding to 2.4 V, which is a practically required value for the collector-emitter saturation voltage V _CE (sat), is 150Ω / □.
It is. Therefore, a practically desirable sheet resistance value is in the range of 40Ω / □ to 150Ω / □. More preferably, it is good to set in the range of 60Ω / □ to 120Ω / □.

If the sheet resistance of the n-type emitter region 4a is set high, the transition time when the device is turned off and turned on becomes long, causing a problem that the loss accompanying the switching operation of the device slightly increases. For this reason,
Preferably, the transition time is shortened by lowering the resistance value of the gate electrode 6. In order to reduce the resistance of the gate electrode 6 formed of polysilicon, it is preferable to introduce an n-type impurity such as arsenic. FIG. 46 is a graph showing the relationship between the sheet resistance of the polysilicon gate electrode 6 and the loss due to turn-on of the device, obtained by actual measurement. FIG. 46 shows that the loss decreases as the sheet resistance decreases. The upper limit of the loss required for practical use is about 5.6 mJ / pulse. In FIG. 46, the value of the sheet resistance corresponding to this value is 250Ω / □. Therefore, a practically preferable sheet resistance value is 250Ω.
/ □ The range is as follows. More preferably, 200Ω / □
It is better to set in the following range.

<Manufacturing Method of IGBT>
Regarding the method of manufacturing the BT, the IGBT 200 shown in FIG.
An IGBT 200 having the same cross-sectional shape as described above will be described as an example.

<Example 1 of Manufacturing Method>> Fig. 47 shows IGBT2
00 at a certain stage of the first example of the manufacturing process
FIG. 3 is a cross-sectional view of the T unit cell 210 taken along line B1-B1. The manufacturing process of the IGBT 200 of this embodiment will be described with reference to FIG.

First, the IGBT which is the device of the first embodiment
A process similar to the manufacturing process shown in FIGS. Next, the process proceeds to the step shown in FIG. 47, and first, the polysilicon gate electrode 6 and the silicon oxide
A resist layer is provided on the entire surface of the substrate. Photolithography of the resist layer is performed using a mask 82 having a mask pattern 56 similar to the mask pattern 54 shown in FIG. 1, thereby obtaining a resist pattern 83 corresponding to the mask pattern 56. Further, using the resist pattern 83 as a mask, a predetermined amount of arsenic is selectively implanted into the gate electrode 6 to reduce the sheet resistance of the gate electrode 6 in advance.
After removing the resist pattern 83, the same steps as those shown in FIGS. 16 to 21 are performed.

In the steps shown in FIGS. 18 and 19, an impurity is again introduced into gate electrode 6 simultaneously with the upper main surface of semiconductor substrate 1. At this time, the amount of impurity to be introduced is determined by setting a predetermined n-type emitter region
Is set to form Therefore, the amount of impurities introduced into gate electrode 6 in the step shown in FIG. 47 is adjusted in advance so that the sheet resistance of gate electrode 6 after all the steps have a predetermined value.

<Example 2 of manufacturing method>> Fig. 48 shows IGBT2
00 at a certain stage of the second example of the manufacturing method
FIG. 3 is a cross-sectional view of the T unit cell 210 taken along line B1-B1. The manufacturing process of the IGBT 200 of this embodiment will be described with reference to FIG.

First, the IGBT which is the device of the first embodiment
A process similar to the manufacturing process shown in FIGS. Next, the process proceeds to the step shown in FIG. 48. First, a resist layer is provided on the entire surface of the polysilicon gate electrode 6 and the oxide film 71 (that is, the gate insulating film 5 and the oxide film pattern 80 remaining in the central area). A mask pattern 56 similar to the mask pattern 54 shown in FIG.
Photolithography of the resist layer is performed using a mask 82 having a mask pattern 56, thereby obtaining a resist pattern 83 corresponding to the mask pattern 56. Further, a predetermined amount of arsenic is selectively implanted into the gate electrode 6 using the resist pattern 83 as a mask to reduce the sheet resistance of the gate electrode 6. After removing the resist pattern 83, the same steps as those shown in FIGS. 20 and 21 are performed.

In the steps shown in FIGS. 18 and 19, impurities are previously introduced into gate electrode 6 simultaneously with the upper main surface of semiconductor substrate 1. The amount of impurity introduced at this time is set so as to form a predetermined n-type emitter region 4 on the upper main surface of semiconductor substrate 1. Therefore, FIG.
Is adjusted so that the sheet resistance of the gate electrode 6 becomes a predetermined value after all the steps are completed.

<Example 3 of manufacturing method>> FIG. 49 shows IGBT2
00 at a certain stage of the third example of the manufacturing method
FIG. 4 is a sectional view of a T unit cell 210. The manufacturing process of the IGBT 200 of this embodiment will be described with reference to FIG.

First, the IGBT which is the device of the first embodiment
A process similar to the manufacturing process shown in FIGS. Next, the process proceeds to the step shown in FIG. 49, and first, a polysilicon gate electrode 6 is provided on the entire surface of the oxide film 71. Next, a predetermined amount of arsenic is implanted into the entire area of the gate electrode 6 to reduce the sheet resistance of the gate electrode 6 in advance. Thereafter, the same steps as those shown in FIGS. 10 to 21 are performed.

In the steps shown in FIGS. 18 and 19, impurities are again introduced into gate electrode 6 simultaneously with the upper main surface of semiconductor substrate 1. At this time, the amount of impurity to be introduced is determined by setting a predetermined n-type emitter region
Is set to form Therefore, the amount of impurities introduced into gate electrode 6 in the step shown in FIG. 49 is adjusted in advance so that the sheet resistance of gate electrode 6 after all the steps are attained to a predetermined value.

Instead of introducing impurities into gate electrode 6 by the process of FIG. 49, gate electrode 6 may be formed using polysilicon (doped polysilicon) doped with an impurity such as phosphorus in advance. At this time,
The concentration of the impurity to be doped is adjusted in advance so that the sheet resistance of the gate electrode 6 after completing all the steps has a predetermined value.

[0131]

According to the gate insulating semiconductor device of the present invention, the section where the inversion layer is to be formed is the gate threshold voltage V _GE
(th) The structure has a structure in which a low part and a high part are connected in parallel in an electric circuit. Therefore, the collector-emitter saturation voltage V _CE (sat) can be reduced by miniaturizing or densifying the device and optimizing the distribution of the high and low portions of the gate threshold voltage V _GE (th). There is an effect that a device having a high short-circuit tolerance can be obtained by reducing the saturation current I _CE (sat) while reducing the loss by lowering the loss . Only
Also, the third semiconductor region has a first portion and a second portion.
Alternatively, the first main electrode layer is formed in the central area of the fourth semiconductor region.
And a portion protruding inside the third semiconductor region.
Connected to the second part. This allows the first
The connection between the main electrode layer and the third semiconductor region is
Guarantees high accuracy in turn alignment
Thus, miniaturization of the device is facilitated. In addition, the gate threshold
The outer area where the voltage V _GE (th) is selectively high is the second area
The second position of the carrier is
Concentration on the part is effectively mitigated, so that the second
Deterioration of short-circuit withstand capability due to the provision of
It is. Thus, the fourth semiconductor region is shifted to the outer area.
The advantage of protruding is reduced by the second part
Without short-circuit, resulting in high short-circuit resistance
The amount is obtained effectively (claim 1 ) .

Further , the second portion connects the pair of first portions with each other.
And the first part and the second part are ladder-shaped as a whole.
Because of the pattern shape, the first main electrode and the third main electrode
Necessary for ensuring the connection to the semiconductor layer
The accuracy of mask pattern alignment has been further relaxed
You. Thereby, miniaturization of the device is further facilitated.
(Claim 2). Further, the ratio of the third semiconductor region and the fourth semiconductor region electrically connected to the first main electrode layer is optimized.
Since it is the saturation current I _CE (sat) is reduced, thus even greater short-circuit tolerance is obtained (claim 3).

Further , the proportion of the channel having a relatively high gate threshold voltage V _GE (th) to the whole channel
To is optimized, the saturation current I _CE (sat) is reduced, thus a large short-circuit withstand capability can be obtained more (claim
5 ).

[0134] In the production method in the present invention, that-out <br/> in that to produce the insulated gate semiconductor device having the above advantages (Claim 8～10,12).

In the gate insulating type semiconductor device according to the present invention,
The value of the sheet resistance of the third semiconductor region is 40Ω / □ to 1
It is in the range of 50Ω / □ (claim 6) .

[0136] For this reason, 10μsec to be practical request
Together is ensured more short-circuit tolerance, even for the collector-emitter saturation voltage V _CE (sat), practical value is obtained <br/> is Ru.

In the gate insulating type semiconductor device according to the present invention,
For the value of the sheet resistance of the control electrode layer is 250 [Omega] / □ or less, that could be practically low switching loss to the extent that can meet the practical requirements (claim 7).

In the gate insulating semiconductor device of the present invention,
Emitter contact (emitter bypass) rate is 5% to 2
Since it is 5%, a practical 10 μ
At the same time sec or more short-circuit tolerance is ensured, Ru practically low value obtained for the collector-emitter saturation voltage V _CE (sat) (claim 4). In the manufacturing method of this invention, it is possible to effectively manufacture the insulated gate semiconductor device according to claim 4, 6, and 7 (claim 11, 1
3 to 17 ).

[Brief description of the drawings]

FIG. 1 is an N-channel IGBT according to a first embodiment of the present invention;
It is a top view which shows the structure of.

FIG. 2 is a sectional view taken along line A1-A1 of FIG.

FIG. 3 is a sectional view taken along line B1-B1 in FIG. 1;

FIG. 4 is a plan view showing a structure of an N-channel IGBT according to a modification of the first embodiment of the present invention.

FIG. 5 is a sectional view taken along line A1a-A1a in FIG.

FIG. 6 is a sectional view taken along line C1a-C1a in FIG. 4;

FIG. 7 is a graph illustrating actual measurement results in the IGBT of FIGS. 4 to 6;

FIG. 8 is a sectional view showing a manufacturing process of the IGBT of FIG. 1;

FIG. 9 is a sectional view showing a manufacturing process of the IGBT of FIG. 1;

FIG. 10 is a sectional view showing a manufacturing step of the IGBT of FIG. 1;

FIG. 11 is a sectional view showing a manufacturing process of the IGBT of FIG. 1;

FIG. 12 is a sectional view showing a manufacturing process of the IGBT of FIG. 1;

FIG. 13 is a sectional view showing a manufacturing process of the IGBT of FIG. 1;

FIG. 14 is a sectional view showing a manufacturing process of the IGBT of FIG. 1;

FIG. 15 is a sectional view showing a manufacturing step of the IGBT of FIG. 1;

FIG. 16 is a sectional view showing a manufacturing process of the IGBT of FIG. 1;

FIG. 17 is a cross-sectional view showing a manufacturing step of the IGBT of FIG. 1;

FIG. 18 is a cross-sectional view showing a manufacturing step of the IGBT of FIG. 1;

FIG. 19 is a cross-sectional view showing a manufacturing step of the IGBT of FIG. 1;

FIG. 20 is a cross-sectional view showing a step of manufacturing the IGBT of FIG. 1;

FIG. 21 is a cross-sectional view showing a manufacturing step of the IGBT of FIG. 1;

FIG. 22 is an N-channel type IGB according to a second embodiment of the present invention;
It is a top view showing the structure of T.

FIG. 23 is a sectional view taken along line A2-A2 in FIG.

FIG. 24 is a cross-sectional view showing a step of manufacturing the IGBT of FIG. 18;

FIG. 25 is a cross-sectional view showing a manufacturing step of the IGBT of FIG. 18;

FIG. 26 is an N-channel type IGB according to a third embodiment of the present invention;
It is a top view showing the structure of T.

FIG. 27 is a sectional view taken along line A3-A3 in FIG.

FIG. 28 is a sectional view taken along line B3-B3 in FIG.

FIG. 29 is a cross-sectional view showing a manufacturing step of the IGBT of FIG. 22;

FIG. 30 is a cross-sectional view showing a manufacturing step of the IGBT of FIG. 22;

FIG. 31 is a cross-sectional view showing a manufacturing step of the IGBT of FIG. 22;

FIG. 32 is a sectional view showing the manufacturing process of the IGBT of FIG. 22;

FIG. 33 is a cross-sectional view showing a step of manufacturing the IGBT of FIG. 22;

FIG. 34 is a cross-sectional view showing a manufacturing step of the IGBT of FIG. 22;

FIG. 35 is an N-channel type IGB according to a fourth embodiment of the present invention;
It is a top view showing the structure of T.

36 is a sectional view taken along line A4-A4 in FIG.

FIG. 37 is a sectional view showing the manufacturing process of the IGBT of FIG. 35;

FIG. 38 is a cross-sectional view showing a step of manufacturing the IGBT of FIG. 35;

FIG. 39 is a front sectional view showing a structure of an N-channel IGBT according to a modification of the present invention.

FIG. 40 is a plan view showing the structure of a conventional N-channel IGBT.

FIG. 41 is a sectional view taken along the line AA of FIG. 40;

FIG. 42 is a sectional view taken along the line BB of FIG. 40;

FIG. 43 shows an N-channel IG according to an embodiment of the present invention.
It is a top view which shows the structure of BT.

FIG. 44 is a graph showing the relationship between various characteristics and the emitter contact ratio e in the example of the present invention.

FIG. 45 is a graph showing the relationship between various characteristics and the sheet resistance of the n-type emitter region in the example of the present invention.

FIG. 46 is a graph showing the relationship between the turn-on loss and the sheet resistance of the gate electrode 6 in the example of the present invention.

FIG. 47 is a cross-sectional view showing a manufacturing step of the IGBT of Embodiment 5 of the present invention;

FIG. 48 is a cross-sectional view showing a manufacturing step of the IGBT of Embodiment 5 of the present invention;

FIG. 49 is a cross-sectional view showing a manufacturing step of the IGBT of Embodiment 5 of the present invention;

[Explanation of symbols]

 Reference Signs List 1 p-type collector layer 2 n-type epitaxial layer 3 p-type base region 4 n-type emitter region 4 a n-type emitter region 5 gate insulating film 6 gate electrode 6 a opening 6 b opening end 7 emitter electrode 8 oxide film 8 a opening 8 b opening end 9 Collector electrode 31 High concentration p-type semiconductor region 32 High concentration p-type semiconductor region 32a High concentration p-type semiconductor region 33 High concentration p-type semiconductor region 34 High concentration p-type semiconductor region 35 High concentration p-type semiconductor region 36 High concentration p-type Semiconductor region 51 Mask pattern 52 Mask pattern 53 Mask pattern 53a Mask pattern 54 Mask pattern 54a Mask pattern 55 Mask pattern 56 Mask pattern 57 Mask pattern 71 Silicon oxide film 73 Resist pattern 74 P-type semiconductor region 76 Resist pattern 77 High-concentration p-type Conductive region 79 Resist pattern 80 Oxide film pattern 83 Resist pattern 84 High concentration p-type semiconductor region 86 Resist pattern 87 High concentration p-type semiconductor region 88 High concentration p-type semiconductor region 89 High concentration p-type semiconductor region 90 High concentration p-type semiconductor region 220 Semiconductor substrate S1 Lower main surface CA Central area BA Strip area WD Opening

────────────────────────────────────────────────── ─── of the front page continued (56) reference Patent Sho 60-254658 (JP, a) JP Akira 62-266871 (JP, a) (58 ) investigated the field (Int.Cl. ^6, DB name) H01L 29/78 H01L 21/336

Claims (17)

(57) [Claims] 1. A gate-insulated semiconductor device comprising the following (a) to (e). Defines (a) a top major surface and a lower major surface, the semiconductor substrate comprises the following from (a-1) (a- 4): exposed to the upper main surface of (a-1) the semiconductor body, (A-2) a second semiconductor type selectively formed on an upper surface portion of the first semiconductor region and selectively exposed on the upper main surface of the semiconductor substrate; a second semiconductor region of; (a-3) selectively formed on the upper surface portion of said second semiconductor region, wherein on said upper major surface of the semiconductor substrate, the side of the exposed surface of said second semiconductor region in the inner edge portion, the first part of the pair that extend in parallel and strip away from each other
Minutes and from each of the pair of first parts toward the other
A third portion of the first conductivity type having
Semiconductor region; (a-4) a second conductivity type, higher than the concentration of the impurity for forming the second conductivity type is the second semiconductor region,
The semiconductor device is selectively formed on an upper surface portion of the semiconductor base so as to include the third semiconductor region .
A region excluding the second portion in the region sandwiched between
In that central area, exposed upper major surface of said semiconductor body
As well as, before toward the outside of the pair of first portion
A region projecting from each of the first portions,
In the outer area where the position matches the projecting position of the second part
A fourth semiconductor region exposed on an upper main surface of the semiconductor substrate; (b) selectively formed on the upper main surface of the semiconductor substrate, and at least a part of the second portion and the fourth semiconductor region; An insulating layer having an opening on a predetermined region covering at least a part of the central area; (c) the pair of first parts embedded in the insulating layer;
The control electrode layer opposes to the interval between the minute and the exposed surface of said first semiconductor region; (d) are formed in said opening, the opening of the upper major surface of said semiconductor body a first main electrode layer electrically connected to the portion exposed; (e) wherein the lower main surface and the second main electrode layer electrically connected to the semiconductor substrate. 2. The second portion is between the pair of first portions.
Are connected in a cross-linking manner to form the pair of first portions.
And the second portion have a ladder-like pattern shape as a whole.
2. The gate-insulated semiconductor device according to claim 1, wherein
Place. 3. The ratio of the area of the third semiconductor region exposed to the opening to the area of the opening is 5%.
Or less 0%, insulated gate semiconductor device according to 請 Motomeko 1 or claim 2. 4. 25% to the proportion from 5%請
The gate-insulated semiconductor device according to claim 3. Wherein Oite on said main surface of said semiconductor body,
In the outer edge of the pair of first portions, wherein the ratio of outer area occupied by the adjacent portions is 20% or more, according to any of 請 <br/> Motomeko 1 to claim 4 Gate-insulated semiconductor device. 6. A sheet resistance value of said third semiconductor region is 1 at 50 [Omega / □ to 40 [Omega / □ no claims 1
A gate insulating semiconductor device according to claim 5 . The value of the sheet resistance of wherein the control electrode layer, 2
7. The method according to claim 1, wherein the resistance is 50 Ω / □ or less.
2. A gate-insulated semiconductor device according to claim 1 . 8. A method for manufacturing a gate insulating semiconductor device comprising the following steps (a) to (o). (A) defining an upper main surface and a lower main surface, and exposing the upper main surface
Semiconductor base body having a first semiconductor region of a first conductivity type that
Obtaining a; selectively having <br/> (c) a first opening strip-like over the insulating film; (b) the step of forming an insulating film on the upper major surface of the semiconductor substrate Forming a control electrode layer; (d) selectively introducing an impurity of a second conductivity type into an upper main surface of the semiconductor substrate through the first opening to form a second semiconductor region of a second conductivity type forming a step; (e) selectively to diffuse the previous SL impurity introduced in the step (d) in said first semiconductor region, due to its
A second opening only a part of (f) opening the mouth end located in said first opening; Te, step to widen the front Stories second semiconductor region to below the previous SL control electrode layer possess the selected 択的, a shielding film for preventing the introduction of impurities, on the insulating film in the first opening
A step provided on said control electrode layer; the <br/> on a main surface of (g) the semiconductor body through said second opening, than the concentration of impurity introduced in the step (d) Forming a third semiconductor region of the second conductivity type by selectively introducing a high concentration of impurities of the second conductivity type; (h) removing the shielding film; pre Symbol impurity introduced in (g) selectively diffused into the semiconductor body, whereby the
While maintaining a higher impurity concentration than the second semiconductor region,
Said third semiconductor region, as part of their projects to below the control electrode layer, spread Rutotomoni, in the upper main surface of said semiconductor substrate immediately below the first opening corresponds <br/> to that process to expose a region to encompass realm; (j) of the upper main surface of said semiconductor body, in the inside of the region corresponding to the right under the first opening, Apart from each other
And a pair of first portions extending in parallel and in a band shape,
Protruding from each of the first portions of the
The third semiconductor region is located in front of the third semiconductor region.
A position matching the position protruding downward from the control electrode layer.
And two portions, below the first opening
By selectively removing the insulating film, the pair is removed.
Exposing the upper major surface of said semiconductor body in the first portion and the second portion of, sandwiched between the pair of first portion
The central area, which is the area excluding the second part in the area
The A step leaving the insulating film; using said insulating film existing under the insulating film and the control electrode layer remaining (k) the central area as a mask, the upper major surface of said semiconductor body A step of selectively introducing an impurity of a first conductivity type to form a fourth semiconductor region of a first conductivity type in the third semiconductor region; (l) removing the insulating film remaining in the central area; step of removing; (m) of the upper main surface of said semiconductor substrate, said second part
Min and at least a portion step wherein at least part of the central area, selectively has a third opening over the, an insulating layer covering the side and top surfaces of said control electrode layer; (n A) providing in the third opening a first main electrode layer electrically connected to a portion of the upper main surface of the semiconductor substrate that is exposed to the third opening; the step of forming the lower major surface and a second main electrode layer electrically connected to the semiconductor substrate on the lower major surface of the semiconductor substrate. 9. The method according to claim 9, wherein the second portion is between the pair of first portions.
Are connected in a cross-linking manner to form the pair of first portions.
And the second portion have a ladder-like pattern shape as a whole.
9. The gate-insulated semiconductor device according to claim 8, wherein
Manufacturing method . 10. An area corresponding to the area of the third opening.
Occupied by the fourth semiconductor region exposed in the third opening
Step (j) so that the area ratio is 50% or less.
In the step (m), selectively removing the insulating film in
Or the formation of the insulating layer is performed.
A method for manufacturing a gate insulating semiconductor device according to claim 9 . 11. The method according to claim 1, wherein the ratio is 5% to 25%.
Thus, the selective removal of the insulating film in the step (j)
And forming the insulating layer in the step (m) is performed.
11. The production of the gate insulating semiconductor device according to claim 10, wherein
Construction method . 12. The semiconductor device according to claim 1 , wherein said upper main surface of said semiconductor substrate is provided.
And the third outer part of the pair of first portions is located within the outer edge.
Where the semiconductor region protrudes below the control electrode layer
So that the ratio of adjacent parts is 20% or more,
The selective diffusion of the impurity in the step (i) is performed.
The game according to any one of claims 8 to 11,
A method for manufacturing a heat-insulated semiconductor device . 13. The first conductive material introduced in the step (k).
The impurity in the form of a sheet resistance of the fourth semiconductor region
Introduced so that the value is between 40Ω / □ and 150Ω / □
The method according to any one of claims 8 to 12, wherein
A method for manufacturing a gate insulating semiconductor device . 14. The control formed in the step (c).
The electrode layer contains a polycrystalline semiconductor, and the manufacturing method includes: (p) using the shielding film as a first shielding film;
After step (j) and before step (j), the introduction of impurities is prevented ;
Forming a second shielding film covering the first opening portion on the insulating film ;
To the use of (q) the second shielding film as a mask; a step of providing on
The method further comprising: selectively introducing an impurity of the first conductivity type into the control electrode layer; and ( r ) removing the second shielding film before the step (j) . The impurities of the first conductivity type introduced in the step (k)
Is also introduced into the control electrode layer at the same time, and is introduced in the step (q).
Is, after both of the step (q) and the step (k), the value of the sheet resistance of said control electrode layer is 250 [Omega] /
□ The gel according to claim 13, which is introduced so as to be:
A method for manufacturing a heat-insulated semiconductor device . 15. The control formed in the step (c).
The electrode layer includes a polycrystalline semiconductor, and the impurity of the first conductivity type introduced in the step (k) is introduced.
Is simultaneously introduced into the control electrode layer, and the manufacturing method includes: (p) using the shielding film as a first shielding film;
After and before step (l), the introduction of impurities is prevented ;
A second shielding film covering the first opening is provided on the first opening;
A portion of the upper main surface of the semiconductor substrate exposed to the portion and the
To the use of (q) the second shielding film as a mask; step of providing on a portion of the insulating film
More, the value of the sheet resistance of said control electrode layer is 250 [Omega] / □
As the following step of selectively introducing an impurity of the first conductivity type into said control electrode layer; prior to and (r) said step (l), removing the second shield layer; the The gate insulating semiconductor according to claim 13, further comprising:
Device manufacturing method . 16. wherein step (c), (c-1) wherein become under the control electrode layer on the insulating film multi
A step of introducing a first conductivity type impurity into (c-2) the material; the material including a crystalline semiconductor forming a layer and a first opening strip shaped to (c-3) said material particular form
Thus, the step of forming the control electrode layer; wherein the impurity of the first conductivity type which is introduced in said step (k)
Is simultaneously introduced into the control electrode layer, and the impurity of the first conductivity type introduced in the step (c-2) is introduced.
Is, after both of the step (c-2) and the step (k), the value of the sheet resistance of said control electrode layer is 250 [Omega] /
□ The gel according to claim 13, which is introduced so as to be:
A method for manufacturing a heat-insulated semiconductor device . 17. wherein step (c), (c-1) Multi impurity of the first conductivity type is introduced in advance
The material of the control electrode layers including a crystalline semiconductor, the step of forming on the insulating <br/> film layered; and, forming a first opening in the substantially strip-shaped (c-2) the material step; wherein the impurity of the first conductivity type which is introduced in said step (k)
Is simultaneously introduced into the control electrode layer, and the concentration of the impurity of the first conductivity type, which is previously introduced into the material formed in the step (c-1) , is
The gate according to claim 13 , wherein after both (c-1) and the step (k) , the value of the sheet resistance of the control electrode layer is set to be 250 Ω / □ or less. Insulation type semi
A method for manufacturing a conductor device .