JPS59110165A - Semiconductor device - Google Patents

Abstract

PURPOSE:To improve the current amplification rate and the characteristic of turn-off time by a method wherein a ring form or many diffusion form regions of the same conductivity type as that of the emitter is provided in the base region outside the ring emitter, and this region is connected to a base electrode. CONSTITUTION:The base region 2 and the emitter region 3 are formed in a substrate 1, and a surface base-emitter junction is protected with an oxide film 4. A base and an emitter electrode 5 and 8 are formed at an aperture. In such a planar structure, the forth regio 31a and 31b of a single or a plurality of layers and the fifth regions 32a-32c of the same structure are provided. The forth and fifth regions face the planar main surface, and are formed with the same conductivity type as that of the emitter 3. Besides, the forth region 4 is so formed as to block the carrier injection into the side surface of the emitter 3, and the fifth region exists outside the forth region and is connected to the base electrode 5, thus acting to reduce the base resistance. By constituting in such a manner, the current amplification rate can be increased, while the turn-off time is reduced.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a ring emitter structure for a planar semiconductor device, and particularly to a semiconductor device that has been improved to have a short switching time and a high current amplification factor. be.

[Technical background of the invention]

A ring emitter structure for a Brenna type semiconductor device is proposed in Japanese Patent Publication No. 1632/1983. This ring emitter structure was developed by improving the previously known base-type semiconductor device (i.e., the structure 9 consisting of a substrate 1, a space region 2, an emitter region 6, and an oxide film 4 as shown in FIG. 1). As shown in the figure, a ring-shaped diffusion region 6 of the same conductivity type as the emitter is provided between the emitter 6 and the base electrode 5 in the base region 2. According to this ring emitter structure, the emitter surface Injection of carriers from the sides is prevented, and carrier injection occurs only from the bottom surface 6a of the emitter.As a result, the injection efficiency of the emitter is improved, current amplification factors hJ and E increase, and surface carrier This has the advantage of reducing low frequency noise due to injection.

However, although the conventional ring emitter structure shown in FIG. 2 has the above-mentioned advantages, it has a drawback in that its switching characteristics are worse than the planar structure shown in FIG. That is, looking at the turn-off operation in the NPN transistor shown in Figures 1 and 2, in the on state, holes (.marked 9) and electrons (.marked) exist as excess carriers in the base region 2. However, it is impossible to turn it off instantly.The reason is the high current amplification factor hF]
,.

The reason is that the base region is made to have a low impurity concentration in order to obtain this. In particular, in the ring emitter structure shown in Figure 2, the first
Fig. Width of the base under the ring emitter W than the planar structure
The base resistance increases due to B, and the amount of excess carriers increases by the amount accumulated under the ring emitter. Therefore, the ring emitter structure shown in FIG. 2 tends to have a longer turn-off time (both accumulation time 1 and fall time t) than the planar structure shown in FIG.

[Purpose of the invention]

An object of the present invention is to provide a planar semiconductor device with a high hFE in the on state, short ts and tf in the Kuhn-off state, and a high BvEBo, so that the switching time is short and the current amplification factor is large. It is an object of the present invention to provide an improved structure as described above, and to provide such an improved structure that can be easily manufactured using conventional manufacturing processes.

[Summary of the invention]

In short, the present invention provides a planar ring emitter improved structure characterized in that an annular or multi-dispersed region of the same conductivity type as the emitter is provided in the outer base region of the ring emitter, and this region is connected to the base electrode. It is a type semiconductor device. This results in high hFF and short 18.
1f. The tank bottom and its operation will be explained in detail below with reference to FIGS. 6-5.

3 to 5, an N-type substrate 1 (third region), a haze region 2 (second region) and an emitter region 6 (first region) are shown.
is formed, and the surface-based emitter junction is formed using an oxide film 4.
A base electrode 5 and an emitter electrode 8 are formed in the opening. In such a planar structure, the present invention provides a fourth region of one or more layers (two layers 31a and 31b in the figure) and a fifth region of one or more layers.
The fourth region and the fifth region face the planar main surface and are formed of the same conductivity type as the emitter.
The regions are formed to prevent carrier injection into the side surfaces of the emitter, and the fifth region is located outside the fourth region and is connected to the base electrode 5, serving to reduce the base resistance.

FIG. 6 is an explanatory diagram of the on state, in which holes (marked with 0) injected from the base electrode 5 are injected into the emitter layer 6 from the emitter bottom 6a all the way under the layers of the fourth regions 31a and 31b. Emi,
At the bottom 6a, the ND/NAc ratio (ND: donor concentration, N
The injection efficiency is improved due to the large Ao concentration and the high hFE.

FIG. 4 is an explanatory diagram at the time of turn-off, in which the reverse bias flows out to the base electrode 5 through the forward biased P-N+ junctions of the fifth regions 32a, 32b, and 32c and the low resistance furnace layer. Therefore, holes flow out more quickly than in the case of the conventional structure of FIGS. 1 and 2 which does not have the fifth region as in the present invention, and as a result, t's and t are significantly shortened.

FIG. 5 is a diagram illustrating the case of a reverse bias. When a reverse bias is applied, the fourth regions 31a and 31b are formed by promoting the development of a surface depletion layer and by expanding a depletion layer 51 toward the base region.

In this way, in the fourth region and the fifth region not connected to the base electrode, the development of the depletion layer is promoted and the surface electric field is weakened, so that BvF and Bo are higher than in the conventional structure shown in FIGS. 1 and 2. Therefore, the Kuhn-off signal voltage can be increased, and the turn-off time can also be shortened from this point of view. This can be used extremely effectively especially in a gate turn-off thyristor (CGTO) which requires a high reverse breakdown voltage between the gate and cathode.

[Embodiments of the invention]

Examples of the present invention will be described below. In the drawings of the embodiment, the parts indicated by the same reference numerals as those in the drawings of the conventional example are the same parts as the parts of the conventional example, and therefore the explanation thereof will be omitted.

FIG. 6 is a plan view of the element of the first embodiment. In the figure, annular fourth regions 61a and 61b are formed surrounding the emitter 6, and an annular fifth region 62 is formed outside of the fourth regions 61b, and the fifth region 62 is connected to the base electrode 5.

The manufacturing of the semiconductor device of the first embodiment is shown in FIGS. 7(a) to (e).
) The emitter region 6 and the fourth and fifth regions can be formed at the same time. That is, first, a wafer is prepared as shown in FIG.
+ layer 72 has a donor concentration of 10×1021an-32 and a layer thickness of 1
60 μm). Next, in FIG. 2B, a first oxide film 76 is formed, an etching opening is made, and low concentration diffusion is performed to form the base layer 2 and the HIFIEL 1 annealing layer 74.
(base surface resistance is approximately 65 Ω/hole, base surface acceptor concentration is approximately 7.0×10 an , and Heiss diffusion depth X3P is approximately 301 i′n′L). Next, in the same figure (C), a second oxide film 75 is formed, an etching opening is made, N+ diffusion is performed, and the emitter 6 and the fourth region 61 are
a: "61b and the fifth regions 62a and 62b are formed at the same time (surface donor concentration is 5 x 1020 cm-3, diffusion depth XjN+ is about 15 μm).

Next, in the same figure (d), a third oxide film 76 is formed,
The etching opening is made and the emitter plate 8 is etched in the figure (e).
and the base electrode 5 is formed. As shown, the fifth regions 62a, 62b are connected to the base electrode.

FIG. 8 shows the impurity profile of the first embodiment shown in FIGS. 6 and 7.

9 and 10 are enlarged views of essential parts for explaining the criteria for determining the dimensions of the fourth and fifth regions of the first embodiment.

(1) The distance between the emitter region 6 and the fourth region 61a is 1□.
1□ is determined by the resistance in the R1 direction and the resistance in the R2 direction shown in the figure. R□ and R2 are expressed by the following formulas (1) and (2), respectively.
).

Here, 1 is the base average resistance from the surface to X, N+,
1 (D = impurity diffusion coefficient, t: diffusion time 9) can be obtained by calculating by applying the numerical values of the first example, and in the above example, LE/2 = 50 μm, and 40 μm, which is 80% of that.
Since it is designed so that the bottom surface up to works as an emitter, it can be set as y = 40 x 10' + 1 □ (cm). If R1>R2, most of ■3 flows to the bottom side of the emitter, so we obtain the relationship 0(1, (4,,9411m), so in the first embodiment, 3□k 5 ltm
And so.

(2) Fourth area 61a and 61b +7) Interval m1, fourth area
The distance m2 between the region 61b and the fifth region 62a is Nz7×1017a-3, and the one-sided staircase joint is temporarily AC
, S, the breakdown voltage is approximately 10'V. The spread of the depletion layer at this time is about 1 to 2 .mu.m, so in the first embodiment, the width is set to 2 .mu.m. ml
.

m2 can be made wider as NAC,S decreases.

(3) Layer dimensions of each region d In the example, d
1 night 30 μm, d2 each 20 μ”, d3 = 40 pm
Toshi fc.

As described above, the semiconductor device of the present invention can be manufactured using a short 18,1. High hFE dog BVEB
o biho-latrandisk or GTo can be easily produced. Of course, if desired, the fourth and fifth regions may be diffused separately from the ↓ shemitter diffusion.

FIG. 11 shows a plan view of the second embodiment. The fifth region 66 connected to the base electrode 5 does not surround the fourth region 61b in an annular shape, but is dispersed in large numbers.

FIG. 12 shows a sectional view of a third embodiment applied to a GTO. 64a and 64b are fourth regions, and 65 is a fifth region.

〔Effect of the invention〕

According to the present invention, a planar semiconductor device with the following effects, a high current amplification factor, and a short switching time was obtained.

(1) Improving hFE1 in multi-emitter type power transistors
Regarding the hfe of the emitter islands configured as in the first embodiment, a value of 14.0 to 150 was measured, and when compared with the value of 40 to 5o in the conventional example in FIG. It can be seen that the structure has improved carrier injection efficiency and functions effectively as a ring emitter.

(Monday) According to experiments with Darlington power transistors that reduce turn-off time,
As shown in Table 1, the ts and tf of the structure configured as in the first embodiment are 33%, t,
The time was reduced by 65%.

However, it turns out that shortening too much is not necessarily a good idea. That is, when the inductive load is turned off, the collector emitter surge voltage V. E(surge) is determined by the following equation, and if tf is extremely shortened, a huge surge voltage will be generated and the transistor will be destroyed.

Regarding this point, if the fifth region is configured in a multi-dispersed manner as in the second embodiment, the carrier pull-out effect will be weaker than in the first embodiment, but the turn-off time (1
, +1~ could be shortened by about 30%, and no excessive surge voltage was generated.

(iii) Improvement of emitter-base breakdown voltage By configuring as in the present invention, it was possible to promote the development of the surface depletion layer and weaken the surface electric field. This makes it possible to increase the turn-off signal voltage and shorten the turn-off time. It is also possible to increase the reverse breakdown voltage between the gate and cathode of GTO and other devices.

[Brief explanation of the drawing]

1 and 2 are cross-sectional views of an element explaining the problems of the conventional example, FIGS. 3 to 5 are cross-sectional views of an element explaining the present invention in detail, and FIG. 6 is a cross-sectional view of the element of the first embodiment of the present invention. A plan view of the semiconductor device, FIG. 7 is a manufacturing process diagram of the first embodiment, FIG. 8 is a graph showing the impurity profile of the first embodiment, and FIGS.
0 is a sectional view of a main part of the first embodiment, FIG. 11 is a plan view of a semiconductor device of a second embodiment, and FIG. 12 is a sectional view of a semiconductor device of a third embodiment. 6..First area, 2..Second area, 1,71.72.Third area, 6,61.61a, 61b, 64a, 64b.
= 4th region, 62° 62a, 62b, 66, 6
5--Fifth region, 5. Electrode on i2 region.゛、l! l Figure 1 Figure 2 B Figure 3)? t, ,jd D Go2a
, jll) 318 Fig. 4 Fig. 5 Fig. 6 Fig. 7 Fig. 8 From the king side (lim) Fig. 9 - Fig. 10 Fig. 11 Fig. 12

Claims (1)

[Claims] 1. A first region of the first conductivity type facing the main surface of the semiconductor substrate, a second region of the second conductivity type facing the same main surface and in contact with the first region, and a first conductivity type contacting the second region. In the semiconductor device, a fourth region and a fifth region each facing the main surface and having a first conductivity type are provided in the second region, and the fourth region is a third region of the first conductivity type. A region surrounding the first region within the carrier diffusion length range of the region Shio et al.
The fifth region is an annular or multi-dispersed region outside the fourth region and is a region connected to an electrode provided on the second region, and the first, fourth and fifth regions A semiconductor device characterized in that the region is isolated by a second region.