JPS582457B2 - How to use hand-held equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to semiconductor integrated circuits, and more particularly to integrated injection logic circuits.
The present invention relates to a semiconductor integrated circuit device and a method for manufacturing the same, characterized in that it has improved characteristics of a GIC (hereinafter abbreviated as I2L) and is compatible with conventional bipolar integrated circuits.

Conventional I2L (e.g. ISSCCDiectofTe
The structure that is compatible with the IC of conventional structure (see Chnical Papers '72) is characterized by the structure shown in FIG.

That is, N+ type low resistance buried layers 2, 2' and P+ type isolation region 9 are formed on a P type semiconductor substrate 1 by impurity diffusion, an N type epitaxial layer 3 is formed by epitaxial growth, and then P+ 94,4 ',4'',4
'' and N layers 5.5', 5'' are sequentially formed by impurity diffusion, etc., and windows are opened in the insulator 8 to form electrodes 6, 7.7', 7.
” and so on.

In an IC with a conventional structure, 5''' is the collector contact layer, and 4''' is the collector contact layer.
is the base area, and 5'' is the emitter area.

In addition, I2L in this structure is a lateral PMP transistor (
It is characterized by a structure in which a vertical reverse operation NPN transistor (2' is an emitter, 4' is a base, and 5 is a collector) is integrated (4 is an emitter, 3 is a base, 4' is a collector).

I2L operates as follows.

The N+ type low-resistance buried layer 1 is connected to a low potential (electrodes are not shown because the diagram is complicated).

), when the electrode 6 is set at a high potential, holes are injected from the P layer 4 into the N type epitaxial layer 3.

Then, some of the holes increase the potential of the P layer 4', and in turn N
Electrons are injected from the type epitaxial layer 3 into the P+ layer.

Here, some of the injected electrons recombine with holes within the P+ layer, and the rest reach the N+ layer 5.

However, the conventional structure shown in FIG. 1 has the following drawbacks.

The first drawback is that the forward injection of electrons is small in the NP+ junction consisting of the N-type epitaxial layer 3 and the P+ layer, and the current value taken out to the electrode 7 is small.

(This is because the so-called injection efficiency is low.

) The second drawback is that the carriers injected into the P+ layer 4' are
Since impurities are diffused into the + layer 4' from the surface, the internal drift electric field is in the opposite direction, and the carrier diffusion rate is slowed down.

The third drawback is that the holes injected into the P+ layer 4' are only injected from the sidewall portion of the P+ layer 4, and the injection from the bottom portion is not effectively used.

For this reason, there is a drawback that the characteristics of I2L cannot be fully utilized by simply combining it with a conventional IC as shown in FIG.

An object of the present invention is to solve the first and third drawbacks regarding the structure of the semiconductor device shown in FIG. An object of the present invention is to provide a semiconductor integrated circuit device.

In order to achieve the above object, the present invention considers the energy band and localizes a semiconductor region of a conductivity type opposite to that of the substrate in all or a part of the semiconductor layer where I2L is formed. This solves the third drawback and makes it possible to increase the current amplification factor.

The present invention will be explained in detail below with reference to Examples.

FIG. 2 is a diagram showing one step of forming a semiconductor device according to the present invention.

As shown in FIG. 2a, first, an insulator mask having desired characteristics such as a thin silicon dioxide layer, silicon dioxide layer, or aluminum oxide layer is deposited on the P-type semiconductor substrate 1 by an appropriate method. N+ type low resistance buried layers 2, 2' are formed at desired locations on the semiconductor surface by impurity diffusion, etc., and an N type epitaxial layer 3 is further formed by epitaxial growth.

An insulator 8 such as a silicon dioxide layer is placed on the structure at a desired location.
is deposited as a mask, P-type impurity is diffused, and P-type impurity is diffused.
Form a + type separation layer region 9 or use the mask to etch about half of the N type epitaxial layer 3 to make a hole;
FIG. 2b shows a structure in which isolation layer regions 9 are formed by oxidizing and forming an insulator by a suitable method.

Next, as shown in FIG. 2C, P layers 4.4', 4'', 4'' are formed by diffusion or the like again using an insulating mask 8 made of silicon dioxide or the like.

As shown in Figure 2d, the silicon dioxide layer is opened using a conductive mask 1.1 such as chromium, the chromium layer is brought to a low potential, and N-type impurity elements such as phosphorus are ion-implanted. (In the case of phosphorus, the acceleration energy is 500 KeV and 0.
It is possible to implant to a depth of 1.3μ at 73μ and 1000KeV.

) An N-type implant layer 10 is formed adjacent to a portion of the P layer, such as 4.4', 4'', and then annealed at 600-900°C.

Next, as shown in FIG. 2e, N layers 5.5', 5'', 5'' are formed by diffusion or the like again using an insulating mask 8 made of silicon dioxide or the like.

As shown in FIG. 2f, the electrodes 6, 7.7', 7'' (N+ type low-resistance buried layers 2, 2', since the diagram is complicated) are made using the insulator mask 8 with holes drilled at desired locations. Also, connection electrodes of the P+ type separation layer region 9 are not shown.

), it is possible to form an I2L that is compatible with ICs of conventional structure and has improved characteristics.

FIG. 3 is a diagram showing another process for forming a semiconductor device according to the present invention.

After completing step C in FIG. 2, as shown in FIG. 3a, using an insulator mask 8 such as silicon dioxide,
, 5''' are formed by diffusion or the like.

As shown in FIG. 3b, the silicon dioxide layer is opened using a conductive mask 11 such as chromium, the chromium layer is brought to a low potential, and N-type impurity elements such as phosphorus are ion-implanted. An N-type implant layer 10 is formed adjacent to a portion of the P layer, followed by annealing at 600-900'C.

As shown in FIG. 3C, an IC having the same structure as described above can be formed by providing electrodes 6, 7.7', 7'' using an insulator mask 8 with holes drilled at desired locations.

The feature of this structure is that a low-resistance N-type implantation layer 10 is embedded in a floating form in a high-resistance N-type layer 3, and a P-type layer 4
．． It is at the point where it touches 4', 4''.

The reason for having such a structure will be explained below.

The energy band diagram of the region surrounded by the dot-dash dot circles in FIG. 2f and FIG. 3C is shown in FIG. 4a.

In the same figure, a lateral PNP transistor (emitter is 4, base is 3, and collector is 4') is shown as a solid line.

) and the vertical PN diodes (4 for the anode and 10 for the cathode) are shown in dot-dash dots.

) and the Fermi level indicated by the dotted line.

The current Ic flowing through the electrode 6 of the conventional structure (Fig. 1) is expressed by the formula (1
) can be expressed as

■c=IPL+■nL+■PV+■nV (1) Here,
IPL and InL are respectively the hole current (3 in Figure 4a) injected into the base side of a lateral PNP transistor and the electron current injected into the emitter side (1 in Figure 4a), and I
PV and InV are respectively vertical diodes (in FIG. 1, the anode is 4 and the cathode is 3).

) injected hole current to the cathode side (3 in Figure 4a)
) and the injected electron current to the anode side (1 in Fig. 4a).

Since the impurity concentration of the P layer 4 is higher than that of the n layer 3, equation (1) can be approximated as shown in equation (2).

Ic=IpL+Ipy (2) Current I flowing through the electrode 6 of this structure (Fig. 2 f and Fig. 3 f)
N can be expressed by equation (3).

IN=IPL+InL+■PV+InV (3) Here,
IPL and InL are as described above, and I'PV and InL are
V is each a vertical diode (in FIGS. 2f and 3f, the anode is 4 and the cathode is 10).

) injected hole current to the cathode side (2 in Figure 4a)
) and the injected electron current to the anode side (1 in Fig. 4a).

Since the impurity concentration of the n-layer 3 is lower than the concentration of the n-layer 10,
IPV>IPV' holds true.

Therefore, equation (3) can be approximated as equation (4).

IN=PL (4) PNP transistor injection efficiency γC (conventional structure) and γN
(This structure) can be simplified as shown in equation (5).

From the above explanation, the effective injection efficiency of this structure is improved compared to the conventional structure.

γN>γc; Due to the presence of the N layer 10, the current injected from the P layer 4 flows through the lateral PNP transistor, and most of the current becomes a hole current, improving the effective injection efficiency compared to the conventional structure.

) Further, the advantage of having the N layer 10 adjacent to the P layers 4, 4', 4'' also contributes to improving the reverse current amplification factor of the vertical NPN transistor described below.

The energy band diagram of the area enclosed by the circles in FIG. 2f and FIG. 3C is shown in FIG. 4b.

The dotted area in the figure is the energy band in the same region of the conventional structure.

N The current flowing through the N layer 2' of the conventional structure can be expressed by equation (6).

Here, ■■ and ■■ are vertical NPN transistors (emitter is 3, base is 4',
The collector is 5.

) are the hole current injected to the emitter side (3 in FIG. 4b) and the electron current injected to the base side (1 in FIG. 4b).

The current flowing through the N layer 2' of this structure can be expressed by equation (7).

The hole current injected to the emitter side (2 in FIG. 4b) of the NPN transistor is the electron current injected to the base side (1 in FIG. 4b).

As mentioned above, the impurity concentration of the N layer 2' is P layer 4.4',
The concentration of P layer 4.4', 4'' is higher than that of N
Higher than layer 3.

For this reason, equation (8) holds true.

Reverse injection efficiency γ■ (conventional structure) and γ of NPN transistor
(2) (This structure) can be expressed by equation (9).

From equations (8) and (9), this structure has improved back injection efficiency compared to the conventional structure.

(γ■>γ■; The hole current injected to the emitter side is N layer 10
Due to the existence of , most of the current flowing through the longitudinal NPN transistor becomes an injection electron current, and the reverse current amplification factor is improved compared to the conventional structure.

) Note that since the N+ layer 10 embedded in the N layer 3 is bonded by majority carriers, the N layer 10 does not need to be adjacent to the N+ buried layer 2, and the thickness of the N layer is arbitrary, and it is simply a P layer. 4.4', 4'', it does not affect the characteristics at all even if it is not directly connected to the external electrode.

Therefore, the current amplification factor of the reverse operation characteristic of the conventional transistor used in the 2L circuit is significantly improved (for example, about β2 is improved by more than one order of magnitude to about β20), and the operation of the circuit becomes stable.

Therefore, since the current amplification factors of the conventional 2L horizontal PNP transistor and vertical inverted NPNh transistor have both been improved, the reactive power consumed between the base and emitter of each transistor has been significantly improved, and the power usage efficiency has improved compared to the conventional I2L. It is improved compared to the previous model and can achieve lower power consumption of 2L.

Figure 5 shows an example of circuit connection of a device using a conventional structure IC and ■2L, Q1 to Q6 are transistors, R
1 to R3 are resistances.

A is an input circuit (conventional structure IC) section, B is a 2L section, and C is an output circuit (conventional structure IC) section that converts the output of 2L to an external signal level.

Such a configuration is possible in chip form and is completely compatible with all conventional ICs and LSIs.

In addition, in the above process, when an N-type substrate is used instead of a P-type substrate, all of the above-mentioned P and N are replaced.

As described above, the structure of the present invention has the following advantages over conventional structure methods.

(1) The power usage efficiency of I2L is significantly improved and the operation is stable.

(2) A configuration compatible with bipolar ICs of conventional structure can be achieved.

(3) Therefore, arbitrary interconnection between the conventional IC and the 2L becomes possible.

(4) ■Multifunctional large bipolar LSI chip
The configuration is easy.

(5) Furthermore, the ion implantation process required to form the present semiconductor device is relatively simple, and the increase in the number of processes is small;
Yield loss is hardly a problem.

Therefore, according to the present invention, it is possible to manufacture a bibolar LSI, which has not been possible in the past, and the industrial benefits are extremely large.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing a conventional 12L, FIG. 2 is a diagram illustrating the structure and manufacturing method of one embodiment of a semiconductor device according to the present invention, and FIG. 3 is a diagram similar to the above of another embodiment. Figure 4a,
b is an energy band diagram for explaining one embodiment of the present invention, and FIG. 5 is an equivalent circuit diagram of a semiconductor device using a conventional structure IC and I2L. 1, 2, and 3, 1 is a P-type semiconductor substrate, 2 and 2' are N+ type low-resistance buried layers, 3 is an N-type epitaxial layer, and 4, 4', 4", and 4"' are P-type semiconductor substrates. (P+) layer,
5.5', 5", 5"' are N (N+) layers, 6 and 7.7'
, 7'', 7''' are electrodes, 8 is an insulator, 9 is a (P+ type) isolation layer region, and 10 is an N type implantation layer. Figure 4a is an energy band diagram of the injection region, where 1 is the injected electron current, 2 and 3 are the injected hole currents, and Figure 4b is the energy band diagram of a vertical NPN transistor, where 1 is the injected electron current, 2 and 3 are injected hole currents. In FIG. 5, A is an input circuit, B is an I2L, and C is an output circuit.

Claims (1)

[Claims] 1. In a semiconductor integrated circuit device in which a bipolar integrated circuit and an integrated injection logic circuit coexist on one semiconductor chip, a plurality of conductivity types opposite to that of the substrate are provided at desired locations on the surface of the semiconductor substrate. A plurality of first semiconductor layers are provided, a second semiconductor layer of a conductivity type opposite to that of the substrate is provided on the surface of the semiconductor substrate including the first semiconductor layer, and a plurality of third semiconductor layers of the same conductivity type as the substrate are formed.
The second semiconductor layer is separated into a plurality of regions by a semiconductor layer or an insulator, and a plurality of fourth semiconductor layers having the same conductivity type as the substrate are provided at desired locations below the surface portion of the separated second semiconductor layer region. By providing a fifth semiconductor layer of a conductivity type opposite to that of the substrate at a desired location of the fourth semiconductor layer and the second semiconductor layer, the fourth semiconductor layer is provided in at least one separated second semiconductor layer region.
a semiconductor layer as a base, a fifth semiconductor layer provided within the fourth semiconductor layer;
A bipolar integrated circuit having a semiconductor layer as an emitter is constructed, and in at least one of the other separated second semiconductor layer regions, two fourth semiconductor layers are used as an emitter and a collector of a lateral transistor, and a fourth semiconductor layer is provided as an emitter and a collector of a lateral transistor. An integrated injection logic circuit is constructed in which a fourth semiconductor layer and a fifth semiconductor layer provided in the fourth semiconductor layer are used as the base and collector of a vertical reverse operation transistor, and A sixth semiconductor layer having a conductivity type opposite to that of the substrate and having low resistance is present under the fourth semiconductor layer, and the impurity concentration peak position of the first semiconductor layer is in the interface region between the substrate and the second semiconductor layer, and A semiconductor integrated circuit device characterized in that a peak position of impurity concentration in the sixth semiconductor layer is above a peak position of impurity concentration in the first semiconductor layer. 2. The semiconductor integrated circuit device according to claim 1, wherein the low-resistance sixth semiconductor layer is located apart from the first semiconductor layer. 3 A process of forming a plurality of first semiconductor layers by diffusing impurities of a conductivity type opposite to that of the substrate on the surface of the semiconductor substrate, and forming a second semiconductor layer of a conductivity type opposite to that of the substrate on the surface of the semiconductor substrate. a step of forming the second semiconductor layer by taxial growth; a step of separating the second semiconductor layer into a plurality of regions using a third semiconductor layer or an insulator having the same conductivity type as the substrate; A step of forming a fourth semiconductor layer of the same conductivity type as the substrate below the surface portion, and a step of forming a fifth semiconductor layer of the opposite conductivity type to the substrate at desired locations of the fourth semiconductor layer and the second semiconductor layer. and a bipolar integrated circuit having a fourth semiconductor layer as a base and a fifth semiconductor layer provided in the fourth semiconductor layer as an emitter is formed in the at least one separated second semiconductor layer region. , two fourth semiconductor layers are used as an emitter and a collector of a lateral transistor in at least one other separated second semiconductor layer region, and a fourth semiconductor layer serving as the collector and a fourth semiconductor layer provided in the fourth semiconductor layer are provided. A method for manufacturing a semiconductor integrated circuit device in which an integrated implanted logic circuit is formed using a fifth semiconductor layer as a base and a collector of a vertical inverse dynamic body transistor, wherein a desired second semiconductor layer region in which the integrated implanted logic circuit is formed is provided. forming a low-resistance sixth semiconductor layer of a conductivity type opposite to that of the substrate by performing ion implantation, and forming at least a portion of the sixth semiconductor layer under the fourth semiconductor layer; A method for manufacturing a semiconductor integrated circuit device, comprising: