JPS61150231A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent a parasitic PNP transistor from being formed, to improve characteristics of a transistor, and to manufacture the IC operating stably, by forming an N<+>-type diffusion layer extended from an N<+>-type buried layer between an N<->-type semiconductor region and an isolation P-type layer. CONSTITUTION:An N<+>-type buried layer 2 is extended to below an isolation groove 4, and an N<+>-type diffusion layer 9 with a high concentration is formed between the periphery of an N<->-type mesa semiconductor region 3a and an N<+>-type buried layer extension. A portion of the N<+>-type diffusion layer 9 serves as a collector taking-out section 8 where a collector electrode C is provided in a groove. In an IC structure having an NPN transistor so constructed, its base would be coupled to the isolation P-type diffusion layer in the peripheral groove when being saturated to result in a parasitic PNP sub-transistor. However, by forming the N<+>-type diffusion layer 9 with a high concentration on the periphery acting as the base of the PNP sub-transistor, amplification factor alphaof the PNP sub-transistor is reduced and thus its operation is prevented. In this way, transistor characteristics can be improved and the transistor can be operated at a low consuming power.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a technique for preventing parasitic transistors in semiconductor devices, particularly in ICs (semiconductor integrated circuit devices) having saturated transistors.

[Background technology]

In bipolar ICs, it is known to use an isolation structure in which a groove or an insulating layer is provided in a part of a semiconductor substrate for electrical isolation between elements, and this is further combined with a pn junction. (Electronic materials July 1982 P11
1-115 New Element Isolation Technique) FIG. 13 shows an example of an isolation structure using a groove portion, which is adopted by the applicant of the present application in a miniaturized IC.

1 is a p-type silicon semiconductor substrate (substrate), on which an n-type buried layer 2 is partially interposed, an epitaxial n-type silicon layer 3 is formed, and the surface of this n-type silicon layer 30 is A groove (isolation groove) 4 is dug in a part and a p-type layer 5 is formed directly under the groove 4 so as to be connected to the p-type substrate.

The n-type semiconductor island region 3a surrounded by the groove 4 and the p-type layer 5 is used as a collector, and the surface of the n-type semiconductor island region 3a when the base is saturated is
and the emitter n-type layer 7 is diffused to form a vertical npn) transistor. Note that the collector extraction portion 8 is formed using a part of the groove portion 4 to form a shallow n+ type scattered layer. (It is also possible to reduce the collector series resistance.) In such an npn) run risk structure, the base part (6
) is saturated, the potential between the base and the collector becomes a forward potential, which combines with the p-type layer 5 directly below the isolation groove to generate a parasitic sub-pnp) transistor as shown in FIG. The potential of NPN transistors increases, causing malfunctions of NPN transistors such as SiRisk.

In such a parasitic sub-pnp run risk structure, the impurity concentration of the epitaxial n-type layer serving as the base is low, and the distance between the base and the isolation is narrow (as a result, pnp operation is likely to occur). This is particularly noticeable in miniaturized ICs in which the thickness of the epitaxial n-type layer is thin.

This is also the case with lateral pnp transistors separated by trench isolation: 1.C, in which case the pnp transistor
This resulted in the generation of a parasitic sub-pnp (pnp) transistor consisting of an n-type emitter fist, an n-type base and a p-type substrate, and a collector base-substrate when the p-type collector is saturated.

[Purpose of the invention]

The present invention has been made to overcome the above-mentioned problems, and its purpose is to eliminate the generation of parasitic sub-pnp transistors and improve the characteristics of transistors in micro ICs used in saturation type. , to stabilize IC operation.

[Summary of the invention]

A summary of typical inventions disclosed by the present inventor is as follows.

That is, an epitaxial n-type layer is formed by partially interposing an n++ buried layer on a p-type conductor substrate, and an n-
An isolation trench is dug in a part of the surface of the mold layer, and an isolation p-type layer is provided between this isolation trench and the p-type substrate directly below it. An IC in which an npn (npn) transistor with this n-type layer as a collector is formed on the surface of an n-type semiconductor region, and the n-type buried conductor region is provided between the n-type groove conductor region and the isolation p-type layer. n with extended layers
By forming the + type scattering layer, the generation of sub-pnp parasitic transistors at the time of base saturation is prevented, thereby achieving the object of the invention.

[Embodiment 1] FIGS. 1 and 2 show an embodiment of the present invention, in which FIG. 1 is a plan view of a main part of an IC having an npn) transistor, and FIG. It is an AA' cut sectional view. 1 is a p-type silicon substrate (substrate),
2 is an n++ buried layer, 3 is an n-type silicon layer formed by epitaxial growth on the substrate, 4 is an isolation groove, and 5 is an isolation 1-type p+ type diffusion provided between the groove and the substrate directly below it. It is a layer. A p-type diffusion layer 6 and an n+ type scattering layer 7 are formed on the surface of the mesa-shaped semiconductor region 3a surrounded by these isolation regions 1, forming the base and emitter of the npn transistor.

Particularly noteworthy in this invention is that the n++ buried layer 2 extends to the bottom of the isolation trench 4, and the n++ buried layer 2 extends to the periphery of the mesa-shaped n-type semiconductor region 3a (including the part in contact with the trench). A high-concentration n+ type scattering layer 9 is provided between the layer extension portion and the layer extension portion. As shown in FIG. 1, a part of this n-type diffusion layer 9 becomes a collector lead-out part (8) located in the groove, and a collector electrode C is provided therein. 10 is a surface oxide film (Sin, film).

FIG. 3 shows that by making the isolation groove 4 deeper than the thickness of the epitaxial n-type layer, the n++ buried layer 2 is
This is an example in which the n+ type scattering layer 9) in the peripheral portion does not necessarily have to be formed.

〔effect〕

In an IC structure having such an npn) run lister, when the base part is saturated, it connects with the isolation p-type diffusion layer in the peripheral trench, resulting in a parasitic sub-pnp) run lister. By providing the highly concentrated n++ diffusion layer 9 in the I)nl)) runlister amplification factor α is reduced, it is possible to prevent the parasitic pnp) runlister operation.

In this way, if the parasitic pnp) run lister operation is eliminated,
npn) Run Lister has high saturation characteristics,
Lower power consumption is realized along with improved characteristics.

[Embodiment 2] FIG. 4 shows another embodiment of the present invention, in which an isolation groove 4 and an isolation p-type diffusion layer 5 are shown.
1 is a cross-sectional view of an IC in which a lateral pnp (pnp) run lister is formed in an n-type island region electrically isolated from the periphery by a lateral pnp).

In this case, the island region n-type layer 3b becomes the base of a lateral pnp transistor. 11 is a p+ type layer which becomes a collector;
12 is a p+ type layer which becomes an emitter. Reference numeral 13 denotes an n+ type layer serving as a base extraction portion, located within the groove 4 and connected to the n++ buried layer 2. Insulating film (S r Ot film) 1 on the surface
Covered with 0.

Particularly noteworthy in this invention is that the n++ buried layer 2 extends to the bottom of the isolation trench 4, and is located between the peripheral part of the mesa-shaped n-type semiconductor island region 3b and the n++ buried layer 2. A high concentration n+ type scattering layer 9 is provided.

〔effect〕

In an IC structure having such a lateral pnp) run lister, the parasitic sub-parasitic sub-pnp) that occurs when the collector of the lateral pnp) run lister is saturated (by increasing the impurity concentration around the n-type region, which is the base of the lateral pnp) run lister, the current The amplification factor α is reduced, which reduces parasitic currents.

By eliminating the parasitic sub-pnp (pnp) run lister operation in this manner, the horizontal pnp (pnp) run lister has a high saturation characteristic, which improves the characteristics and reduces power consumption.

〔Example〕

5 to 12 show other embodiments of the present invention, in which steps are taken in the manufacturing process of an IC equipped with on-substrate linear elements (NPN transistors) and IIL (injected stacking logic). FIG.

Hereinafter, each step will be specifically explained.

(1) Prepare a p-type silicon crystal substrate 1 (wafer),
The fifth layer is formed by oxidation, photoetching, and sb (antimony) diffusion.
An n-type buried layer 2 shown in the figure is formed, and an n-type silicon layer 3 is formed.
After epitaxially growing (thickness: 1.5 μm), a thermal oxide film 14. CVD/Oxide film (Sin,) 15
form.

(The n-type silicon layer 3 is etched through a photoetched mask of 21CVD11Si01, and an isolation groove 4 with a depth of 0.8 μm is dug as shown in FIG. 6.

Of the n-type layer 3 separated by the isolation groove 4, the region 3a is a linear element formation region, and the region 3b is an II
Let it be L area.

(The near side of 311J is covered with an oxide film mask 16, and the surface of the n-type layer 3b on the IcIIL side is further covered with 0.000.
Etch by 3 μm (4) Form an oxide film mask 17 through oxidation and photoetching, and ion implant P (phosphorus) (5X1012cIIr).
”) As shown in FIG. 8, on the linear side, an n+ type scattering layer 19 is formed in the peripheral area including the collector extraction portion 18, and on the IIL side, the entire area 20 where the injector is formed and the emitter are formed. An in-type diffusion layer 21 is formed around the periphery where the extraction portion is formed.

(5) Next, B (boron) ions are implanted (1,
As shown in FIG. 9, an isolation p-type layer 23 is formed directly under the groove so as to surround each region.

(6) B ion implantation after oxidation and photoetching (2,7X1
As shown in FIG. 10, a base p-type layer 24 is formed on the linear side, an injector p-type layer 25 and an inverter base p+-type layer 26 are formed on the IIL side.

(7) Emitter, photoetch, oxidize + As ion implantation (5X I0IIlcIX+-), 11th
As shown in the figure, on the linear side, an emitter n-type layer 27. A multi-collector n+ type layer 28 is formed on each linear side.

(8) Finally, after oxidation, contact photoetching, aluminum vapor deposition, patterning etching, and contact alloying are performed to form aluminum electrodes 29 in contact with each region as shown in FIG.

〔effect〕

n on the periphery of the semiconductor island region where the transistor is formed.
By using the IIL IN diffusion process in forming the type diffusion layer, it is possible to prevent the occurrence of run listers (parasitic sub-pnp) without increasing the number of new processes.

Although the invention made by the present inventor has been specifically explained above using examples, the present invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof.

For example, the n+ type scattered layer may be formed in the peripheral portion of the semiconductor island region by upwelling diffusion JK from the n++ buried layer 2.

The present invention can also be applied to the case where an n+ type scattered layer is formed along an isoplanar oxide film in which an oxide film is formed by selective oxidation along the isolation groove.

[Application field]

The present invention can be applied to ICs in general and miniaturized ICs using a groove isolation method.

The present invention is particularly applicable to saturation type IC, TTL, “II
This is effective when applied to IC9LSI including L.

[Brief explanation of the drawing]

1 and 2 show an embodiment of the present invention, FIG. 1 is a plan view of a main part of an IC having an npn) run lister, and FIG. 2 is a cross-sectional view taken along the line AA' in FIG. 1. . FIG. 3 is a sectional view of an IC showing another embodiment of the present invention. FIG. 4 shows another embodiment of the present invention, in which the horizontal p n
FIG. 1 is a cross-sectional view of a main part of an IC having a p-transistor. FIGS. 5 to 1 and 2 show other embodiments of the present invention, and are cross-sectional views of the manufacturing process of a S=AφIIL coexistence IC. FIG. 13 is a sectional view showing an example of an IC having an eyelash groove, and FIG. 14 is a circuit diagram equivalent to FIG. 13. 1...p-type silicon substrate (substrate), 2.
... n++ buried layer, 3... epitaxial n- type silicon layer, 4... isolation groove, 5... Eisley's p-type diffusion layer, 6... p-type diffusion layer (base) , 7...n+ type scattering layer emitter), 8...n
+ type scattered layer collector extraction part), 9...n+ type scattered layer 10...surface oxide film, 1:1...p+ type layer (collector), 12...p+ type layer ( emitter), 13...
・N+ type scattering layer base extraction part), 14... Thermal oxide film, 15... CVD/oxide film, 16... Oxide film mask, 17... Oxide film mask, 23... Iso 24... base p-type layer, 25... injector p+ type layer, 26... base p-type layer, 27...
・Emitter n+ type layer, 28...Multi collection n+
Type layer, 29IC - IFR -

Claims (1)

[Claims] 1. A low concentration semiconductor layer of a second conductivity type is formed by epitaxial growth on a semiconductor substrate of a first conductivity type with a high concentration buried layer of a second conductivity type partially interposed therein, The type semiconductor layer has an isolating first layer provided between a portion of its surface and the substrate.
A semiconductor device in which a semiconductor region electrically isolated from other regions is formed by a conductivity type layer, and a vertical transistor with a second conductivity type layer as a collector is formed on the surface of this semiconductor region, and the base of the transistor is A semiconductor characterized in that a second conductivity type high concentration diffusion layer in which the high concentration buried layer is extended is interposed between the first conductivity type region and the isolation first conductivity type layer. Device. 2. A patent in which a groove is dug in a part of the surface of the second conductivity type semiconductor layer, and a first conductivity type layer for electrical isolation is formed between the groove part and the first conductivity type substrate. A semiconductor device according to claim 1. 3. An epitaxially grown second conductivity type low concentration semiconductor layer is formed on the first conductivity type semiconductor substrate with a second conductivity type high concentration buried layer partially interposed, and the second conductivity type semiconductor layer is formed on the surface thereof. A semiconductor region electrically isolated from other regions is created by the first conductivity type layer provided between a part of the semiconductor region and the substrate, and a lateral transistor based on the second conductivity type layer is formed on the surface of this semiconductor region. A second conductivity type high concentration semiconductor device formed in which the high concentration buried layer is extended between the first conductivity type layer serving as the collector of the transistor and the isolation first conductivity type layer. A semiconductor device characterized by having a layer interposed therebetween. 4. A patent claim in which a groove is dug in a part of the surface of the second conductivity type layer, and a first conductivity type layer for electrical isolation is formed between the groove part and the first conductivity type substrate. The semiconductor device according to scope 3.