JPH0294527A - Semiconductor device - Google Patents

Abstract

PURPOSE:To ensure breakdown strength between an emitter and a collector while obtaining a lateral type transistor having high hFE, ICmax and fT by a high-concentration second region and a buried region by forming the high- concentration second region in a collector region and connecting the second region to the buried region shaped toward an emitter region. CONSTITUTION:A P<+> type impurity is diffused selectively at a place corresponding to a P<+> buried region 3 in an N-type epitaxial layer 4, and a P<+> type insulating isolation region 5 is formed. The P<+> type impurity is also diffused selectively into a region corresponding to a P<+> buried region 3' at the same time, and a P<+> type collector second region 5' is shaped. When these regions are formed, the P<+> type buried regions 3, 3' shaped to an silicon substrate 1 are pushed up toward the epitaxial layer 4, and connected to the P<+> type insulating isolation region 5 and the P<+> type collector second region 5' respectively. Accordingly, the high-concentration second region 5' connected to a collector region 6c is extended in the lateral direction up to a section approximately near to an emitter region 6e, thus improving hFE, ICmax and fT.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device including a lateral transistor with improved electrical characteristics.

[Conventional technology]

Conventionally, the lateral transistor has a PN structure as shown in the cross-sectional view of Fig. 3.
As exemplified by a P transistor, a P-type semiconductor substrate 1
An N-type buried layer 2 and a P-type buried region 3 are formed, and an N-type epitaxial layer 4 as a base region is grown thereon. Then, a P'' isolation diffusion region 5 connected to the P'' type buried region is formed to isolate the island region in which the transistor is to be formed. A P-type emitter region 6e is provided within the island region.

A P type collector region 6c and an N+ type base contact region 7 are formed to be arranged laterally. Further, emitter, collector, and base electrodes 9, 10, and 11 are formed through the opening region of the oxide film 8 on the surface.

[Problems to be Solved by the Invention] - In the conventional lateral transistor described above, in order to increase the withstand voltage between the base and collector, it is necessary to increase the distance between the emitter region 6e and the collector region 6c. However, in a lateral transistor, current in the lateral direction is dominant, so the larger the distance between the emitter region 6e and the collector region 6c, the longer it takes for holes injected from the emitter region 6e to reach the collector region 6C. The probability of recombination with electrons within the base region 4 increases, and the current amplification factor (hrt) decreases.

In addition, normally this collector region 6c and emitter region 6e
Since these are formed at the same time as the base contact region of the NPN transistor, the collector region 6c and emitter region 6e cannot be formed with a high concentration due to the element characteristics of the NPN transistor.

As a result, it becomes difficult to improve the hrt of the transistor, which causes an increase in the collector saturation resistance (rtc), which causes a decrease in the maximum collector current (IC, , ) and a decrease in the gain bandwidth product (f, ). .

The present invention is based on hrE, IC□8. It is an object of the present invention to provide a semiconductor device including a lateral transistor with improved f7.

[Means to solve the problem]

In the semiconductor device of the present invention, a buried layer of a second conductive type and an epitaxial layer as a base region are formed in a semiconductor substrate of a first conductive type, and an emitter region of a first conductive type is formed in the epitaxial layer on the buried layer. .

In a semiconductor device in which a lateral transistor is formed by forming a collector region and a base contact 8N region of a second conductivity type, at least the collector region of the emitter region and the collector region has a height of the second conductivity type in the depth direction. Concentration 2nd
A second region of the collector is connected to a buried region of a second conductivity type selectively provided on the buried layer toward the emitter region.

[Effect]

In the above-mentioned configuration, a high concentration of second N is provided especially in the collector region.
By forming a region and connecting it to a buried region provided toward the emitter region, the withstand voltage between the emitter and collector is ensured, while hFE+IC□8. and improve fr.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows a first embodiment of the present invention, in particular a horizontal type P
NP) is a structural cross-sectional view showing a transistor.

In the figure, an N-type impurity such as arsenic or antimony is diffused from the surface of a P-type silicon substrate 1 to form an N-buried layer 2, and a P-type impurity such as boron is injected into a region surrounding this N-buried layer 2. Impurities are diffused to form a P-containing region 3. At the same time, P impurity is diffused into the region where a collector will be formed in the future to form a P impurity region 3'. Then, an N-type silicon epitaxial layer 4 is grown on the surface by vapor phase growth.

This N-type epitaxial layer 4 includes the P1 buried region 3.
Selectively diffuse P゛゛ impurity to the position corresponding to P°
A mold insulation isolation region 5 is formed. At this time, P° type impurities are also selectively diffused into the region corresponding to the P-type region 3' to form a P-type collector second region 5'.

In addition, when forming these regions, the P'' type buried region 33' formed in the silicon substrate 1 rises toward the epitaxial layer 4, and the P'' type insulating isolation region 5. P°
They are respectively connected to the mold collector second regions 5'. As a result, in the collector region, the P3 type buried region 3' is also configured as a part of the collector.

Then, P-type impurities are diffused from the surface of the epitaxial layer 4 to form an emitter region 6e and a collector region 6c. Further, N° type impurities are similarly diffused to form an N9 type base contact region 7.

Further, the oxide film 8 formed on the surface is etched to form openings, and electrodes 9, 10, and 11 of the emitter, collector, and base made of aluminum are formed.

Therefore, in this configuration, while maintaining the lateral distance between the collector region 6C and the emitter region 6e at a predetermined dimension to obtain the withstand voltage between the base and collector, the collector region 6C
Since the highly doped second region 5' connected to the emitter region 6e is extended in the lateral direction almost to the vicinity of the emitter region 6e, hFt can be improved, and at the same time, IC, . . . , fT can be improved.

Furthermore, in this configuration, the P'' type buried region 3' and the collector second region 5' can be formed at the same time as the conventional P'' type buried region 3 and P+ type insulation isolation region 5, respectively. , the number of steps does not increase and the structure can be easily configured.

FIG. 2 is a structural sectional view of the second embodiment of the present invention, and FIG.
As in the embodiment, an example in which the present invention is applied to a horizontal PNP transistor is shown. Note that the same parts as in FIG. 1 are given the same reference numerals.

In this embodiment, the area of the P'' type buried region 3' provided below the collector region 6c is reduced. Further, a P-type buried region 5 is also formed in the emitter region 6e, which constitutes a second emitter region.

Also in this configuration, the same effects as in the first embodiment can be obtained. However, in this embodiment, the P" type buried region 3'
By making the area smaller, the breakdown voltage can be improved, and by providing the second emitter region 5#, IC, . . . , f can be further improved.

〔Effect of the invention〕

As explained above, in the present invention, the highly concentrated second M region is formed in the collector region, and this is connected to the buried region provided toward the emitter region, thereby ensuring the emitter-collector breakdown voltage. In addition, h FE is formed by the high concentration second region and the buried region.

IC□1. There is an effect that a lateral transistor with high f and f can be constructed. Further, there is an effect that the pattern size can be manufactured at the same level as the conventional method without adding a new manufacturing process to the conventional manufacturing method.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a first embodiment in which the present invention is applied to a lateral PNP transistor, FIG. 2 is a sectional view of a second embodiment of the invention, and FIG. 3 is a sectional view of a conventional lateral PNP transistor. . 1... P-type silicon substrate, 2... N-containing layer, 3.
3'...P'' type buried region 4...N type epitaxial layer, 5...P'' insulation isolation region, 5'...P'' collector second region, 5''...P'' second emitter region, 6c...collector region, 6e...emitter region,
7... Base contact region, 8... Oxide film, 9.
10.11... Electrode.

Claims (1)

[Claims] 1. A buried layer of a second conductivity type and an epitaxial layer as a base region are formed in a semiconductor substrate of a first conductivity type, and on the buried layer, an emitter region, a collector region and a collector region of a first conductivity type are formed in the epitaxial layer. In a semiconductor device comprising a lateral transistor formed by forming a base contact region of two conductivity types, at least the collector region of the emitter region and the collector region includes a highly doped second region of the second conductivity type in the depth direction. and a second region of the collector is connected to a second conductivity type buried region selectively provided on the buried layer toward the emitter region.