JP2703955B2 - Vertical bipolar transistor - Google Patents

Description

The present invention relates to a vertical bipolar transistor, and more particularly, to a vertical bipolar transistor.
The present invention relates to a vertical bipolar transistor in which a substrate current (hereinafter, referred to as _ISUB ) in a saturation region is reduced.

[Prior art] A triple-diffusion PNP transistor (hereinafter referred to as T-PNPTr) as a vertical bipolar transistor has a large emitter ground current amplification factor (h _FE ), a large increase in h _FE collector current, and a cut-off frequency. It is widely used because it has such features as high and has good complementarity with NPN transistors. The conventional T-PNPTr has the structure shown in FIG. 2, which is formed as follows.

An N ⁻ -type epitaxial layer 4 is formed on a P-type semiconductor substrate 1 having an N ⁺ -type buried layer 2 and P ⁺ -type buried layers 3 and 3a. To form a P-type first collector region 6 which becomes a part of the collector region. Next, P ⁺ which becomes part of the collector region
The mold second collector region 7 and the P ⁺ insulating isolation region 7a are formed simultaneously. At this time, the P-type first collector region 6 and the P ⁺ -type second
The collector region 7 and the P ⁺ -type insulating isolation region 7a are connected to the P ⁺ -type buried layers 3 to 3a, respectively. Next, an N-type base region 8 is formed in the P-type first collector region 6, and then an N ⁺ base contact region 9 is formed. Subsequently, the P ⁺ -type emitter region 10 and the P ⁺ -type collector contact region 10a are simultaneously formed. Finally, an emitter electrode 12, a base electrode 13, and a collector electrode 14, which are in contact with each region through the opening of the silicon oxide film 11, are formed.

[Problems to be Solved by the Invention] In recent years, in a stabilized power supply integrated circuit, T · PNPTr is often used as a driver for an output transistor. In this case, the substrate current I _SUB is _reduced . The increase in current consumption due to the increase is a major problem. This I _SUB increases rapidly when T · PNPTr enters the saturation region, which is considered to be due to the following reason. Second
As shown in FIG. 3, a parasitic NPNTr having an N ⁻ type epitaxial layer 4 as a collector, a P ⁺ type buried layer 3 as a base, and an N type base region 8 as an emitter, as shown in FIG. P
A parasitic PNP Tr having a ⁺ -type insulating isolation region 7a, a P ⁻ -type semiconductor substrate 1 as a collector, an N ⁻ -type epitaxial layer 4 as a base, and a P ⁺ -type buried layer 3 as an emitter. This equivalent circuit is shown in FIG.

Therefore, when T • NPPTr saturates, the base of the parasitic NPNTr −
Since the emitter junction is forward biased, this parasitic transistor conducts, supplies a base current to the parasitic PNPTr, and makes the parasitic PNPTr conductive. As a result, the substrate current I _SUB
Increase rapidly. The situation is shown in FIG. This is because the collector-emitter voltage is 3 V, the base-emitter voltage _VBE versus the collector current I _C , the base current IB and the substrate current I _{B
The SUB} characteristic is shown. As is clear from FIG.
When NPTr enters the saturation region, i.e. V _BE is, V _BE> 1V become the substrate current I _SUB is rapidly increased.

Therefore, an object of the present invention is to prevent the substrate current I _SUB from being rapidly increased even when a vertical bipolar transistor such as a T-PNP Tr is operated in a saturation region. The purpose is to suppress an increase in heat generation.

[Means for Solving the Problems] A vertical bipolar transistor according to the present invention includes a first conductivity type semiconductor substrate, a second conductivity type buried layer formed on a surface of the first conductivity type semiconductor substrate, A first conductivity type buried layer formed in a region of the buried layer on the surface of the second conductivity type buried layer, a second conductivity type epitaxial layer formed on the surface of the first conductivity type semiconductor substrate, A first conductivity type collector region formed in the epitaxial layer on the first conductivity type buried layer so as to reach the first conductivity type buried layer; a base region formed in the collector region; An emitter region formed in the base region, and a first conductivity type insulating region provided outside and surrounding the second conductivity type buried layer and provided in the epitaxial layer so as to penetrate therethrough. That the transistor has A second conductivity type high impurity concentration region provided outside the first conductivity type buried layer and surrounding the first conductivity type buried layer so as to reach from the surface of the epitaxial layer to the second conductivity type buried layer; I have.

Example Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of a T-PNP Tr showing an embodiment of the present invention. This transistor is formed as follows.

First, the impurity concentration is 10 ¹⁴ ~10 ¹⁶ cm ^-3 P ^- -type surface from phosphorus (P) ions of the semiconductor substrate 1 by ion implantation, the sheet resistance (hereinafter, referred to as [rho _S) is 50~100Ω / □ of N ⁺ -type buried layer 2 is formed, then, boron (B) ions are implanted by [rho _S ions are formed simultaneously 10~50Ω / □ P ⁺ type buried layer 3, 3a. Thereafter, an N ⁻ -type epitaxial layer 4 having an impurity concentration of 10 ¹⁴ to 10 ¹⁶ cm ⁻³ is formed.

Next, from the surface of the N ⁻ -type epitaxial layer 4, an N ⁺ region 5 having ρ _{S of 4} to 10 Ω / □ is formed by phosphorus diffusion using POCl ₃ . At this time, the N ⁺ region 5 is connected to the N ⁺ type buried layer 2 and formed so as to surround a P ⁺ type second collector region 7 described later. Next, boron (B) ions are ion-implanted from the surface of the N ⁻ -type epitaxial layer 4 so that ρ _S is 500 to 3000.
The Ω / □ P-type first collector region 6 is formed. Then BC
The P ⁺ -type second collector region 7 and the P ⁺ -type isolation region 7 a having ρ _{S of 7} to 20 Ω / □ are simultaneously formed by boron diffusion using l ₃ . At this time, the P-type first collector region 6 is connected to the P ⁺ -type buried layer 3, and similarly, the P ⁺ -type second collector region 7 and P ⁺
The mold isolation region 7a is also connected to the P ⁺ buried layers 3 and 3a, respectively. Next, ρ _S becomes 10 by ion implantation of phosphorus (P) ions.
An N-type base region 8 of 0 to 300 Ω / □ is formed.
[Rho _S by phosphorus diffusion using a ₃ to form a N ⁺ -type base contact region 9 of 7~20Ω / □. Next, a P ⁺ -type emitter region having a ρ _{S of 10} to 20 Ω / □ by boron diffusion using BCl _3.
10 and a P ⁺ type collector contact region 10a are formed simultaneously. Finally, the oxide film 11 is selectively etched to form contact openings at predetermined locations in the emitter, base and collector regions, and the electrodes 12, 13 and 14 are formed.

In the T.PNPTr thus formed, since the N ⁺ region 5 exists in the epitaxial layer 4, the emitter injection efficiency of the parasitic PNP transistor is significantly reduced. Therefore, even if T.PNPTr enters the saturation region and the parasitic PNPTr conducts, the collector current of the parasitic PNPTr, that is, the substrate current _ISUB does not increase rapidly as shown in FIG.

The T-PNPTr has been described above, but the present invention can be applied to general vertical bipolar transistors.

[Effects of the Invention] As described above, the present invention surrounds the periphery of the P ⁺ -type second collector region 7 in the N ⁻ -type epitaxial layer 4 and
According to the present invention, since the N ⁺ -type region 5 connected to the N ⁺ -type buried layer 2 and having a higher concentration than the N ⁻ -type epitaxial layer 4 is provided inside the P ⁺ -type insulating isolation region 7a, When T • PNPTr is saturated and the parasitic PNP becomes conductive, the P ⁺ type second collector region 7 and the P ⁺ type buried layer (emitter of the parasitic PNPTr) are injected into the N ⁻ type epitaxial layer 4 (the base of the parasitic PNPTr). An electric field that prevents injection is formed for the hole
H _FE is reduced, and a rapid increase in the substrate current I _SUB can be prevented.

Therefore, according to the present invention, it is possible to suppress unnecessary current consumption and heat generation in the vertical bipolar transistor used in the saturation region.

[Brief description of the drawings]

FIG. 1 is a sectional view showing an embodiment of the present invention, and FIG.
FIG. 3 is a cross-sectional view showing a conventional example, FIG. 3 is an explanatory view of a parasitic transistor generation place of the conventional example, FIG. 4 is an equivalent circuit diagram of FIG.
FIG. 5 is an operation characteristic diagram of the conventional example and one embodiment of the present invention. 1 ... P ^- type semiconductor substrate, 2 ... N ⁺ type buried layer, 3, 3a ...
P ⁺ -type buried layer, 4 ...... N ^- -type epitaxial layer, 5 ...... N ⁺ region, 6 ...... P-type first collector region, 7 ...... P ⁺ -type second collector region, 7a ...... P ⁺ -type isolation region, 8 ...... N-type base region, 9 ...... N ⁺ -type base contact region, 10 ...... P ⁺ -type emitter region, 10a ...... P ⁺ -type collector contact region, 11
……Oxide film.

Claims (1)

(57) [Claims] 1. A semiconductor substrate of a first conductivity type, a buried layer of a second conductivity type formed on a surface of the semiconductor substrate of the first conductivity type, and a buried layer on a surface of the buried layer of the second conductivity type. A first conductivity type buried layer formed within the range of: a second conductivity type epitaxial layer formed on the first conductivity type semiconductor substrate; and a second conductivity type buried layer formed on the first conductivity type buried layer. A first conductivity type collector region formed to reach the first conductivity type buried layer, a second conductivity type base region formed in the collector region, and a first conductivity type base region formed in the base region. The vertical bipolar transistor, comprising: a conductive type emitter region; and a first conductive type insulating isolation region penetrating the epitaxial layer and surrounding the second conductive type buried layer. Surrounding the conductive type buried layer and extending from the surface of the epitaxial layer Vertical bipolar transistor, characterized in that a high impurity concentration region of the second conductivity type is provided to reach the second conductivity type buried layer.