JPH09283534A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device which can have large base resistance by narrowing a base current path, and can improve a clamp characteristics by reducing an ON current of an electrostatic destruction preventing element. SOLUTION: N type buried layers 112 are formed on areas of a surface of a P type semiconductor substrate 111 and at the same time, ring-shaped N type buried layers 113 are formed on areas of the substrate surface not formed with the N type buried layers 112, and then an N type epitaxial layer 121 is formed on the substrate 111. A P type well layer 131 is formed to cover the N type buried layers 113. Ring-shaped N type collector diffusion layers 142 are formed so that the layers 142 come into contact with the N type buried layers 113 and the N type buried layers 113 inwardly protrude. At the same time, an N type emitter diffusion layer 141 is formed so as not to come into contact with the N type buried layers 113 inside of the N type collector diffusion layers 142.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing an electrostatic breakdown protection device mounted on a bipolar LSI.

[0002]

2. Description of the Related Art Conventionally, techniques in such a field include:
For example, there are the following. FIG. 3 is a cross-sectional process diagram of a method of manufacturing a lateral NPN transistor for preventing electrostatic breakdown, which is mounted on such a conventional bipolar LSI.

(A) First, arsenic (A) is ion-implanted into a P-type semiconductor substrate 311 having a specific resistance of about 10 to 30 Ωcm.
type s). At this time, a region where arsenic is not implanted is created by photolithography. Then, heat treatment is performed to diffuse arsenic and form an N-type buried layer 312 having a sheet resistance of about 30Ω / □. (B) Next, an N-type epitaxial layer 321 having a thickness of 1.0 μm and a specific resistance of about 1.0 Ω is formed on the surface of the P-type semiconductor substrate 311 by epitaxial growth.

(C) Next, by photolithography and ion implantation, boron is implanted in a region where the N-type buried layer 312 is not formed, and heat treatment is performed to obtain a surface concentration of 5
E16ions / cm ³ A P well diffusion layer 331 having a depth of about 3.0 μm is formed. (D) Next, phosphorus (P) is added to the P-well diffusion layer 331 by photolithography and ion implantation at 1E16ions / c.
As shown in FIG. 4, a ring-shaped N-type collector diffusion layer 34 was formed by performing m ² implantation and heat treatment at 1000 ° C. for about 30 minutes.
2 and the N-type emitter diffusion layer 341 is formed inside thereof.

At this time, the N-type collector diffusion layer 342 and N
The spacing between the type emitter diffusion layers 341 is 2.0 to 3.0 μm.
About. The base potential is taken from the back surface of the substrate. After that, a horizontal NPN for preventing electrostatic breakdown is performed by the steps of forming an insulating film, forming a contact, wiring, etc. by a normal process.
A transistor is formed.

[0006]

However, the manufacturing method of the lateral NPN transistor described above has the following problems. Figure 5 shows a horizontal NP for electrostatic breakdown prevention
FIG. 6 is a circuit diagram when an N-transistor is used, and FIG. 6 is a diagram showing a clamp current characteristic when the potential of PAD changes.

When the PAD current becomes more negative than the ground, the CB junction becomes forward biased and the clamp current immediately starts to flow. However, when the PAD potential is on the positive side, the CB junction is reverse biased, so that a current starts to flow between CB after reaching the CB junction breakdown voltage (BVcbo). After that, the potential of B rises from the ground potential due to the influence of the base resistance (Rbase), the junction between E and B is forward-biased, a bipolar operation starts, and a current flows between C and E. After reaching Ion)
The voltage drops to the C-E breakdown voltage (BVceo).

As for the clamping characteristic of the electrostatic breakdown preventing element, when the on-current (Ion) is large, the power consumption of the protective element itself becomes large and the element is easily broken, and a high voltage is applied to the internal element for a long time. Therefore, there is a problem that the internal element is also easily broken. Therefore, the on-current (Ion)
Must be as small as possible, and the on-current (Io
In order to reduce n), the base resistance (Rbase)
Needs to be as large as possible.

In view of the above problems, the present invention is a semiconductor device capable of improving the clamp characteristics by narrowing the current path of the base, increasing the base resistance, and reducing the on-current of the electrostatic breakdown preventing element. It aims at providing the manufacturing method of.

[0010]

In order to achieve the above object, the present invention provides (1) a buried layer having a second conductivity type on a part of the surface of a semiconductor substrate (111) having a first conductivity type. (11
2) and simultaneously forming a ring-shaped buried layer (113) having a second conductivity type in a region where the buried layer (112) is not formed, and the semiconductor substrate (11).
1) A step of forming an epitaxial layer (121) having a second conductivity type on the surface of 1), and forming a well layer (131) having a first conductivity type so as to cover the ring-shaped buried layer (113). And a ring-shaped collector diffusion layer (142) having a second conductivity type so that the ring-shaped buried layer (113) contacts the ring-shaped buried layer (113) and the ring-shaped buried layer (113) protrudes inward. To form
At the same time, a step of forming an emitter diffusion layer (141) having a second conductivity type inside the ring-shaped collector diffusion layer (142) so as not to contact the ring-shaped buried layer (113). It was done.

(2) A first substrate having a first conductivity type, a second substrate having a second conductivity type on a part of the surface of a semiconductor substrate (211).
Embedded layer (212) and the first embedded layer (2
12) in the region where the first buried layer (21) is not formed.
2) forming a second buried layer (213) having a second conductivity type having a surface concentration lower than that of 2), and an epitaxial layer (221) having a second conductivity type on the surface of the semiconductor substrate (211). Forming a well diffusion layer (231) having a first conductivity type so as to cover the second buried layer (213), and not contacting the second buried layer (213). Forming a ring-shaped collector diffusion layer (242) having a second conductivity type,
At the same time, a step of forming an emitter diffusion layer (241) having a second conductivity type inside the ring-shaped collector diffusion layer (242) so as not to contact the second buried layer (213). It was done.

[0012]

[Action]

(1) According to the method of manufacturing a semiconductor element of claim 1,
A lateral semiconductor device (bipolar transistor) has an active region near the surface, and P from the surface to the back surface of the substrate.
The resistance of the mold region becomes the base resistance. Then, by forming the ring-shaped N-type buried layer, it is possible to narrow the current path of the base and increase the base resistance.

Further, it can be realized without increasing the number of manufacturing steps of the bipolar LSI. (2) According to the method of manufacturing a semiconductor element of claim 2,
The horizontal semiconductor device (bipolar transistor) has a second
By forming the N-type buried layer, the current path of the base is narrowed and the base resistance is increased.

Since the second N type buried layer is not in contact with the collector diffusion layer and the emitter diffusion layer, the base resistance can be increased without increasing the capacitance component.

[0015]

Embodiments of the present invention will be described with reference to the drawings. 1 is a sectional view of a semiconductor device in a manufacturing process showing a first embodiment of the present invention, and FIG. 2 is a top view of a semiconductor device showing the first embodiment of the present invention. (A) First, arsenic is implanted into the P-type semiconductor substrate 111 having a specific resistance of about 10 to 30 Ωcm by ion implantation. At this time, an area where arsenic is not implanted and a ring-shaped area where arsenic is implanted are formed by photolithography.

Thereafter, heat treatment is performed to diffuse arsenic to form an N-type buried layer 112 and a ring-shaped N-type buried layer 113 having a sheet resistance of about 30Ω / □. (B) Next, on the surface of the P-type semiconductor substrate 111, the thickness is 1.0 μm and the specific resistance is 1.0 Ωcm by epitaxial growth.
The N-type epitaxial layer 121 is formed to some extent.

(C) Next, boron is implanted by photolithography and ion implantation so as to cover the ring-shaped N-type buried layer 113, and heat treatment is performed to obtain a surface concentration of 5E.
16 ions / cm ³ A P well diffusion layer 131 having a depth of about 3.0 μm is formed. (D) Next, phosphorus is implanted into the P-well diffusion layer 131 by photolithography and ion implantation at 1E16 ions / cm ² and heat treatment is performed at 1000 ° C. for about 30 minutes to diffuse a ring-shaped N-type collector as shown in FIG. The layer 142 and the N-type emitter diffusion layer 141 are formed inside the layer 142.

At this time, the ring-shaped N-type collector diffusion layer 142 overlaps with the ring-shaped N-type buried layer 113, and the ring-shaped N-type buried layer 113 is formed so as to protrude inside, and the N-type emitter diffusion layer 141 is formed. Is formed so as not to contact the ring-shaped N-type buried layer 113. After that, the steps of forming an insulating film, forming a contact, wiring, etc. are performed by usual steps to prevent electrostatic breakdown from occurring in the lateral NPN.
A transistor is formed.

As described above, since the ring-shaped N-type buried layer 113 is formed in this embodiment, the current path of the base can be narrowed and the base resistance can be increased. FIG. 7 is a sectional view of a semiconductor device manufacturing process showing the second embodiment of the present invention, and FIG. 8 is a top view of the semiconductor device showing the second embodiment of the present invention. (1) First, as shown in FIG.
Arsenic is implanted into the P-type semiconductor substrate 211 of about 0 Ωcm by ion implantation. At this time, an area where arsenic is not implanted is created by photolithography. Then, heat treatment is performed to diffuse arsenic and form a first N-type buried layer 212 having a sheet resistance of about 30 Ω / □.

Then, arsenic is implanted into a region where the first N-type buried layer 212 is not formed by photolithography and ion implantation to perform heat treatment, so that the surface concentration becomes 1E.
A second N-type buried layer 213 having a depth of about 15 μions / cm ³ and 1.0 μm is formed. (2) Next, as shown in FIG. 7B, a thickness of 1.0 is formed on the surface of the P-type semiconductor substrate 211 by epitaxial growth.
N-type epitaxial layer 2 having a specific resistance of about 1.0 Ωcm
21 are formed.

(3) Next, as shown in FIG. 7 (c), boron (B) is implanted by photolithography and ion implantation so as to cover the second N-type buried layer 213, and heat treatment is performed. A P well diffusion layer 231 having a surface concentration of 5E16 ions / cm ^{3 and a} depth of about 3.0 μm is formed.
At this time, the upper portion of the second N-type buried layer 213 is P
It is not affected by the well diffusion layer 231 and the depth becomes about half.

(4) Then, as shown in FIG.
P-well diffusion layer 231 by photolithography and ion implantation
Phosphorus is injected into the tube at 1E16ions / cm ² for 100
A heat treatment is performed at 0 ° C. for about 30 minutes to form a ring-shaped N-type collector diffusion layer 242 and an N-type emitter diffusion layer 241 inside thereof, as shown in FIG. At this time, the second N-type buried layer 213 is formed so that the N-type emitter diffusion layer 241 and the ring-shaped N-type collector diffusion layer 242 do not come into contact with each other.

After that, the steps of forming an insulating film, forming a contact, wiring, etc. are performed by usual steps to form a lateral NPN transistor for preventing electrostatic breakdown. In this embodiment, since the second N-type buried layer 213 is formed, the base current path can be narrowed and the base resistance can be increased. Further, in this embodiment, the second N-type buried layer 213 is not in contact with the collector diffusion layer or the emitter diffusion layer, so that the base resistance can be increased without increasing the capacitance component.

It should be noted that the present invention is not limited to the above embodiment, but various modifications are possible based on the spirit of the present invention, and these are not excluded from the scope of the present invention.

[0025]

As described above in detail, (1) According to the first aspect of the invention, in the lateral semiconductor device (bipolar transistor), the vicinity of the surface becomes the active region, and from the vicinity of the surface to the back surface of the substrate. The resistance of the P-type region of becomes the base resistance. Then, by forming the ring-shaped N-type buried layer, it is possible to narrow the current path of the base and increase the base resistance.

Further, it can be realized without increasing the number of manufacturing steps of the bipolar LSI. (2) According to the second aspect of the invention, in the lateral semiconductor device (bipolar transistor), by forming the second N-type buried layer, the base current path is narrowed and the base resistance is increased. did.

Since the second N-type buried layer is not in contact with the collector diffusion layer and the emitter diffusion layer, the base resistance can be increased without increasing the capacitance component.

[Brief description of drawings]

FIG. 1 is a cross-sectional view illustrating a manufacturing process of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a top view of the semiconductor device showing the first embodiment of the present invention.

FIG. 3 is a cross-sectional process diagram of a method for manufacturing a lateral NPN transistor for preventing electrostatic breakdown, which is mounted on a conventional bipolar LSI.

FIG. 4 is a top view of a lateral NPN transistor for preventing electrostatic breakdown, which is mounted on a conventional bipolar LSI.

FIG. 5 is a circuit diagram when a lateral NPN transistor for preventing electrostatic breakdown is used.

FIG. 6 is a diagram showing a clamp current characteristic when the potential of PAD changes.

FIG. 7 is a sectional view of a semiconductor device manufacturing process showing the second embodiment of the present invention.

FIG. 8 is a top view of a semiconductor device showing a second embodiment of the present invention.

[Explanation of symbols]

 111, 211 P-type semiconductor substrate 112 N-type buried layer 113 Ring-shaped N-type buried layer 121,221 N-type epitaxial layer 131,231 P-well diffusion layer 141,241 N-type emitter diffusion layer 142,242 Ring-shaped N-type Collector diffusion layer 212 First N-type buried layer 213 Second N-type buried layer

Claims (2)

[Claims] 1. A buried layer (112) having a second conductivity type is formed on a part of a surface of a semiconductor substrate (111) having a first conductivity type, and at the same time, the buried layer (1).
12) a step of forming a ring-shaped buried layer (113) having a second conductivity type in a region where the second conductivity type is not formed, and (b) an epitaxial layer having a second conductivity type on the surface of the semiconductor substrate (111) ( 121), and (c)
First to cover the ring-shaped buried layer (113)
Forming a well layer (131) having a conductivity type, and (d) contacting the ring-shaped buried layer (113) and projecting the ring-shaped buried layer (113) inward. A ring-shaped collector diffusion layer (142) having a conductivity type of 2 is formed, and at the same time, a second collector diffusion layer (142) is formed inside the ring-shaped collector diffusion layer (142) so as not to come into contact with the ring-shaped buried layer (113). And a step of forming an emitter diffusion layer (141) having a conductivity type. 2. (a) A first substrate having a second conductivity type on a part of a surface of a semiconductor substrate (211) having a first conductivity type.
Embedded layer (212) and the first embedded layer (21
2) in the region where the second buried layer (21) is not formed.
2) forming a second buried layer (213) having a second conductivity type having a surface concentration lower than that of 2), and (b) an epitaxial layer having a second conductivity type on the surface of the semiconductor substrate (211). And (c) forming a well diffusion layer (231) having a first conductivity type so as to cover the second buried layer (213).
(D) A ring-shaped collector diffusion layer (242) having a second conductivity type is formed so as not to come into contact with the second buried layer (213), and at the same time, the ring-shaped collector diffusion layer (242) is formed. The second buried layer (21
3) The step of forming an emitter diffusion layer (241) having the second conductivity type so as not to contact with 3).