JPH0695522B2 - Method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a bipolar element.

[Conventional technology]

Conventionally, in a semiconductor device having a bipolar element,
PNP transistors are often used together with NPN transistors. Among the PNP transistors, the triple diffusion type PNP transistor (hereinafter referred to as T-PNP) has a high current amplification factor (hereinafter referred to as h _FE ), the expansion of h _FE with respect to the collector current (hereinafter referred to as Ic _max ), the cutoff frequency ( Since it has excellent characteristics such as high f _T ) and has very good complementarity with the NPN transistor, it has attracted particular attention.

For example, FIG. 2 shows a configuration in which an NPN transistor and a T-PNP transistor are formed on one semiconductor substrate. As shown, an N-type first buried layer 2 and an N ⁺ -type second buried layer 3 are formed on a P ⁻ -type semiconductor substrate 1, and a P ⁺ -type third buried layer 4 is further formed on the N ⁻ -type semiconductor substrate 1. The epitaxial layer 5 is formed.

Then, in the T-PNP transistor portion, the P-type collector region 6 is formed, and the P ⁺ -type collector wall region 7a and the P ⁺ -type isolation region 7b are formed, and then the N-type base region 8 and the P ⁺ -type emitter region are formed. Forming 10.

Further, in the NPN transistor portion, the P-type base region 9 is formed, and further, the N ⁺ -type emitter region 11a and the N ⁺ collector contact region 11b are formed.

Recently, this T-PNP transistor is often applied to the output stage of power integrated circuits, power integrated circuits, etc.
Development of low saturation T-PNP transistors is underway. In order to achieve low saturation in a T-PNP transistor, it is essential to increase the concentration of the buried layer, and it is necessary to form a buried layer having an impurity concentration profile of at least 10 ¹⁸ cm ^{-3 on the} surface. is necessary.

The T-PNP transistor formed in this way has very good characteristics, and its range of application is expanding more and more.

[Problems to be solved by the invention]

However, in integrated circuits for power supplies, the maximum rated voltage is 35
Since the device has a relatively high breakdown voltage of V or higher, it is necessary to increase the emitter-collector breakdown voltage (hereinafter referred to as BV _CED ) of 40V or higher for both the NPN transistor and T-PNP transistor. In addition, in a power integrated circuit for vehicles, it is also necessary to increase the emitter-base short-collector breakdown voltage (hereinafter referred to as BV _CES ) to 70V or higher to prevent surge damage. From these requirements, the specific resistance of the epitaxial layer (epitaxial layer 5 in FIG. 2) forming the element is set to 3
Ω · cm or more is required.

However, conventionally, since the epitaxial layer is grown after the P ⁺ -type high-concentration buried layer 4 used in the low-saturation T-PNP transistor is formed, a relatively low-concentration growth is achieved.
Even when the epitaxial layer is formed by the SiH ₄ source, boron is likely to be auto-doped from the P ⁺ type buried layer. Therefore, as shown in the impurity concentration profile of the AA line portion in FIG. 2 in FIG. 3, the impurities in the epitaxial layer 5 are offset and the specific resistance increases, and the variation in the specific resistance also increases. Has caused a significant drop in.

In addition, regarding the electrical characteristics of the transistor, especially NP
Lowering of h _FE of N transistor, collector series resistance (hereinafter n
_SC ) and the decrease in Ic _max due to the pseudo saturation effect of the transistor.

An object of the present invention is to provide a method for manufacturing a semiconductor device capable of growing an epitaxial layer that prevents an increase in resistivity.

[Means for solving problems]

A method of manufacturing a semiconductor device according to the present invention includes a step of forming a buried layer of one conductivity type on a semiconductor substrate, and a first epitaxial of reverse conductivity type having a specific resistance of less than 2 Ωcm and a thickness of 3 to 5 μm on the semiconductor substrate. A step of forming a layer and a step of forming a second conductivity type second epitaxial layer having a specific resistance of 3 Ωcm or more on the second epitaxial layer by eliminating the influence of the buried layer in the second epitaxial layer. It prevents the increase of resistivity.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

1 (a) to 1 (c) are structural sectional views showing an embodiment of the present invention in the order of manufacturing steps. Here, a T-PNP transistor and an NPN transistor are integrally formed on one semiconductor substrate. 2 shows an example of forming the structure shown in FIG.

First, as shown in FIG. 1 (a), the impurity concentration is 10 ¹⁴ to 10
P (phosphorus) is ion-implanted into the T-PNP transistor forming portion from the surface of the P ⁻ type substrate 1 of ¹⁶ cm ⁻³ , and N of 30 to 100 Ω / □ is obtained.
The mold first buried layer 2 is formed. Next, diffuse Sb (antimony) or As (arsenic) into the NPN transistor part,
An N ⁺ type second buried layer 3 of Ω / □ is formed. Furthermore, T-PNP
BCl ₃ (boron chloride) is diffused in the transistor portion and the isolation region portion to form a P ⁺ -type third buried layer 4 of 7 to 20 Ω / □.
The order of the first burying layer 2 and the second burying layer 3 may be reversed.

Next, as shown in FIG. 1 (b), the N ⁻ -type first epitaxial layer 5A having a thickness of 0.5 to 2.0 Ωcm is grown to a thickness of 3 to 5 μm by a thermal decomposition reaction of SiH ₄ at about 1050 ° C.

Then, when BV _CEO ≧ 40 V is required as shown in FIG. 1 (c), the N ⁻ type second epitaxial layer 5B having a resistance of 3 Ωcm or more is formed.
Is similarly grown to an appropriate thickness using a thermal decomposition reaction of SiH ₄ at about 1050 ° C.

After that, the same T-PNP transistor and NPN transistor as those in FIG. 2 are formed by the above-mentioned steps, but the description thereof is omitted here.

Therefore, according to this method, the first epitaxial layer 5A
And then the second epitaxial layer with a desired resistivity is formed.
Since 5B is formed, the P ⁺ -type third buried layer 4 having a particularly high concentration is masked by the first epitaxial layer 5A during the growth of the second epitaxial layer 5B.
Autodoping of P-type impurities from the P ⁺ -type third buried layer 4 can be prevented. As a result, the concentration profile shown by the broken line in FIG. 3 is obtained, an increase or variation in the specific resistance of the N type epitaxial layer 5B can be prevented, and the yield can be improved. Regarding the electrical characteristics of the transistor, it is possible to effectively prevent a decrease in h _FE of the NPN transistor, an increase in n _SC , and a decrease in Ic _max due to the pseudo saturation effect of the transistor.

In the present invention, the first and second epitaxial layers 5
Although A and 5B may be grown by a reduction reaction of SiCl ₄ at about 1170 ° C., when the surface concentration of the third buried layer 4 is 10 ¹⁸ cm ⁻³ or more, the growth concentration of SiH ₄ is as low as possible. It is desirable to utilize a thermal decomposition reaction. Further, in this case, the first epitaxial layer 5A may be grown by the thermal decomposition reaction of SiH ₄ , and the second epitaxial layer 5B may be grown by the reduction reaction of SiCl ₄ .

Further, it is needless to say that the present invention is not limited to the above-mentioned embodiment, and the same effect can be obtained even if the conductivity type polarity is changed.

〔The invention's effect〕

As described above, according to the present invention, after the buried layer of one conductivity type is formed on the semiconductor substrate, the first epitaxial layer of the opposite conductivity type having the specific resistance of less than 2 Ωcm and the thickness of 3 to 5 μm is formed on the semiconductor substrate. Since the second epitaxial layer having a specific resistance of 3 Ωcm or more is formed on the epitaxial layer, there is no increase in the specific resistance of the epitaxial layer, the yield is improved, and the NPN transistor formed in this epitaxial layer is improved. It has the effect of preventing the decrease of h _FE , the increase of n _SC , and the decrease of Ic _max , and improving the electrical characteristics.

[Brief description of drawings]

1 (a) to 1 (c) are sectional views showing an embodiment of the present invention in the order of steps, and FIG. 2 is a sectional view of an integrated T-PNP transistor and an NPN transistor formed by a conventional method. 3 is an impurity concentration profile of the AA cross section in FIG. 1 ... P ^- type substrate, 2 ... N type first buried layer, 3 ... N ⁺ type second buried layer, 4 ... P ⁺ type third buried layer, 5 ... N type epitaxial layer,
5A ... N type first epitaxial layer, 5B ... N type second epitaxial layer, 6 ... P type collector region, 7a ... P ⁺ type collector wall region, 7b ... P ⁺ type isolation region, 8 ... N type base region,
9 ... P-type base region, 10 ... P ⁺ -type emitter region, 11a ... N ⁺
Type emitter region, 11b ... N ⁺ collector contact region.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI technical display location H01L 29/73

Claims (1)

[Claims] 1. A method of manufacturing a semiconductor device having a high breakdown voltage triple diffusion bipolar transistor, comprising a step of forming a buried layer of one conductivity type on a semiconductor substrate, and a specific resistance of less than 2 Ωcm on the semiconductor substrate. The method includes the steps of forming a reverse conductivity type first epitaxial layer having a thickness of 3 to 5 μm, and forming a reverse conductivity type second epitaxial layer having a specific resistance of 3 Ωcm or more on the first epitaxial layer. A method of manufacturing a semiconductor device, characterized in that the bipolar transistor is formed in a layer and a second epitaxial layer.