JP2007180472A - Semiconductor device and its fabrication process - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the matter of a conventional semiconductor device that it is difficult to achieve the withstand voltage characteristics of a power semiconductor element and the reduction in device size of a control semiconductor element. <P>SOLUTION: In the inventive semiconductor device, an n-type epitaxial layer 4 is formed on a p-type single crystal silicon substrate 3. A p-type buried diffusion layer 6 is formed on the substrate 3, and an n-type buried diffusion layer 10 is formed on a p-type buried diffusion layer 7 in the substrate 3 and the epitaxial layer 4. With such a structure, creep up of the p-type buried diffusion layer 7 is suppressed, and the epitaxial layer 4 can be made thin while sustaining the withstand voltage characteristics of a power semiconductor element. Furthermore, device size of a control semiconductor element can be reduced. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device for reducing the collector resistance of a vertical PNP transistor used as a power semiconductor element and a method for manufacturing the same.

As an example of a conventional method for manufacturing a semiconductor device, the following vertical PNP transistor manufacturing method is known. A P-type semiconductor substrate is prepared, and two N-type epitaxial layers are formed on the semiconductor substrate. An N type buried diffusion layer is formed over the P type semiconductor substrate and the first epitaxial layer, and a P type buried diffusion layer is formed over the first and second epitaxial layers. Here, after a silicon nitride film is selectively formed above the P type buried diffusion layer on the surface of the second epitaxial layer, the P type buried diffusion layer is thermally diffused. Then, by performing thermal diffusion with the silicon nitride film formed, creeping of the P type buried diffusion layer below the silicon nitride film is suppressed. Further, in the region where the silicon nitride film is not formed thereabove, the P type buried diffusion layer rises and a recess is formed on the upper surface of the P type buried diffusion layer. On the other hand, on the surface of the second epitaxial layer, a LOCOS oxide film is formed in a region other than the formation region of the silicon nitride film. Thereafter, by removing the LOCOS oxide film, an uneven portion is formed on the surface of the second epitaxial layer. Then, a collector region is formed by utilizing the concave portion of the second epitaxial layer and the rising of the P type buried diffusion layer. Further, the base region and the emitter region are formed using the convex portion of the second epitaxial layer and the concave portion of the P type buried diffusion layer. With this manufacturing method, a vertical PNP transistor that increases the emitter-collector breakdown voltage (V _CEO ) of the vertical PNP transistor and decreases the saturation voltage (Vce) can be formed (see, for example, Patent Document 1).
JP 2000-232111 (page 3-4, FIG. 1-3)

  As described above, in a conventional semiconductor device, a power semiconductor element and a control semiconductor element are formed on a single semiconductor substrate. Since the semiconductor substrate is used as the GND potential, a semiconductor substrate having a specific resistance value of, for example, 2 to 4 (Ω · cm) is used to reduce the ground resistance. In this case, the impurity concentration of the P-type semiconductor substrate is relatively high, and in order to form the N-type buried diffusion layer deeply, it is necessary to form the N-type buried diffusion layer having a high impurity concentration. . Therefore, in order to form a deep P type buried diffusion layer in the N type buried diffusion layer in order to reduce the sheet resistance value, it is necessary to form a P type buried diffusion layer having a high impurity concentration. . As a result, a PN junction region having a high impurity concentration is formed, causing problems such as difficulty in adjusting withstand voltage characteristics, and there is a problem in that it is difficult to form a semiconductor element having desired element characteristics.

  In a conventional semiconductor device, for example, a vertical PNP transistor for power and an NPN transistor for control are formed monolithically. In the vertical PNP transistor, it is necessary to increase the thickness of the N-type epitaxial layer in order to improve the breakdown voltage characteristics. On the other hand, in the control NPN transistor, there is a problem that by increasing the film thickness of the epitaxial layer, the lateral diffusion of the isolation region is widened and it is difficult to reduce the device size. That is, by forming the power vertical PNP transistor and the control NPN transistor monolithically, there is a trade-off between the breakdown voltage characteristics of the power vertical PNP transistor and the reduction in the device size of the control NPN transistor. There is a problem of becoming a relationship.

  Further, in the conventional method for manufacturing a semiconductor device, for example, when a vertical PNP transistor for power is formed on a semiconductor substrate having a specific resistance value of 2 to 4 (Ω · cm), the collector region and the substrate are PN-junctioned. There is a problem that it is difficult to increase the diffusion depth of the N type buried diffusion layer to be separated. Therefore, the P type buried diffusion layer used as the collector region cannot be diffused deep in the semiconductor substrate, and there is a problem that it is difficult to reduce the collector resistance.

  In the conventional method for manufacturing a semiconductor device, two epitaxial layers are formed on a P-type semiconductor substrate. A P type buried diffusion layer used as a collector region is formed across the first and second epitaxial layers. Further, the creeping of the P type buried diffusion layer is partially suppressed by the formation region of the silicon nitride film formed on the surface of the second epitaxial layer. However, even in the P type buried diffusion layer located below the silicon nitride film, there is a problem that it is difficult to partially suppress the creeping due to the wraparound of oxygen or the like. Specifically, in the region where the rising of the P-type buried diffusion layer is suppressed, the amount of rising can be suppressed only by about 0.5 (μm) from the region where the rising is performed. Therefore, in order to satisfy the desired withstand voltage characteristics, the epitaxial layer needs to have a two-layer structure, and there is a problem that the manufacturing cost increases.

  Further, in the conventional method for manufacturing a semiconductor device, after a LOCOS oxide film is formed on the surface of the second epitaxial layer, the LOCOS oxide film is removed, and irregularities are formed on the surface of the epitaxial layer. Then, a P-type diffusion layer used as a collector region is formed from the surface of the epitaxial layer in which the recess is formed, and the P-type diffusion layer and the raised region of the P-type buried diffusion layer are connected. However, the silicon nitride film may not be formed in a desired region above the P-type buried diffusion layer due to mask displacement or the like when the silicon nitride film formed on the epitaxial layer is selectively removed. In this case, the overlapping region between the P type diffusion layer and the P type buried diffusion layer is reduced, and the collector resistance cannot be reduced. That is, there is a problem that element characteristics fluctuate due to mask displacement in each process, high-precision alignment is required, and the manufacturing process becomes complicated.

  Further, in a conventional method for manufacturing a semiconductor device, for example, a vapor phase epitaxial growth apparatus using a vertical reactor is used to form an epitaxial layer on a semiconductor substrate. When the epitaxial layer is formed, there is a problem that boron (B), which is a P-type impurity diffused in the semiconductor substrate, is easily auto-doped. In particular, when the amount of impurities introduced is increased in order to reduce the sheet resistance value in the buried diffusion layer, the amount of autodoping increases.

  The semiconductor device of the present invention is made in view of the above-described circumstances, and includes a one-conductivity-type semiconductor substrate, a reverse-conductivity-type epitaxial layer formed on the semiconductor substrate, and at least the semiconductor substrate. A first conductivity type first buried diffusion layer formed, the second conductivity diffusion layer of one conductivity type formed as a collector region formed over the semiconductor substrate and the epitaxial layer, and the semiconductor substrate; And a first buried diffusion layer of a reverse conductivity type formed between the semiconductor substrate and the second buried diffusion layer of one conductivity type. Two buried diffusion layers overlapping each other and their formation region, and a second conductivity diffusion type second buried diffusion layer rising from the upper surface of at least the one conductivity type second buried diffusion layer, and from the surface of the epitaxial layer Formed and base region and A reverse conductivity type diffusion layer used as a collector region, a first conductivity type diffusion layer formed from the surface of the epitaxial layer and used as a collector region, and a reverse conductivity type diffusion layer formed as an emitter region. And a second diffusion layer of one conductivity type. Therefore, in the present invention, the second buried diffusion layer of one conductivity type used as the collector region is suppressed from rising, but can be reduced to the deep part of the substrate, thereby reducing the collector resistance. .

  In addition, the semiconductor device of the present invention includes an isolation region that partitions the semiconductor substrate and the epitaxial layer into a plurality of element formation regions, and the one conductivity type first buried diffusion layer includes the plurality of elements. It is formed over the formation region. Therefore, in the present invention, the specific resistance value of the semiconductor substrate can be adjusted by the first buried diffusion layer of one conductivity type.

  In the semiconductor device of the present invention, the specific resistance value of the semiconductor substrate is 40 to 60 (Ω · cm). Therefore, in the present invention, by using a semiconductor substrate having a low impurity concentration, the reverse conductivity type first buried diffusion layer and the one conductivity type second buried diffusion layer can be diffused to the deep part of the substrate.

  The semiconductor device of the present invention is characterized in that the first conductivity type buried diffusion layer is diffused from the surface of the semiconductor substrate to 15 to 20 (μm). Therefore, in the present invention, the first one conductivity type buried diffusion layer can prevent the ground resistance value from increasing.

  According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: preparing a one-conductivity-type semiconductor substrate; forming a reverse-conductivity-type first buried diffusion layer on the semiconductor substrate; Forming a first conductivity type first buried diffusion layer over a region wider than the first buried diffusion layer, and overlapping the formation region of the first conductivity diffusion region with the opposite conductivity type. Forming a second conductive diffusion layer of one conductivity type on the semiconductor substrate, and ionizing a reverse conductivity type impurity in the region where the second buried diffusion layer of one conductivity type is formed. Implanting and forming a reverse conductivity type second buried diffusion layer, forming a reverse conductivity type epitaxial layer on the semiconductor substrate, and using the first conductivity type as a collector region from the surface of the epitaxial layer Diffusion layer, reverse conductivity type diffusion layer used as a base region, and emitter Characterized by a step of forming a second diffusion layer of one conductivity type to be used as a pass. Therefore, in the present invention, by forming the first buried diffusion layer of one conductivity type after forming the first buried diffusion layer of reverse conductivity type on the semiconductor substrate having a low impurity concentration, the reverse conductivity is achieved up to the deep part of the substrate. A first buried diffusion layer of the mold can be formed.

  In the method of manufacturing a semiconductor device according to the present invention, in the step of forming the one conductivity type first buried diffusion layer, the one conductivity type first buried diffusion layer is formed on the entire surface of the semiconductor substrate. It is characterized by that. Therefore, according to the present invention, it is possible to prevent an increase in ground resistance even in a plurality of element formation regions formed on the semiconductor substrate.

  The method of manufacturing a semiconductor device according to the present invention is characterized in that a thermal oxidation process is performed on the semiconductor substrate before the step of ion-implanting impurities forming the second buried diffusion layer of the reverse conductivity type. To do. Therefore, in the present invention, the reverse conductivity type impurity is ion-implanted in a state where the impurity concentration of the surface of the second buried diffusion layer of one conductivity type and the vicinity thereof is lowered. By this manufacturing method, it is possible to suppress the creeping of the one conductivity type second buried diffusion layer. Further, when the epitaxial layer is formed, the amount of auto-doping of one conductivity type impurity can be reduced.

  Further, in the method of manufacturing a semiconductor device according to the present invention, the thermal oxidation step and the step of ion-implanting the impurity for forming the second conductivity type buried diffusion layer are performed in a non-oxidizing atmosphere. This heat treatment step is not performed. Therefore, in the present invention, the reverse conductivity type second buried diffusion layer can be efficiently formed by ion-implanting the reverse conductivity type impurity into the region where the impurity concentration of one conductivity type is low.

  In the present invention, a vertical PNP transistor for power is formed on a semiconductor substrate having a low impurity concentration. With this structure, the buried diffusion layer used as the collector region can be formed deep in the semiconductor substrate, and the collector resistance can be reduced.

  In the present invention, a P type buried diffusion layer is formed on the entire surface of the semiconductor substrate. With this structure, an increase in ground resistance can be prevented in a plurality of element formation regions.

  Further, according to the present invention, the rising width of the buried diffusion layer used as the collector region of the vertical PNP transistor for power is partially suppressed. With this structure, the thickness of the epitaxial layer can be reduced while maintaining the breakdown voltage characteristics.

  Further, in the present invention, in the vertical NPN transistor for control, the lateral diffusion of the isolation region is suppressed by reducing the thickness of the epitaxial layer. With this structure, the device size of the vertical NPN transistor is reduced.

  In the present invention, the buried diffusion layer used as the collector region of the vertical PNP transistor has a region that rises. Then, the collector resistance can be reduced by increasing the impurity concentration in the raised region and using it as a connecting region of the collector region.

  In the present invention, after the N type buried diffusion layer is formed on the P type semiconductor substrate having a low impurity concentration, the P type buried diffusion layer is formed on the entire surface of the semiconductor substrate. By this manufacturing method, an N-type buried diffusion layer can be formed up to the deep part of the semiconductor substrate.

  In the present invention, the N type buried diffusion layer is formed in a state where the impurity concentration in the surface of the P type buried diffusion layer used as the collector region of the vertical PNP transistor and in the vicinity thereof is lowered. By this manufacturing method, the creeping of the P type buried diffusion layer can be suppressed.

  In the present invention, the epitaxial layer is deposited in a state where the N type buried diffusion layer is formed so as to overlap with the P type buried diffusion layer used as the collector region of the vertical PNP transistor. By this manufacturing method, the P-type impurity concentration on the substrate surface can be reduced and the amount of autodoping can be reduced.

In the present invention, a P-type impurity such as boron (B) is ion-implanted at an acceleration voltage of 100 (keV) and an introduction amount of about 8.0 × 10 ¹² (/ cm ² ), so that When the buried diffusion layer of the type is formed, even if the specific resistance value of the semiconductor substrate is 40 to 60 (Ω · cm), the collector resistance of the vertical NPN transistor and the vertical PNP transistor does not increase, and the specific resistance A ground resistance almost the same as a ground resistance of about 2 kΩ having a value of 2 to 4 (Ω · cm) can be obtained.

  Hereinafter, a semiconductor device according to an embodiment of the present invention will be described in detail with reference to FIGS. FIG. 1 is a cross-sectional view for explaining the semiconductor device in this embodiment. FIG. 2A is a cross-sectional view for explaining the vertical PNP transistor in this embodiment. FIG. 2B is a cross-sectional view for describing the vertical PNP transistor in this embodiment. FIG. 3 is a diagram for explaining the concentration profile of the vertical PNP transistor in the present embodiment. FIG. 4A is a diagram for explaining the sheet resistance value and the creeping width of the buried diffusion layer of the semiconductor device in the present embodiment. FIG. 4B is a diagram for explaining the withstand voltage characteristics of the semiconductor device in this embodiment.

  As shown in FIG. 1, a vertical PNP transistor 1 and a vertical NPN transistor 2 are monolithically formed on a P-type single crystal silicon substrate 3. For example, the vertical PNP transistor 1 is used as a power semiconductor element, and the vertical NPN transistor 2 is used as a control semiconductor element. In other element formation regions, a large-area NPN power transistor or the like is formed as a power semiconductor element, and a small-area NPN transistor or the like is formed as a control semiconductor element. The vertical PNP transistor 1 mainly includes a P-type single crystal silicon substrate 3, an N-type epitaxial layer 4, an N-type buried diffusion layer 5, a P-type buried diffusion layer 6, P type buried diffusion layers 7, 8, and 9 used as collector regions, N type buried diffusion layers 10, 11, and 12, N type diffusion layers 13 and 14 used as base regions, and emitter regions P-type diffusion layer 15 used as a collector region, P-type diffusion layers 16 and 17 used as a collector region, and N-type diffusion layers 18 and 19.

The N type epitaxial layer 4 is formed on the P type single crystal silicon substrate 3. The specific resistance value of the substrate 3 is about 40 to 60 (Ω · cm), and a P-type impurity concentration of about 1.0 × 10 ¹⁴ is used.

  The N type buried diffusion layer 5 is formed across the substrate 3 and the epitaxial layer 4. The N type buried diffusion layer 5 is formed to a deeper portion of the substrate 3 than the P type buried diffusion layer 7. The N type buried diffusion layer 5 forms a PN junction region with each of the substrate 3 and the P type buried diffusion layer 7, and separates the substrate 3 from the P type buried diffusion layer 7 with a PN junction. ing. Note that the N type buried diffusion layer 5 in the present embodiment corresponds to the “first conductivity diffusion type buried diffusion layer” of the present invention.

The P type buried diffusion layer 6 is formed over the entire region where the vertical PNP transistor 1 is formed, and is formed to a depth of about 15 to 20 (μm) from the surface of the substrate 3, for example. The P-type buried diffusion layer 6 is formed by ion-implanting a P-type impurity, for example, boron (B) with an introduction amount of 1.0 × 10 ^{12 to} 1.0 × 10 ¹⁴ (/ cm ² ). . Therefore, the P-type buried diffusion layer 6 is a diffusion region having a low impurity concentration, and in the region overlapping with the N-type diffusion region, the overlapping region becomes an N-type region. The formation of the P-type buried diffusion layer 6 on the substrate 3 prevents an increase in ground resistance and solves problems such as latch-up. Various design changes can be made so that the impurity concentration of the P type buried diffusion layer 6 has a desired ground resistance value. The P type buried diffusion layer 6 in the present embodiment corresponds to the “one conductivity type first buried diffusion layer” of the present invention.

  The P type buried diffusion layers 7, 8, 9 are formed across the substrate 3 and the epitaxial layer 4. The P type buried diffusion layers 8 and 9 are arranged in the vicinity of the end of the P type buried diffusion layer 7, and the P type buried diffusion layers 8 and 9 are connected to the P type buried diffusion layer 7. is doing. The P type buried diffusion layers 8 and 9 may be formed in a ring shape near the end of the P type buried diffusion layer 7 or may be formed only in a region to be drawn out as a collector region. The P type buried diffusion layer 7 in the present embodiment corresponds to the “one conductivity type second buried diffusion layer” of the present invention.

  The N type buried diffusion layer 10 rises at least from the upper surface of the P type buried diffusion layer 7 to the surface side of the epitaxial layer 4. On the other hand, the N type buried diffusion layers 11 and 12 are formed across the substrate 3 and the epitaxial layer 4. The N type buried diffusion layers 11 and 12 are arranged so as to surround the P type buried diffusion layers 7, 8 and 9. The N type buried diffusion layer 10 in the present embodiment corresponds to the “second conductivity type second buried diffusion layer” of the present invention.

  An N type diffusion layer 13 is formed in the epitaxial layer 4. An N type diffusion layer 14 is formed in the N type diffusion layer 13. The N type diffusion layer 14 is used as a base extraction region. The N-type diffusion layer 13 in the present embodiment corresponds to the “reverse conductivity type diffusion layer” of the present invention.

  A P type diffusion layer 15 is formed in the N type diffusion layer 13. The P type diffusion layer 15 in the present embodiment corresponds to the “one conductivity type second diffusion layer” of the present invention.

  P-type diffusion layers 16 and 17 are formed in the epitaxial layer 4. The P-type diffusion layers 16 and 17 are disposed so as to surround the N-type diffusion layer 13, and the P-type diffusion layer 16 and the P-type buried diffusion layers 7 and 8 are connected to each other. 17 and the P type buried diffusion layers 7 and 9 are connected. The P-type diffusion layers 16 and 17 may be formed in a ring shape so as to surround the N-type diffusion layer 13 or may be formed only in a region to be drawn out as a collector region. The P type diffusion layers 16 and 17 in the present embodiment correspond to the “one conductivity type first diffusion layer” of the present invention.

  The N type diffusion layers 18 and 19 are formed in the epitaxial layer 4. The N type diffusion layers 18 and 19 are formed in a ring shape so as to surround the P type diffusion layers 16 and 17. The N type diffusion layer 18 and the N type buried diffusion layers 5 and 11 are connected, and the N type diffusion layer 19 and the N type buried diffusion layers 5 and 12 are connected. That is, the N-type diffusion layers 18 and 19 are arranged so as to surround the outer periphery of the P-type diffusion layers 16 and 17 which are collector regions, so that the surface of the epitaxial layer 4 is inverted and the collector current passes through the isolation region. To flow to the substrate 3 through the substrate 3.

An insulating layer 20 is formed on the upper surface of the epitaxial layer 4. The insulating layer 20 is formed of a PSG (Phospho Silicate Glass) film or the like. Then, contact holes 21, 22, and 23 are formed in the insulating layer 20 by dry etching using a CHF ₃ + O ₂ gas, for example, using a known photolithography technique.

  In the contact holes 21, 22, and 23, an aluminum alloy, for example, an Al—Si film 24 is selectively formed, and a collector electrode 25, an emitter electrode 26, and a base electrode 27 are formed.

  On the other hand, the vertical NPN transistor 2 mainly includes a P-type single crystal silicon substrate 3, an N-type epitaxial layer 4, a P-type buried diffusion layer 6, and an N-type buried layer used as a collector region. Diffusion layers 28 and 29, an N type diffusion layer 30 used as a collector region, a P type diffusion layer 31 used as a base region, and an N type diffusion layer 32 used as an emitter region. .

  The N type epitaxial layer 4 is formed on the P type single crystal silicon substrate 3.

  The N type buried diffusion layer 28 is formed across the substrate 3 and the epitaxial layer 4.

  The N type buried diffusion layer 29 is formed so as to overlap the N type buried diffusion layer 28 and its formation region. The N type buried diffusion layer 29 rises from the N type buried diffusion layer 28 to the surface side of the epitaxial layer 4. By forming the N type buried diffusion layer 29, the resistance of the collector region can be reduced. By forming the N type buried diffusion layer 29, the resistance of the collector region can be reduced.

  The N type diffusion layer 30 is formed in the N type epitaxial layer 4. The N type diffusion layer 30 is connected to the N type buried diffusion layer 29 and used as a collector region. The N-type diffusion layer 30 and the N-type buried diffusion layer 29 are connected to reduce the amount of lateral diffusion of the N-type diffusion layer 30 and reduce the device size of the vertical NPN transistor 2. be able to.

  The P type diffusion layer 31 is formed in the epitaxial layer 4.

  The N type diffusion layer 32 is formed in the P type diffusion layer 31.

An insulating layer 20 is formed on the upper surface of the epitaxial layer 4. Then, contact holes 33, 34, and 35 are formed in the insulating layer 20 by dry etching using, for example, a CHF ₃ + O ₂ gas using a known photolithography technique.

  In the contact holes 33, 34, and 35, an aluminum alloy, for example, an Al—Si film 36 is selectively formed, and an emitter electrode 37, a base electrode 38, and a collector electrode 39 are formed.

  As shown in FIG. 2A, the P type buried diffusion layers 7, 8 and 9 and the P type diffusion layers 16 and 17 are collector regions of the vertical PNP transistor 1. The N type buried diffusion layer 10, the N type epitaxial layer 4, and the N type diffusion layers 13 and 14 are base regions of the vertical PNP transistor 1. The P type diffusion layer 15 is an emitter region of the vertical PNP transistor 1. On the P type buried diffusion layer 7 formed of P type impurities, for example, boron (B), an N type buried diffusion layer 10 formed of N type impurities, for example, phosphorus (P). Is formed. Then, the P type buried diffusion layer 7 is suppressed from creeping up to the surface side of the epitaxial layer 4. Specifically, the creeping width W1 from the surface of the substrate 3 of the P type buried diffusion layer 7 is about 2.0 to 4.0 (μm). In the case where the N type buried diffusion layer 10 is not formed, the P type buried diffusion layer 7 usually rises about 5.5 (μm) from the surface of the substrate 3. That is, by forming the N type buried diffusion layer 10 on the P type buried diffusion layer 7, the rising width of the P type buried diffusion layer 7 is 1.5 to 3.5 (μm). The degree is suppressed.

  With this structure, in the vertical PNP transistor 1, the thickness of the epitaxial layer 4 can be reduced even when a desired base region width W2 is ensured. For example, the film thickness of the epitaxial layer 4 is about 6.5 to 7.5 (μm). As a result, in the vertical PNP transistor 1 as a power semiconductor element, the thickness of the epitaxial layer 4 is reduced, but the breakdown voltage characteristics can be prevented from deteriorating. On the other hand, in the vertical NPN transistor 2 as the control semiconductor element, the thickness of the epitaxial layer 4 is reduced, so that the lateral diffusion of the isolation region is reduced and the device size is reduced. That is, by suppressing the rising width W1 of the P type buried diffusion layer 7 and by forming the epitaxial layer 4 thin, the power semiconductor element having the desired breakdown voltage characteristic and the device size are reduced. The control semiconductor element is formed monolithically.

  Further, as shown in the figure, the N type buried diffusion layer 5 is formed from the surface of the substrate 3 to about 30 (μm). The P type buried diffusion layer 7 is formed from the surface of the substrate 3 to about 20 (μm). The P type buried diffusion layer 6 is formed from the surface of the substrate 3 to about 15 to 20 (μm). With this structure, a desired width W3 is secured by using the substrate 2, and the collector resistance is reduced. This structure will be described later in detail in a method for manufacturing a semiconductor device. By forming an N-type buried diffusion layer 5 in the state of a substrate 3 having a low impurity concentration, an N-type buried diffusion for PN junction isolation is formed. This is realized by being able to form the layer 5 deep. On the other hand, as described above, the P-type buried diffusion layer 6 is formed on the substrate 3 from the surface of the substrate 3 to about 15 to 20 (μm), thereby adjusting the ground resistance value to a desired range. Can do.

  Here, as shown in FIG. 2B, in the P type buried diffusion layer 7, in the region L1 where the N type buried diffusion layer 10 is formed on the upper surface, the P type buried diffusion layer 7 is formed. The scooping up is suppressed. On the other hand, the N type buried diffusion layer 10 is formed in a region inside the P type buried diffusion layer 7. Therefore, in the regions L2 and L3 where the N type buried diffusion layer 10 is not formed, the P type buried diffusion layer 7 rises toward the surface side of the epitaxial layer 4. In the regions L 2 and L 3, the P type buried diffusion layer 7 is formed so as to surround the N type buried diffusion layer 10. The P type diffusion layers 16 and 17 used as the collector region are connected to the P type buried diffusion layer 7 in the regions L2 and L3. The P-type diffusion layers 16 and 17 are connected to the rising region of the P-type buried diffusion layer 7 so that the collector resistance can be reduced.

  As shown in FIG. 2A, in the regions L2 and L3 where the N-type buried diffusion layer 10 is not formed, the P-type buried diffusion layers 8 and 9 are replaced with the P-type buried diffusion layer. 7 is formed to overlap. As described above, the P type diffusion layer 16 is connected to the P type buried diffusion layers 7 and 8, the P type diffusion layer 17 is connected to the P type buried diffusion layers 7 and 9, and the collector region is connected to the collector region. Forming. With this structure, the collector resistance of the vertical PNP transistor 1 can be further reduced.

  FIG. 3 shows the concentration profile of the vertical PNP transistor 1 on the substrate 3. The dotted line indicates the impurity concentration of the substrate 3, the alternate long and short dash line indicates the impurity concentration of the P-type buried diffusion layer 7, and the two-dot chain line indicates the impurity concentration of the P-type buried diffusion layer 6. The solid line indicates the impurity concentration of the N type buried diffusion layer 5. As shown in the figure, when the alternate long and short dash line is compared with the solid line, the P type buried diffusion layer 7 is formed from the surface of the substrate 3 to about 20 (μm), and the N type buried is formed from 20 (μm) to 30 (μm). It can be seen that this is the diffusion layer 5. On the other hand, as indicated by the two-dot chain line, the P type buried diffusion layer 6 is a low impurity concentration region, and at least one of the N type buried diffusion layer 5 or the P type buried diffusion layer 7 is formed. In some areas, it will be offset.

  As shown in FIG. 4A, the horizontal axis indicates the amount of impurities introduced into the N type buried diffusion layer 10. The vertical axis (left side of the drawing) shows the sheet resistance value of the P type buried diffusion layer 7. The vertical axis (right side of the drawing) shows the rising width W1 (see FIG. 2) of the P-type buried diffusion layer 7. The solid line shows the relationship between the impurity introduction amount of the N type buried diffusion layer 10 and the sheet resistance value of the P type buried diffusion layer 7. The dotted line shows the relationship between the impurity introduction amount of the N type buried diffusion layer 10 and the rising width W1 of the P type buried diffusion layer 7.

  As indicated by the solid line, the sheet resistance value of the P type buried diffusion layer 7 increases as the amount of impurities introduced into the N type buried diffusion layer 10 increases. On the other hand, as indicated by the dotted line, the rising width W1 of the P-type buried diffusion layer 7 decreases as the impurity introduction amount of the N-type buried diffusion layer 10 increases. As the amount of impurities introduced into the N type buried diffusion layer 10 increases, the creeping width W1 of the P type buried diffusion layer 7 decreases, but the sheet resistance value of the P type buried diffusion layer 7 decreases. Increase. On the other hand, as the amount of impurities introduced into the N type buried diffusion layer 10 decreases, the sheet resistance value of the P type buried diffusion layer 7 decreases, but the rising width W1 of the P type buried diffusion layer 7 is as follows. Increase. That is, the sheet resistance value of the P-type buried diffusion layer 7 and the rising width W1 are in a trade-off relationship with the amount of impurities introduced into the N-type buried diffusion layer 10. As a result, the impurity introduction amount of the N-type buried diffusion layer 10 is set to a desired introduction amount according to the relationship between the sheet resistance value of the P-type buried diffusion layer 7 and the creeping width W1.

As shown in FIG. 4B, the horizontal axis indicates the amount of impurities introduced into the N type buried diffusion layer 10. The vertical axis indicates the breakdown voltage (V _CBO ) of the vertical PNP transistor 1. As indicated by the solid line, the withstand voltage (V _CBO ) decreases as the impurity introduction amount of the N type buried diffusion layer 10 increases. This is because the PN junction region formed by the high impurity concentration P type buried diffusion layer 7 and the high impurity concentration N type buried diffusion layer 10 has the breakdown voltage (V _CBO ) of the vertical PNP transistor 1. It is because it is determined. As shown in FIG. 4A, the rising width W1 of the P type buried diffusion layer 7 decreases as the amount of impurities introduced into the N type buried diffusion layer 10 increases. However, the vertical PNP transistor 1 withstand voltage (V _CBO ) is reduced. That is, the amount of impurities introduced into the N-type buried diffusion layer 10 is related to the breakdown voltage (V _CBO ) of the vertical PNP transistor 1, the sheet resistance value of the P-type buried diffusion layer 7, and its rising width W1. Thus, the introduction amount is determined.

  As shown in the figure, the N-type diffusion layer 13 and the N-type buried diffusion layer 10 do not have to be connected to each other. For example, the N-type diffusion layer 13 and the N-type buried diffusion layer 10 may be connected. In this case, the impurity concentration of the N type buried diffusion layer 10 becomes high, and the breakdown voltage in the PN junction region between the P type buried diffusion layer 7 and the N type buried diffusion layer 10 as described above. Considering the characteristics, the impurity concentrations of the N type diffusion layer 13 and the N type buried diffusion layer 10 are set.

  Next, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described in detail with reference to FIGS. 5 to 11 are cross-sectional views for explaining the method of manufacturing a semiconductor device in the present embodiment.

First, as shown in FIG. 5, for example, a P-type single crystal silicon substrate 3 having a specific resistance of about 40 to 60 (Ω · cm) is prepared. A silicon oxide film (not shown) is formed on the substrate 3, and an N-type impurity such as phosphorus (P) is introduced from the surface of the substrate 3 with an acceleration voltage of 90 to 110 (keV) using the silicon oxide film as a mask. Ion implantation is performed with an amount of 1.0 × 10 ^{13 to} 1.0 × 10 ¹⁵ (/ cm ² ). Thereafter, thermal diffusion is performed to form the N type buried diffusion layer 5, and then the silicon oxide film is removed.

Next, a silicon oxide film 40 is deposited on the entire surface of the substrate 3 by about 450 (４５０), for example. Then, a P-type impurity such as boron (B) is accelerated from 90 to 110 (keV) and introduced from 1.0 × 10 ^{12 to} 1.0 × 10 ¹⁴ (/ cm ² ) over the entire surface of the substrate 3. Ion implantation.

Next, as shown in FIG. 6, a photoresist 41 is formed on the silicon oxide film 40. Then, using a known photolithography technique, an opening is formed in the photoresist 41 on the region where the P type buried diffusion layer 7 is to be formed. Thereafter, P-type impurities such as boron (B) are ionized from the surface of the substrate 3 with an acceleration voltage of 90 to 110 (keV) and an introduction amount of 1.0 × 10 ^{14 to} 1.0 × 10 ¹⁶ (/ cm ² ). inject. Then, the photoresist 41 is removed and thermally diffused to form P type buried diffusion layers 6 and 7 simultaneously. At this time, the surface of the substrate 3 is thermally oxidized to form a silicon oxide film 42 (see FIG. 7) on the surface of the substrate 3. In this embodiment, after the N-type buried diffusion layer 5 is formed on the substrate 3 having an impurity concentration of, for example, about 1.0 × 10 ^{14 to} 1.0 × 10 ¹⁵ (/ cm ² ). Then, the P type buried diffusion layer 6 is formed. With this manufacturing method, the N type buried diffusion layer 5 can be formed up to the deep part of the substrate 3 without increasing the amount of introduction when forming the N type buried diffusion layer 5. As a result, the P-type buried diffusion layer 7 can be formed in the N-type buried diffusion layer 5 formed at a low impurity concentration, so that the sheet resistance value in the P-type buried diffusion layer 7 can be reduced. it can.

  Next, as shown in FIG. 7, the silicon oxide film 42 is selectively removed so that an opening is formed on the formation region of the N type buried diffusion layers 11, 12, and 28. Then, using the silicon oxide film 42 as a mask, a liquid source 43 containing an N-type impurity such as antimony (Sb) is applied to the surface of the substrate 3 by a spin coating method. Thereafter, antimony (Sb) is thermally diffused to form N type buried diffusion layers 11, 12, and 28.

  Here, in a state where the silicon oxide film 42 is deposited on the substrate 3, the substrate 3 is placed in an oxidizing atmosphere of 1200 to 1250 (° C.) for about 1 hour to perform thermal oxidation treatment. By this thermal oxidation treatment, boron (B) in the surface of the P type buried diffusion layer 7 and in the vicinity thereof (for example, from the surface of the epitaxial layer 4 to about 3.5 (μm)) is diffused into the silicon oxide film 42. To do. As a result, the concentration of boron (B) in the surface of the P-type buried diffusion layer 7 and in the vicinity thereof, depending on the depth, is reduced to about half before the thermal oxidation treatment. Thereafter, the silicon oxide film 42 is removed.

  In this thermal oxidation treatment, boron (B) existing in a deep region of the substrate 3 is transferred to the surface of the substrate 3 by placing the substrate 3 in an oxidizing atmosphere at least at 1000 (° C.) or higher. It can be prevented from spreading. Alternatively, the substrate 3 may be placed in an oxidizing atmosphere until the thermal oxidation process is completed. By this thermal oxidation treatment, the silicon oxide film 42 is grown from about 6000 to 7000 (Å) to about 10,000 (Å).

Next, as shown in FIG. 8, a silicon oxide film 44 is deposited on the substrate 3 by, for example, about 100 to 450 mm. Next, a photoresist 45 is formed on the silicon oxide film 44. Then, an opening is formed in the photoresist 45 on the region where the N type buried diffusion layers 10, 29, 46, 47 are formed using a known photolithography technique. Thereafter, N-type impurities such as phosphorus (P) are ionized from the surface of the substrate 3 at an acceleration voltage of 30 to 110 (keV) and an introduction amount of 1.0 × 10 ^{13 to} 1.5 × 10 ¹⁵ (/ cm ² ). Implantation is performed to form N type buried diffusion layers 10, 29, 46 and 47. Thereafter, the photoresist 45 is removed.

  At this time, as described above with reference to FIG. 7, the concentration of boron (B) on the surface of the P-type buried diffusion layer 7 and in the vicinity thereof is reduced, so that phosphorus (P) and boron (B) Is reduced, and the amount of phosphorus (P) introduced can be reduced. Further, also in the thermal oxidation process for forming the silicon oxide film 44 on the substrate 3, boron (B) in the surface of the P type buried diffusion layer 7 and in the vicinity thereof diffuses into the silicon oxide film 44.

  Further, when forming the opening in the photoresist 45, the same alignment mark as that used when forming the P type buried diffusion layer 7 is used. With this manufacturing method, the N type buried diffusion layer 10 can be formed with high positional accuracy with respect to the P type buried diffusion layer 7, so that the desired region of the P type buried diffusion layer 7 is prevented from creeping up. be able to.

  In FIG. 8 and subsequent figures, the N type buried diffusion layer 46 is shown integrally with the N type buried diffusion layer 11, and the N type buried diffusion layer 47 is shown integrally with the N type buried diffusion layer 12. Illustrated.

Next, as shown in FIG. 9, a photoresist 48 is formed on the silicon oxide film 44. Then, using a known photolithography technique, an opening is formed in the photoresist 48 on the region where the P type buried diffusion layers 8, 9, 49, 50, 51 are formed. Thereafter, P-type impurities such as boron (B) are ionized from the surface of the substrate 3 with an acceleration voltage of 90 to 180 (keV) and an introduction amount of 0.5 × 10 ^{14 to} 1.0 × 10 ¹⁶ (/ cm ² ). inject. Then, the photoresist 48 is removed.

  Next, as shown in FIG. 10, the substrate 3 is placed on the susceptor of the vapor phase epitaxial growth apparatus, and the epitaxial layer 4 is formed on the substrate 3. The vapor phase epitaxial growth apparatus mainly includes a gas supply system, a reaction furnace, an exhaust system, and a control system. In the present embodiment, the film thickness uniformity of the epitaxial layer can be improved by using a vertical reactor. On the other hand, as described above with reference to FIGS. 7 and 8, the concentration of boron (B) on the surface of the P-type buried diffusion layer 7 and in the vicinity thereof is reduced by the thermal oxidation treatment. Further, an N type buried diffusion layer 10 is formed so as to overlap the P type buried diffusion layer 7. Therefore, when the epitaxial layer 4 is formed on the substrate 3, the amount of boron (B) autodoping can be reduced.

Next, a silicon oxide film 52 is deposited on the epitaxial layer 4 by about 450 (Å), for example. Next, a photoresist 53 is formed on the silicon oxide film 52. Then, using a known photolithography technique, an opening is formed in the photoresist 53 on the region where the N type diffusion layer 12 is to be formed. Using the photoresist 53 as a mask, an N-type impurity, for example, phosphorus (P) is introduced from the surface of the epitaxial layer 4 at an acceleration voltage of 90 to 110 (keV) and an introduction amount of 1.0 × 10 ^{13 to} 1.0 × 10 ¹⁵ ( / Cm ² ). Thereafter, phosphorus (P) is thermally diffused to form an N-type diffusion layer 13 and a thermal oxide film is formed.

  Next, as shown in FIG. 11, the P type diffusion layers 15, 16, 17, 31, 54, 55, and 56 and the N type diffusion layer 14 are formed using a known photolithography technique according to a desired formation method and order. , 18, 19, 30, 32 are formed. The P-type diffusion layer 15 and the P-type diffusion layers 16, 17, 54, 55, and 56 may be formed in the same process or in different processes.

Thereafter, for example, a PSG film or the like is deposited on the epitaxial layer 4 as the insulating layer 20. Then, contact holes 21, 22, 23, 33, 34, and 35 are formed in the insulating layer 20 by using a known photolithography technique, for example, by dry etching using a CHF ₃ + O ₂ gas. In the contact holes 21, 22, 23, 33, 34, and 35, an aluminum alloy, for example, an Al—Si film is selectively formed, and collector electrodes 25 and 39, emitter electrodes 26 and 37, and base electrodes 27 and 38 are formed. Form.

  In this embodiment, the case where the P type buried diffusion layer 6 is formed on the entire surface of the substrate 3 has been described. However, the present invention is not limited to this case. For example, the P type buried diffusion layer 6 may be formed only in a region where the ground resistance is desired to be reduced. In addition, the case where the P type buried diffusion layer 6 is formed from the surface of the substrate 3 to about 15 to 20 (μm) has been described, but the present invention is not limited to this case. For example, the design of the diffusion depth may be changed according to a desired ground resistance value. Further, it may be formed by changing the diffusion depth of the P type buried diffusion layer 6 for each element formation region. The N type buried diffusion layer 10 that suppresses the creeping of the P type buried diffusion layer 7 has been described by being formed by ion implantation of phosphorus (P). However, the present invention is not limited to this case. . For example, arsenic (As) or the like may be used as the N-type impurity. In addition, various modifications can be made without departing from the scope of the present invention.

It is sectional drawing explaining the semiconductor device in embodiment of this invention. 1A is a cross-sectional view and FIG. 1B is a cross-sectional view illustrating a semiconductor device according to an embodiment of the present invention. It is a figure for demonstrating the concentration profile of the semiconductor device in embodiment of this invention. It is a figure for demonstrating the sheet resistance value and creeping width of the (A) buried diffused layer of the semiconductor device in embodiment of this invention, (B) It is a figure for demonstrating a pressure | voltage resistant characteristic. It is sectional drawing explaining the manufacturing method of the semiconductor device in embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device in embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device in embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device in embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device in embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device in embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device in embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Vertical PNP transistor 2 Vertical NPN transistor 3 P type single crystal silicon substrate 4 N type epitaxial layer 5 N type buried diffusion layer 6 P type buried diffusion layer 7 P type buried diffusion layer 10 N Type buried diffusion layer

Claims (9)

A semiconductor substrate of one conductivity type;
An opposite conductivity type epitaxial layer formed on the semiconductor substrate;
A first buried diffusion layer of one conductivity type formed on at least the semiconductor substrate;
A second buried diffusion layer of one conductivity type formed over the semiconductor substrate and the epitaxial layer and used as a collector region;
A reverse conductivity type first buried diffusion layer formed across the semiconductor substrate and the epitaxial layer and joining and separating the semiconductor substrate and the one conductivity type second buried diffusion layer;
A second buried diffusion layer of opposite conductivity type that overlaps the formation region of the second buried diffusion layer of one conductivity type and rises from the upper surface of at least the second buried diffusion layer of one conductivity type; ,
A reverse conductivity type diffusion layer formed from the surface of the epitaxial layer and used as a base region;
A first diffusion layer of one conductivity type formed from the surface of the epitaxial layer and used as a collector region;
And a second diffusion layer of one conductivity type formed in the opposite conductivity type diffusion layer and used as an emitter region. An isolation region that partitions the semiconductor substrate and the epitaxial layer into a plurality of element formation regions;
The semiconductor device according to claim 1, wherein the first conductivity type first buried diffusion layer is formed across the plurality of element formation regions. The semiconductor device according to claim 1, wherein a specific resistance value of the semiconductor substrate is 40 to 60 (Ω · cm). 4. The semiconductor device according to claim 3, wherein the first conductivity type buried diffusion layer is diffused from the surface of the semiconductor substrate to 15 to 20 ([mu] m). After preparing a semiconductor substrate of one conductivity type and forming a first buried diffusion layer of opposite conductivity type on the semiconductor substrate, a region wider than the first buried diffusion layer of opposite conductivity type of the semiconductor substrate Forming a first buried diffusion layer of one conductivity type,
Forming a first conductivity type second buried diffusion layer on the semiconductor substrate so that the first conductivity diffusion region of the opposite conductivity type overlaps the formation region;
A step of ion-implanting a reverse conductivity type impurity into the region where the one conductivity type second buried diffusion layer is formed to form a reverse conductivity type second buried diffusion layer;
A reverse conductivity type epitaxial layer is formed on the semiconductor substrate, a first conductivity type diffusion layer used as a collector region from the surface of the epitaxial layer, a reverse conductivity type diffusion layer used as a base region, and an emitter region And a step of forming a second diffusion layer of one conductivity type to be used. 6. The semiconductor according to claim 5, wherein in the step of forming the first buried diffusion layer of one conductivity type, the first buried diffusion layer of one conductivity type is formed on the entire surface of the semiconductor substrate. Device manufacturing method. 7. The method of manufacturing a semiconductor device according to claim 6, wherein the impurity forming the first conductivity type first and second buried diffusion layers is boron. 8. The method of manufacturing a semiconductor device according to claim 7, wherein a thermal oxidation step is performed on the semiconductor substrate before the step of ion-implanting the impurity forming the second buried diffusion layer of the reverse conductivity type. . A heat treatment step in a non-oxidizing atmosphere is not performed between the thermal oxidation step and the step of ion-implanting impurities forming the second conductivity type second buried diffusion layer. Item 9. A method for manufacturing a semiconductor device according to Item 8.