JP2648027B2 - IIL type semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IIL type semiconductor device.

[0002]

2. Description of the Related Art The basic structure of a conventional IIL circuit is shown in FIG.
(A). This conventional example will be described in accordance with the manufacturing process. On a P-type semiconductor substrate 1 having a high-concentration N-type buried layer 2, an impurity concentration (per cubic centimeter) of 10 13 to 10 14 (1E13 to 1E)
Notation 14 An N-type epitaxial layer 3 of the following) is formed, and impurities are selectively introduced from the surface of the N-type epitaxial layer 3 to form a P-type isolation region 5.

Next, a high-concentration N-type collector phosphorus region 11 is formed in the isolated N-type epitaxial layer 3, and a high-concentration P-type injector region 6 and a high-concentration P-type base region 7 are simultaneously formed by a selective diffusion method. I do.

Next, a high-concentration P-type guard ring region 9 having a higher concentration is formed around the high-concentration P-type base region 7, and then N-type impurities are diffused. A high concentration N-type emitter region 10 is formed on the high concentration N-type collector phosphorus region 11 at the same time as forming the type collector region 8.

Finally, an injector electrode 13, a base electrode 14, a collector electrode 15, and an emitter electrode 16 are formed through the opening of the silicon oxide film 2.

FIG. 2 (b) shows an equivalent circuit diagram of this conventional example. Here, the emitter, base, and collector of the PNP transistor Q1 in FIG. 2B are formed by the injector electrode 13, the emitter electrode 16, and the base electrode 14 in the cross-sectional view of FIG. , Emitter electrode 16 form the collector, base and emitter of NPN transistor Q2.

[0007]

The above-mentioned conventional IIL
The circuit has the following disadvantages.

To prevent surface inversion of the high-concentration P-type base region 7, a high-concentration P-type guard ring region 9 is formed.
As a result, the collector concentration of the PNP transistor Q1 is increased, and the efficiency of injection from the collector to the base of the PNP transistor Q1 is increased. However, there is a disadvantage that the size is reduced.

[0009]

According to the present invention, there is provided an IIL-type semiconductor device comprising an N-type first semiconductor device sequentially deposited on a P-type semiconductor substrate.
A high-concentration P-type base region of a lateral PNP transistor selectively formed in the N-type second epitaxial layer of a semiconductor substrate having an epitaxial layer and an N-type second epitaxial layer having a higher concentration than the N-type first epitaxial layer; A high-concentration P-type guard ring region provided around the high-concentration P-type base region and having a higher concentration than the high-concentration P-type base region; And a high-concentration P-type injector region selectively formed in the second type epitaxial layer.
It has an L circuit.

[0010]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1A is a diagram showing an example of I in one embodiment of the present invention.
FIG. 3 is a sectional view of a semiconductor chip showing a basic structure of an IL circuit.

This embodiment will be described in accordance with the manufacturing process. An impurity concentration of 1E13 to 1E per cubic centimeter is provided on a P-type semiconductor substrate 1 having a high-concentration N-type buried layer 2.
Fourteen N-type first epitaxial layers 4-1 are formed, and then the impurity concentration is higher than that of the N-type first epitaxial layers.
1E15-1E16 per cubic centimeter N-type second
The epitaxial layer 4-2 is formed. Next, a P-type isolation region 5 is formed by selectively introducing impurities from the N-type second epitaxial layer 4-2.

Next, a high-concentration N-type collector phosphorus region 1 is formed in the isolated N-type second epitaxial layer 4-2.
Then, a high-concentration P-type injector region 6 and a high-concentration P-type base region 7 are simultaneously formed by a selective diffusion method.

Next, a high-concentration P-type guard ring region 9 having a higher concentration is formed around the high-concentration P-type base region 7,
Thereafter, an N-type impurity is diffused to form a high-concentration N-type collector region 8 on the high-concentration P-type base region 7, and at the same time, a high-concentration N-type collector region 8 is formed.
Emitter region 10 is a high concentration N-type collector phosphorus region 11
Form on top. Finally, an injector electrode 13, a base electrode 14, a collector electrode 15, and an emitter electrode 16 are formed through openings in the silicon oxide film 12.

FIG. 1B shows an equivalent circuit diagram of the IIL circuit of FIG. 1A. The injector electrode 13, the emitter electrode 16, and the base electrode 14 form the emitter, base, and collector of the PNP transistor Q1, and the collector electrode 15, the base electrode 14 and the emitter electrode 16 form the collector, base, and emitter of the NPN transistor Q2.

In this embodiment, by increasing the impurity concentration of the N-type second epitaxial layer, the PNP transistor Q
When the injector electrode 13 is set at the same potential as the emitter electrode 16 as compared with the conventional example, the efficiency of injection from the collector of the PNP transistor Q1 to the base decreases, so that the NPN transistor Q
2, the DC current amplification factor increases.

If the concentration of the N-type first epitaxial layer 4-1 is made the same as that of the conventional N-type epitaxial layer 3, P
The DC current gain of the NP transistor Q1 does not change.

[0018]

As described above, according to the present invention, the N-type first
The DC current gain of the PNP transistor in the IIL circuit is changed by providing an epitaxial layer and a high-concentration N-type second epitaxial layer provided thereon and providing an injector region and a guard ring region in the N-type second epitaxial layer. The DC current gain of the NPN transistor can be increased without the need. Therefore, there is an effect that the performance of the IIL circuit can be improved.

[Brief description of the drawings]

FIG. 1 is a sectional view (a) and an equivalent circuit diagram (b) for use in describing one embodiment of the present invention.

FIGS. 2A and 2B are a cross-sectional view and an equivalent circuit diagram for explaining a conventional example.

[Explanation of symbols]

 Reference Signs List 1 P-type semiconductor substrate 2 High-concentration N-type buried layer 3 N-type epitaxial layer 4-1 N-type first epitaxial layer 4-2 N-type second epitaxial layer 5 P-type isolation region 6 High-concentration P-type injector region 7 High-concentration P-type base region 8 High-concentration N-type collector region 9 High-concentration P-type guard ring region 10 High-concentration N-type emitter region 11 High-concentration N-type collector phosphorus region 12 Silicon oxide film 13 Injector electrode 14 Base electrode 15 Collector electrode 16 Emitter electrode Q1 NPN transistor Q2 PNP transistor Q3 NPN transistor Q4 PNP transistor

Claims (1)

(57) [Claims] 1. An N-type semiconductor device comprising: a N-type semiconductor substrate;
High-concentration P-type lateral PNP transistor selectively formed in the N-type second epitaxial layer of a semiconductor substrate having a first N-type epitaxial layer and an N-type second epitaxial layer having a higher concentration than the N-type first epitaxial layer A base region, and a high-concentration P provided around the high-concentration P-type base region and having a higher concentration than the high-concentration P-type base region.
And an IIL circuit including a high-concentration P-type injector region selectively formed in the N-type second epitaxial layer at a predetermined distance from the high-concentration P-type guard ring region. IIL type semiconductor device.