JPH0629470A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To prevent latch-up due to a parasitic thyristor of a P-N-P-N junction. CONSTITUTION:A Be-doped P-type layer 2 or a B-doped P-type layer 2a in which resistivity becomes 1/2-1/3 of that of a P-type silicon substrate 1 is formed on the substrate 1 by ion implanting. Then, after an N-type buried layer 3 is formed, an N-type epitaxial layer 6 is grown. Thereafter, a P-type diffused layer 7 and an N-type diffused layer 8 are formed, and an element of a semiconductor integrated circuit having an N-P-N transistor, a resistance element and a capacitor is completed. Thus, a resistance value of the substrate (resistance R2) is reduced, and a voltage drop between an emitter and a base of a parasitic N-P-N transistor Q3 is reduced. The transistor Q3 is scarcely operated to prevent generation of latch-up.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit,
In particular, the present invention relates to a semiconductor integrated circuit that prevents latch-up due to a parasitic thyristor action.

[0002]

2. Description of the Related Art A conventional semiconductor integrated circuit will be described with reference to FIG.

First, an N type buried layer 3 is formed on a P type silicon substrate 1, and then an N type epitaxial layer 6 is grown. Next, the P-type channel stopper 4 is used for element separation.
Then, the LOCOS film 5 is formed by selective oxidation. Next, the P-type diffusion layer 7 and the N-type diffusion layer 8 are formed, and the NPN
The element portion of the semiconductor integrated circuit including the transistor, the resistance element, and the capacitor is completed.

[0004]

In the semiconductor integrated circuit of FIG. 2, the P-type semiconductor layer and the N-type semiconductor layer are adjacent to each other and P-type.
A parasitic thyristor action called latch-up may occur at the NPN junction. The P-type diffusion layer 7, the N-type epitaxial layer 6, the P-type silicon substrate 1 (resistor R ₂ ) and the N-type buried layer 3 form a PNPN junction.

Referring to FIG. 3 which is an equivalent circuit diagram of FIG.
This parasitic thyristor action will be described.

The PNP transistor Q ₁ and the PNP transistor Q ₃ form a parasitic thyristor.

When a switch (switch) serving as a trigger is turned on, the collector current of the parasitic PNP transistor Q ₁ is grounded through the P-type silicon substrate 1 (resistor R ₂ ). At this time, a potential difference is generated between both ends of the resistor R ₂ , and the voltage is sufficient to operate the parasitic NPN transistor Q ₃ , and a collector current flows in the N-type diffusion layer (resistor R ₁ ). Next, a potential difference is generated at both ends of the N-type diffusion layer (resistor R ₁ ) and the parasitic PNP is generated.
The voltage is sufficient to operate the transistor Q ₁ . P
A collector current flows through the silicon substrate 1 to generate a potential difference.

Further, the parasitic NPN transistor Q ₃ operates and a collector current flows through the N type diffusion layer (resistor R ₁ ). Due to these repetitions, a large current continues to flow from the power supply V to the ground, and there is a problem that the semiconductor integrated circuit is destroyed.

[0009]

In a semiconductor integrated circuit according to the present invention, a high concentration P type semiconductor layer is formed over the entire main surface of a P type silicon substrate, and the high concentration P type semiconductor layer is formed on the high concentration P type semiconductor layer. An N type epitaxial layer is formed.

[0010]

EXAMPLE FIG. 1A shows a first example of the present invention.
Will be described with reference to.

First, group 2 beryllium (Be) is ion-implanted into the P-type silicon substrate 1 to form a Be-doped P-type layer 2 having a resistivity of 1/2 to 1/3 that of the P-type silicon substrate 1. . Next, after forming the N-type buried layer 3, the N-type epitaxial layer 6 is grown. Next, the P-type diffusion layer 7 and the N-type diffusion layer 8 are formed to complete the element portion of the semiconductor integrated circuit including the NPN transistor, the resistance element, and the capacitor.

Since the P-type silicon substrate 1 is lightly doped with group III boron, it has a high resistance. On the other hand, the Be-doped P-type layer 2 is ion-implanted with beryllium of Group 2 having twice the carrier of boron, so that the resistivity can be lowered.

The Be-doped P-type layer 2 is a P-type silicon substrate 1.
Connected in parallel with each other, the resistance value of the resistor R ₂ becomes small and the voltage drop between the emitter and the base of the parasitic NPN transistor Q ₃ becomes small. The parasitic NPN transistor Q ₃ becomes difficult to operate, and the occurrence of latch-up can be prevented.

Next, a second embodiment of the present invention will be described with reference to FIG.

In this embodiment, a B-doped P-type layer having a resistivity of 1/2 to 1/3 that of the P-type silicon substrate 1 is obtained by ion-implanting group III boron into the P-type silicon substrate 1 at a high concentration. 2a
Was formed.

[0016]

The p-type silicon substrate has a resistivity of 1/2 to
A 1/3 P-type layer is formed. As a result, the resistance between the emitter and the base of the parasitic NPN transistor in the parasitic PNPN junction existing in the semiconductor integrated circuit becomes low, and the voltage drop becomes small. The parasitic NPN transistor becomes difficult to operate, and latch-up can be prevented.

[Brief description of drawings]

FIG. 1A is a sectional view showing a first embodiment of the present invention. (B) is a sectional view showing a second embodiment of the present invention.

FIG. 2 is a sectional view showing a conventional semiconductor integrated circuit.

FIG. 3 is an equivalent circuit diagram showing a parasitic thyristor structure of a semiconductor integrated circuit.

[Explanation of symbols]

1 P-type silicon substrate 2 Be-doped P-type layer 2a B-doped P-type layer 3 N-type buried layer 4 P-type channel stopper 5 LOCOS film 6 N-type epitaxial layer 7 P-type diffusion layer 8 N-type diffusion layer Q ₁ , Q ₂ Parasitic PNP transistor Q ₃ Parasitic NPN transistor R ₁ N-type diffusion layer resistance R ₂ P-type silicon substrate resistance V Power supply SW switch

Claims (2)

[Claims] 1. A semiconductor integrated circuit in which a high-concentration P-type semiconductor layer is formed over the entire main surface of a P-type silicon substrate, and an N-type epitaxial layer is formed on the high-concentration P-type semiconductor layer. 2. The semiconductor integrated circuit according to claim 1, wherein a high-concentration P-type semiconductor layer containing beryllium as an impurity is formed.