JP3249355B2 - Semiconductor integrated circuit and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit having a built-in spark killer diode for protecting an output transistor of a bipolar integrated circuit.

[0002]

2. Description of the Related Art A bipolar integrated circuit for a two-phase or three-phase motor driver uses two NPN transistors 1 and 2 for one phase as shown in FIG. The circuit in which the output terminal 3 is extracted from the connection point of the transistor 2 with the collector of the transistor 2 is often used. When one of the two transistors 1 and 2 is turned on and the other is turned off, a current flows to rotate a motor (not shown) connected to the output terminal 3 in the forward or reverse direction.

In the case of an inductive load such as a motor, a forward / reverse electromotive force is generated as the motor rotates / stops. Conventionally, a Schottky barrier diode 4 is connected between the collector and the emitter of the transistor 2 formed as an IC, and when the output terminal 3 becomes lower than the GND potential or higher than the VCC potential due to the reverse electromotive force, the diode 4 is turned on. ON
By doing so, the electromotive force is released to a fixed potential, and the output transistor 2 and the inside of the IC are protected. In particular, when a large current of several A flows through the diode 4, the diode 4 is configured using individual components.

[0004] By the way, from the user's point of view, it is a natural requirement that the diode 4 be also made into an IC in order to reduce the number of components of the device. When a diode is formed in a bipolar IC, it is common to form a diode by using a PN junction of an NPN transistor (for example, Japanese Patent Application No. 7-14302). Referring to FIG. 7, an NPN transistor 5 has an island region 7 formed by separating an N-type epitaxial layer on a P substrate 6 as a collector, and a P-type base region 8 and an N + emitter region 9 on the surface. It is composed. 10
Is a collector contact region, 11 is an N + buried layer, 1
2 is a P + isolation region. Diode 13 uses the base-collector junction of NPN transistor 5. That is, the island region 7 is used as a cathode, and the region formed by base diffusion is used as the anode region 14. In this case, no emitter is used. As another example of forming a diode, N
There is an example in which the emitter-base junction of the PN transistor 5 is used, and an example in which a PN junction with the island region 7 and the substrate 6 is used. The former has a withstand voltage of only a few volts and is not suitable for the previous application, and the latter has an anode. Fixed to ground potential and the substrate 6
Since a large current flows during the ON operation, it is not desirable from the viewpoint of preventing a parasitic effect.

[0005]

However, even in the configuration of FIG. 7, a current capacity as large as several A can be secured by increasing the junction area between the anode region 14 and the island region 7. The existence of the leakage current i to the substrate 6 cannot be ignored. For example, 1A
, The leakage current i to the substrate 6 increases to several tens of mA, which raises the potential of the substrate 6 and causes other elements to malfunction, or in the worst case, causes latch-up to destroy the IC. That will lead to the situation.

[0006]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional disadvantages, and utilizes a vertical PNP transistor structure to constitute a diode.
The collector buried layer, the collector lead-out region, and the emitter region of the vertical PNP transistor are used as an anode, the base of the vertical PNP transistor is used as a cathode, and the periphery of the collector buried layer and the collector lead-out region is divided into an N + buried layer and an N + lead-out region. Surround the N + buried layer and the N + lead-out region with the same potential as the anode or a potential higher than the anode, and separate the anode and the substrate with an N + type high concentration layer to greatly reduce the leakage current from the anode to the substrate. Is reduced.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below in detail. FIG. 1 is a sectional view showing a bipolar IC in which an NPN transistor 22, a vertical PNP transistor 23, and a diode 24 are integrated in first, second, and third island regions 21a, 23b, and 23c, respectively, according to the present invention. .

In FIG. 1, reference numeral 25 denotes a P-type silicon semiconductor substrate; 26, an N + type buried layer; 27a and 27b, P + isolation regions; 28, a P-type base region of the NPN transistor 22; An N + type emitter region, 30 is an N + type collector low resistance region of the NPN transistor 22, 31 is a P + collector buried layer, 32 is a P + collector lead region, 33 is an N type well region, 34 is a P + type emitter region, 35 is an N + base contact region, and 36 is an N + of a vertical PNP transistor.
Lead-out area, 37 is a P + anode buried layer, 38 is P +
Anode lead-out area, 39 is a P + anode area, 40 is N
+ Cathode contact region, 41 is N of diode 24
Reference numeral 42 denotes an oxide film, and reference numeral 43 denotes an aluminum electrode that contacts each diffusion region via a contact hole provided in the oxide film 42.

First, second, and third island regions 21a, 21
b and 21c are formed by junction-separating the epitaxial layer formed on the substrate 25 at the P + isolation regions 28a and 29b. The collector of the NPN transistor 22
The low-resistance region 30 is located N N away from the surface of the first island region 21a.
It reaches the + buried layer 26 and has the function of reducing the collector series resistance of the NPN transistor 22. Therefore, this transistor is of a high withstand voltage and a large current type, and is suitable for the use in FIG.

The vertical PNP transistor 23 has a substrate 25
A P + collector buried layer 31 provided so as to overlap the N + buried layer 26 from the surface serves as a collector, and is based on an N-type region surrounded by a collector lead-out region 32 reaching the collector buried layer 26. In this example, an N-well region 33 is provided to increase hfe by electric field acceleration, increase ft by reducing the base width, and increase the breakdown voltage (VCEO). An N + lead-out region 36 is provided outside the collector lead-out region 32 to surround the N + lead-out region 36, and the power supply potential VCC or the potential of the emitter region 34 is applied by an electrode (not shown). This means that the collector lead-out region 32 is an emitter, the island region 21b is a base,
This is for suppressing the occurrence of a parasitic PNP transistor having the isolation regions 27a and 27b as collectors.
The P-transistor can be a high-power PNP transistor capable of forming a complementary pair with the high-power NPN transistor.

The structure of the diode 24 is basically a vertical P
This is the same as the NP transistor 23. That is, the P + anode buried layer 37 provided so as to overlap the buried layer 26 and the P + reaching the anode buried layer 37 from the surface of the island region 21c.
+ N-type layer 44 in the island region surrounded by the anode lead-out region 38
The N-type layer 44 in the island region surrounded by the anode lead-out region 39 is defined as the anode region 39 formed on the surface of
Is used as a cathode to form a PN junction diode. However, the anode region 39 and the anode lead-out region 38 are connected to the electrode 4
3a causes a short circuit. This is a diode formed by short-circuiting the emitter and collector between PNP transistors. Further, the N well region 33 is not formed in the surrounded N type layer 44. This is to prevent the reverse leakage current of the PN junction from increasing due to the high concentration junction.

As in the case of the vertical PNP transistor 23, N + reaching the buried layer 26 from the surface of the island region 21c so as to surround the anode buried layer 37 and the anode lead-out region 38.
A mold deriving region 41 is provided, and the same potential as the anode region 38 or a higher potential than the anode region 38 is applied by the electrode 43. Referring to FIG. 2, an enlarged sectional view of the diode portion of FIG. 1 is shown in FIG. 2A, and an enlarged sectional view of the diode portion of FIG. 7 is shown in FIG. In FIG. 2B, the leakage current of the diode ON current i to the substrate depends on the current amplification factor of the parasitic PNP transistor 50 having the anode region 14 as the emitter, the island region 7 as the base, and the isolation region as the collector. Current i flows through the parasitic PNP
Since the base-emitter junction of the transistor 50 is ON, the parasitic PNP transistor is always O
The state becomes N, and it is impossible to stop the leakage current to the substrate 25.

On the other hand, in the configuration of FIG. 2A, the N-type layer 44 and the anode lead-out region 38
ON current i flows from the substrate 2 to the N-type layer 44, and the substrate 2
The leakage current to 5 makes the anode buried layer 37 the emitter. It depends on the operation of the parasitic PNP transistor 50 using the buried layer 26 as a base and the substrate 25 as a collector. In the present invention, the same potential as or higher than that of the anode buried layer 37 is given to the buried layer 26 via the lead-out region 41, so that the base
The emitter junction does not turn on. Therefore, the parasitic PNP
Without turning on the transistor 50, leakage current to the substrate 25 can be prevented.

FIG. 3 is a sectional view showing a method of manufacturing the above structure in the order of steps. Hereinafter, the manufacturing method will be described in detail with reference to the drawings. First, referring to FIG. 3A, a P-type single-crystal silicon semiconductor substrate 256 serving as a substrate is prepared. A surface of the substrate 25 is thermally oxidized to form an oxide film, a resist is applied on the oxide film, exposed and developed, and the oxide film is etched using the resist pattern as a mask to form an oxide film pattern. After removing the resist mask, antimony or arsenic is initially diffused on the surface of the substrate 25 using the oxide film pattern as a mask. Similarly, boron is initially introduced using an oxide film mask or a resist mask to simultaneously form a P + collector buried layer 31, a P + anode buried layer 37, and an isolation region 27a.

Referring to FIG. 3B, after removing the oxide film to expose the surface of substrate 25, an epitaxial layer 51 having a thickness of 8 to 16 .mu.m is formed on the entire surface by vapor phase epitaxy.
Initially selectively diffuses phosphorus into the surface of the epitaxial layer 51 to form an N + collector lead-out region and a vertical PNP transistor 23.
And the N + deriving region 41 of the diode 24 are formed at the same time.

Subsequently, an N well region of the vertical PNP transistor 23 is formed by ion implantation. Referring to FIG. 4A, N well region 3 of vertical PNP transistor 23 is formed.
3 is formed by ion implantation, and about 110
By applying a heat treatment at 0 ° C. for 3 to 4 hours, the N-type well region 33 and others are thermally diffused.

Referring to FIG. 4B, an epitaxial layer 50P + isolation region 27b is formed and an epitaxial layer 5P is formed.
0 forms a plurality of island regions 21a, 21b, 21c.
Referring to FIG. 5A, P-type base region 28 of NPN transistor 24 is formed by diffusing boron from the surface of second epitaxial layer 38, and boron is further ion-implanted to form P + -type anode region 39. , P + emitter region 34, and further diffuse phosphorus or arsenic to form cathode contact region 40, base contact region 35, and emitter region 29.

Thereafter, an electrode wiring (not shown) made of an aluminum material is formed to form a circuit network of the integrated circuit.
Thus, by sharing the process of the vertical PNP transistor 23, the diode 24 can be efficiently incorporated.

[0019]

As described above, according to the present invention, there is an advantage that the diode element 24 in which the leakage current to the substrate 25 is greatly reduced can be integrated. By reducing the leakage current, malfunction and latch-up in the integrated circuit can be prevented. Therefore, the spark killer diode of the output transistor can also be integrated, which can contribute to the miniaturization and high density of the electronic device. Further, since the structure of the vertical PNP transistor 23 can be used, there is an advantage that integration can be performed without complicating the process.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view for explaining the present invention.

FIG. 2 is a cross-sectional view for explaining the present invention.

FIG. 3 is a cross-sectional view illustrating a manufacturing method of the present invention.

FIG. 4 is a cross-sectional view illustrating a manufacturing method of the present invention.

FIG. 5 is a cross-sectional view illustrating the manufacturing method of the present invention.

FIG. 6 is a circuit diagram illustrating a conventional example.

FIG. 7 is a cross-sectional view illustrating a conventional example.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ identification code FI H01L 29/861 (58) Investigated field (Int.Cl. ⁷ , DB name) H01L 21/822 H01L 21/8222-21/8228 H01L 21/8232 H01L 27/06 H01L 27/08 H01L 27/082

Claims (5)

(57) [Claims] 1. A semiconductor substrate of one conductivity type, a plurality of buried layers of opposite conductivity type formed on the surface of the semiconductor substrate, and an epitaxial layer of opposite conductivity type formed on the substrate, At least first, second, and third island regions formed by separating each of them so as to surround each of them; a base region of one conductivity type formed in the first island region;
An emitter region of the opposite conductivity type formed on the surface of the base region of the one conductivity type; a collector low resistance region reaching the buried layer of the opposite conductivity type from the surface of the first island region; A collector buried layer of one conductivity type, which is buried in contact with the buried layer of the opposite conductivity type in a region; a collector lead-out region of one conductivity type reaching the collector buried layer from a surface of the second island region; A base region of the opposite conductivity type surrounded by a collector lead-out region; an emitter region of one conductivity type formed on the surface of the base region; and a buried layer in contact with the buried layer of the opposite conductivity type in the third island region. An anode buried layer of one conductivity type, an anode lead-out region of one conductivity type reaching the anode buried layer from the surface of the third island region, and a reverse conductivity surrounded by the anode lead-out region An anode region of one conductivity type, and a cathode contact region of the opposite conductivity type, formed on the surface of the region, and a reverse conductivity type that reaches the opposite conductivity type buried layer from the surface of the epitaxial layer and surrounds the anode buried layer. And a means for short-circuiting the anode region and the anode lead region; and a means for applying the same potential as the anode region or a potential higher than the potential of the anode region to the lead region of the opposite conductivity type. A semiconductor integrated circuit. 2. The method according to claim 1, wherein said cathode region is connected to said collector low resistance.
2. The semiconductor integrated circuit according to claim 1, wherein a region and said anode region are respectively connected to said reverse-type emitter region, and said collector lead-out region is connected to an output terminal. 3. A step of forming a plurality of buried layers of the opposite conductivity type on the surface of the semiconductor substrate of the one conductivity type; and forming a buried layer of the one conductivity type and an anode buried layer overlapping the buried layer. Forming a reverse conductivity type epitaxial layer on the substrate; separating the epitaxial layer to form at least first, second, and third island regions; Forming a reverse conductivity type collector low resistance region reaching the buried layer from the surface thereof, and simultaneously forming a reverse conductivity type lead region reaching the buried layer from the surface on the third island region; Forming a collector leading region of one conductivity type from the surface to the collector buried layer on the surface of the second island region, and simultaneously forming the anode buried layer from the surface on the third island region from the surface; Forming an anode lead-out region to reach; forming a base region of one conductivity type and an emitter region of the opposite conductivity type in the first island region to form a transistor having the first island region as a collector; Forming an emitter region of one conductivity type in a region of the second island region surrounded by the collector lead-out region, and forming a transistor based on the region surrounded by the collector lead-out region; Forming an anode region of one conductivity type in a region of the opposite conductivity type surrounded by the anode lead-out region of the third island region, and forming a diode using the surrounded region as a cathode. Of manufacturing a semiconductor integrated circuit. 4. The method according to claim 1, wherein a lower portion of the isolation region is formed simultaneously with the collector buried layer , an upper portion of the isolation region is formed simultaneously with the formation of the collector lead-out region, and the lower portion and the upper portion are connected. 4. The method according to claim 3, wherein the epitaxial layer is separated. 5. The method according to claim 3, wherein the formation of the emitter region of the second island region and the formation of the anode region of the third island region are performed at the same time.