JPS61242061A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS61242061A
JPS61242061A JP60083839A JP8383985A JPS61242061A JP S61242061 A JPS61242061 A JP S61242061A JP 60083839 A JP60083839 A JP 60083839A JP 8383985 A JP8383985 A JP 8383985A JP S61242061 A JPS61242061 A JP S61242061A
Authority
JP
Japan
Prior art keywords
base
collector
pnp transistor
emitter
lateral pnp
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP60083839A
Other languages
Japanese (ja)
Other versions
JPH0715944B2 (en
Inventor
Kenji Manabe
健次 真鍋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP60083839A priority Critical patent/JPH0715944B2/en
Publication of JPS61242061A publication Critical patent/JPS61242061A/en
Publication of JPH0715944B2 publication Critical patent/JPH0715944B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0214Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
    • H01L27/0229Particular design considerations for integrated circuits for internal polarisation, e.g. I2L of bipolar structures
    • H01L27/0233Integrated injection logic structures [I2L]

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Bipolar Integrated Circuits (AREA)

Abstract

PURPOSE:To conduct stable inverter operation at low power consumption by making concentration on the emitter side of a base region in a lateral pnp transistor lower than that on the collector side. CONSTITUTION:A low-concentration n-type region 11 is formed on the emitter side of a base region 10 in a lateral pnp transistor. According to the structure, the forward saturation currents of a base-emitter junction in the lateral pnp transistor are made larger than the saturation currents of a base-collector junction. Accordingly, forward injection currents can be increased by several times as much as reverse injection currents when pnp collector potential is equalized.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は半導体集積回路装置、詳しくは集積注入論理回
路(Integrated Injection Lo
gic。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to semiconductor integrated circuit devices, specifically integrated injection logic circuits.
gic.

以下ILと略す)の改良に関するものである。This paper relates to the improvement of IL (hereinafter abbreviated as IL).

従来の技術    − 従来、MLはラテラルPNP トランジスタと縦方向の
逆動作NPNトランジスタを組み合わせて一体とした論
理回路で、第2図に示すようなデバイス断面構造をとる
ことが多かった。同図において、1はP型基板、2はN
型埋込層、3はN型エピタキシャル層、4は?型拡散層
、5はIL素子のインジェクタと呼ばれるラテラルPN
P トランジスタのエミッタ(P型)、6はインジェク
タPNPトランジスタのコレクタおよびNPNトランジ
スタのベースとなるり型拡散層、7−1.7−2は?拡
散層、8は二酸化シリコンなどの絶縁膜、9はアルミニ
ウム電極である。このよりなILは通常のバイポーラI
 C’の製造プロセスで製造することかで+ き、P拡散層6,6をラテラルPNP トランジスタの
エミッタとコレクタとして動作させ、そのベースはN型
エピタキシャル層3とし、他方、逆動作NPNトランジ
スタは a+埋込層2およびN型エピタキシャル層3を
エミッタ、P拡散層6をベース、N〜散層7−1.7−
2をそのコレクタとしている。
Prior Art - Conventionally, an ML is a logic circuit that is integrated by combining a lateral PNP transistor and a vertical reverse-action NPN transistor, and has often had a device cross-sectional structure as shown in FIG. In the same figure, 1 is a P-type substrate, 2 is an N-type substrate
Type buried layer, 3 is N type epitaxial layer, 4 is ? type diffusion layer, 5 is a lateral PN called the injector of the IL element
Emitter of P transistor (P type), 6 is a rectangular diffusion layer that becomes the collector of the injector PNP transistor and the base of the NPN transistor, 7-1.7-2? A diffusion layer, 8 an insulating film such as silicon dioxide, and 9 an aluminum electrode. This twisted IL is a normal bipolar I
By manufacturing with the manufacturing process of C', the P diffusion layers 6, 6 are operated as the emitter and collector of a lateral PNP transistor, the base of which is the N type epitaxial layer 3, while the reverse operation NPN transistor is a+ Buried layer 2 and N-type epitaxial layer 3 as emitter, P diffusion layer 6 as base, N ~ diffused layer 7-1.7-
2 as its collector.

このような構成にすることにより、集積密度を向上させ
、また、ゲート当りの消費電力も著しく低減させうろこ
とが知られている。
It is known that such a configuration can improve the integration density and significantly reduce power consumption per gate.

発明が解決しようとする問題点 しかしながら従来の構造では、・ラテラルPNPトラン
ジスタのコレクタに供給された正孔がNPNトランジス
タのペース電流となるが、はとんどの正孔は、ラテラル
PNP トランジスタのコレクタ6から逆注入されてエ
ミッタ5に戻ってしまい、NPNトランジスタのコレク
タ7−1.7−2を駆動するベース電流が充分にとれな
いという欠点がある。
Problems to be Solved by the Invention However, in the conventional structure, the holes supplied to the collector of the lateral PNP transistor become the pace current of the NPN transistor; The disadvantage is that the base current is injected back from the source and returns to the emitter 5, making it impossible to obtain a sufficient base current to drive the collector 7-1, 7-2 of the NPN transistor.

本発明は、前述の従来構造の欠点、すなわちラテラルP
NPトランジスタの逆注入を減少せしめる構造に係るも
のである。
The present invention solves the drawbacks of the conventional structure mentioned above, namely, the lateral P
The present invention relates to a structure that reduces back injection of an NP transistor.

問題点を解決するための手段 本発明の装置は、ラテラルPIP トランジスタのペー
ス領域がコレクタ側よりもエミッタ側で低濃度になった
構造とするものである。
Means for Solving the Problems The device of the present invention has a structure in which the space region of the lateral PIP transistor has a lower concentration on the emitter side than on the collector side.

作用 この構造によると、ラテラルPNP )う/ジスタのペ
ース・エミッタ接合の順方向飽和電流が、ペース・コレ
クタ接合飽和電流よりも大きくなり、このため、NPN
ベース電位、すなわちPNPコレクタ電位を同じとした
時、逆方向注入電流に対し順方向注入電流が増加でき、
正味のNPNトランジスタのベース電流を数倍に増加さ
せる。
Effect: According to this structure, the forward saturation current of the pace-emitter junction of the lateral PNP transistor becomes larger than the pace-collector junction saturation current, so that the NPN
When the base potential, that is, the PNP collector potential is the same, the forward injection current can increase relative to the reverse injection current,
Increases the net NPN transistor base current several times.

実施例 第1図に本発明の実施例を断面図で示す。1はP型基板
、2は「型埋込層、3はN型エピタキシャル層、4は「
型拡散層、6はI2L素子のインジェクタ、6はインジ
ェクタPNP トランジスタのコレクタおよびNPNト
ランジスタのペースとなル?拡散rWt、7−1 、7
−2ハN”拡散層、8は二酸化シリコンなどの絶縁膜、
9はアルミニウム電極である。
Embodiment FIG. 1 shows a cross-sectional view of an embodiment of the present invention. 1 is a P-type substrate, 2 is a "type buried layer, 3 is an N-type epitaxial layer, and 4 is a"
type diffusion layer, 6 is the injector of the I2L element, 6 is the injector PNP transistor collector and the NPN transistor pace. Diffusion rWt, 7-1, 7
-2N” diffusion layer, 8 is an insulating film such as silicon dioxide,
9 is an aluminum electrode.

この実施例では、ラテラルPNPトランジスタのベース
領域10のエミッタ側に低濃度N型領域11を設けた構
造である。前記低濃度N型領域111は、ボロンをビー
ズ量1x1o/d程度でイオン注入後、拡散してコンペ
ンセートして形成することができる。あるいは低濃度N
型領域11に対応する表面を除く周辺のベース領域10
にリンあるいはヒ素をイオン注入し、拡散して形成する
こともできる。
This embodiment has a structure in which a lightly doped N-type region 11 is provided on the emitter side of a base region 10 of a lateral PNP transistor. The low concentration N-type region 111 can be formed by ion-implanting boron in a bead amount of about 1×1 o/d and then diffusing and compensating. Or low concentration N
Peripheral base region 10 excluding the surface corresponding to mold region 11
It can also be formed by ion-implanting phosphorus or arsenic and diffusing it.

発明の効果 本発明によるI2L構造にすることによって、ラテラル
PNPトランジスタの逆方向電流を著しく低減でき、逆
動作NPN )ジンジスタの実効ペース電流を増加させ
ることができる。これにより、従来構造のI2Lよりも
、より低消費電力で安定なインバータ動作をさせること
ができるILが実現され、本発明の装置は、工業上大き
な利益をもたらすものである。
Effects of the Invention By adopting the I2L structure according to the present invention, the reverse current of the lateral PNP transistor can be significantly reduced, and the effective pace current of the reverse-acting NPN transistor can be increased. As a result, an IL that can operate an inverter more stably with lower power consumption than an I2L having a conventional structure is realized, and the device of the present invention brings great industrial benefits.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明によるI2Lの実施例断面図、第2図は
従来例断面口である。 1・・・・・・P型基板、2・・・・・・N 埋込層、
3・・・・・・N型エピタキシャル層、5・・・・・・
ラテラルPNP トランジスタのエミッタ、6・・・・
・・ラテラルPNP )う/ジスタのコレクタおよびN
PNトランジスタのペース、10・・・・・・ラテラル
PNP トランジスタのベース領域、11・・・・・・
低濃度N型ベース領域。 宵 I  5i              4−PI
基砥萬 2!!r
FIG. 1 is a sectional view of an embodiment of I2L according to the present invention, and FIG. 2 is a sectional view of a conventional example. 1...P type substrate, 2...N buried layer,
3...N-type epitaxial layer, 5...
Lateral PNP transistor emitter, 6...
・・Lateral PNP) U/DIST collector and N
Pace of PN transistor, 10... Lateral PNP transistor base region, 11...
Low concentration N type base region. Evening I 5i 4-PI
Motoman 2! ! r

Claims (1)

【特許請求の範囲】[Claims]  ラテラルPNPトランジスタのベースとコレクタをそ
れぞれ逆動作NPNトランジスタのエミッタとベースに
対応させ、前記逆動作NPNトランジスタのベース領域
内に複数のコレクタをそなえ、前記ラテラルPNPトラ
ンジスタのベース領域を、同トランジスタのコレクタ側
よりもエミッタ側で低濃度になしたことを特徴とする半
導体装置。
A base and a collector of the lateral PNP transistor correspond to an emitter and a base of a reverse operation NPN transistor, respectively, a plurality of collectors are provided in the base region of the reverse operation NPN transistor, and a base region of the lateral PNP transistor is connected to the collector of the transistor. A semiconductor device characterized by having a lower concentration on the emitter side than on the emitter side.
JP60083839A 1985-04-19 1985-04-19 Semiconductor device Expired - Lifetime JPH0715944B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60083839A JPH0715944B2 (en) 1985-04-19 1985-04-19 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60083839A JPH0715944B2 (en) 1985-04-19 1985-04-19 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS61242061A true JPS61242061A (en) 1986-10-28
JPH0715944B2 JPH0715944B2 (en) 1995-02-22

Family

ID=13813869

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60083839A Expired - Lifetime JPH0715944B2 (en) 1985-04-19 1985-04-19 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH0715944B2 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57128954A (en) * 1981-02-04 1982-08-10 Hitachi Ltd Iil semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57128954A (en) * 1981-02-04 1982-08-10 Hitachi Ltd Iil semiconductor device

Also Published As

Publication number Publication date
JPH0715944B2 (en) 1995-02-22

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