JP2771311B2 - Semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an NPN transistor formed on a P-type semiconductor substrate, and more particularly to a semiconductor including an NPN transistor having a short accumulation time and a good pulse response characteristic at the time of saturation. Related to the device.

[Conventional technology]

A conventional NPN transistor formed on a P-type semiconductor substrate has the structure shown in the perspective sectional view of FIG. That is, on the P-type semiconductor substrate 1 having the N ⁺ -type buried layer 2,
An N-type epitaxial layer 3 serving as a collector is formed, and then an N ⁺ -type high conduction path layer 7 is formed by selective diffusion of impurities from the surface of the N-type epitaxial layer 3. Next, a P-type isolation layer 4 is formed in a frame shape by selective diffusion of impurities from the surface of the N-type epitaxial layer 3. Next, a P ⁺ -type base layer 5 is formed in the N-type epitaxial layer 3 surrounded by the P-type isolation layer 4 and the substrate 1 by selective diffusion of impurities. Finally, an N ⁺ -type emitter layer 6 is formed in the P ⁺ -type base layer 5.
Simultaneously formed by selective diffusion of N-type impurity N ⁺ -type collector contact layer 8 on the N ⁺ highly conductive path layer 7 and.

[Problems to be solved by the invention]

When the above-described conventional NPN transistor (Tr) formed on the P-type semiconductor substrate is saturated, the P ⁺ -type base layer 5 is used as the emitter, the N-type epitaxial layer 3 is used as the base, and the P-type isolation layer 4 and the P-type semiconductor substrate are used. Parasitic PN with 1 as collector
The P transistor (Tr) operates, and part of the base current flowing into the base electrode of the NPNTr flows through the N-type epitaxial layer 3 which is the collector layer of the NPNTr to the P-type semiconductor substrate 1.

By the way, during base current when NPNTr is saturated, parasitic PNP Tr
Accordingly, the ratio of the current flowing through the N-type epitaxial layer 3 to the P-type semiconductor substrate 1 increases in proportion to the current amplification factor of the parasitic PNP Tr. However, the conventional P shown in FIG.
In the NPNTr formed on the semiconductor substrate, the P ⁺ base layer 5
Between the P-type isolation layer 4 and the P-type semiconductor substrate 1, the N ⁺ buried layer 2 and the N ⁺ high-conductivity layer 7 with high concentration
There is a disadvantage that the current amplification factor of the parasitic PNP Tr becomes small, and the accumulation time of N PNT Tr at the time of saturation becomes long.

[Means for solving the problem]

In order to solve the above problem, in the semiconductor device of the present invention, between the N ⁺ high conduction path layer and the P ⁺ base layer in the N type epitaxial layer surrounded by the P type substrate and the isolation layer, By providing a parasitic PNP Tr collector layer connected to the P-type substrate 1 just reaching the upper surface of the N ⁺ buried layer on the bottom surface, the current amplification factor of the parasitic PNP Tr is increased, and thus the base current of the original N PNT Tr is reduced. The number of components flowing to the collector layer of the NPNTr is increased, the number of electron carriers injected into the base of the NPNTr is reduced, the amount of accumulation is reduced, and the accumulation time is shortened.

〔Example〕

 Next, the present invention will be described with reference to examples.

FIG. 1 is a perspective sectional view of one embodiment of the present invention. First
In Figure, P ⁺ type upper surface side of the semiconductor substrate 1 N ⁺ -type buried layer 2 is formed on the upper surface of the substrate 1 further comprising an N ⁺ buried layer 2, impurity concentration 10 ¹⁵ ~10 ¹⁶ cm ^{- 3} N-type epitaxial layers 3 (NPNTr collector layers) are stacked, and a P-type isolation layer 4 reaching the substrate 1 from the upper surface of the N-type epitaxial layer 3 is formed in a frame shape surrounding the N ⁺ buried layer 2 inside. Being
The N-type epitaxial layer 3 surrounded by the P-type isolation layer 4 and the P ⁺ substrate 1 at the bottom constitutes one unit element region. The upper surface side biased to the right side of the element region by selective diffusion of P-type impurities are P ⁺ -type base layer 5 is formed, also, N ⁺ high reach from the upper surface that is biased to the left side of the device region in N ⁺ buried layer 2 A conductive path layer 7 is formed. Next, an N ⁺ -type emitter layer 6 is formed in the P ⁺ base layer 5, and an N ⁺ -type collector contact layer 8 is formed on the upper surface of the N ⁺ high conductive path layer 7 to selectively diffuse N-type impurities. At the same time. The above is the same as that of the conventional NPN transistor of FIG. 2, particularly in the present invention, simultaneously with the isolation formation, in an intermediate portion between the P ⁺ base layer 5 and the N ⁺ highly conductive path layer 7, N N ⁺ from the top of the epitaxial layer 3
The P ⁺ -type parasitic PNP Tr collector layer 9 is formed at such a depth as to reach the buried layer 2. The parasitic PNP Tr collector layer 9 is connected to the same potential as the substrate 1, and the presence of this collector layer 9 increases the current amplification factor of the parasitic PNP Tr, resulting in a shorter accumulation time of the original NPN Tr and a reduction in pulse response characteristics. Be improved.

In the above embodiment, the parasitic PNP Tr collector layer is provided only on one side of the NPNTr base layer. However, the parasitic PNP Tr collector layer can be provided so as to surround the entire circumference of the P ⁺ base layer.

〔The invention's effect〕

As described above, according to the present invention, the P-type parasitic PN having the same potential as the P-type semiconductor substrate is provided between the P ⁺ -type base layer and the N ⁺ high conduction path layer.
By providing the PTr collector layer, the current amplification factor of the parasitic PNP Tr can be increased, and the accumulation time at the time of saturation of the NPNTr can be shortened.

[Brief description of the drawings]

FIG. 1 is a perspective sectional view of one embodiment of the present invention, and FIG. 2 is a perspective sectional view of a conventional semiconductor device. 1 ... P ⁺ semiconductor substrate, 2 ... N ⁺ buried layer, 3 ... N-type epitaxial layer (NPNTr collector layer), 4 ... P-type isolation layer, 5 ... P ⁺ base layer, 6 ... N ⁺ emitter layer, 7 ... N ⁺ high conduction path layer, 8 ... collector contact layer, 9 ... parasitic PNP Tr collector layer.

Claims (1)

(57) [Claims] 1. A top-side N-type layer is stacked in N ⁺ buried layer is formed a P-type semiconductor substrate in the P comprise from the top surface of the N-type layer of the N ⁺ buried layer on the inside A P-type isolation layer reaching the mold substrate; a P ⁺ base layer in an element region surrounded by the substrate and the isolation layer; an N ⁺ emitter layer in the P ⁺ base layer; N ⁺ collector contact layer is formed on the N-type layer upper surface of the element region, the NPN-type transistor and the N ⁺ highly conductive path layer and the N ⁺ collector contact layer connecting the said N ⁺ buried layer is formed In the semiconductor device including the P ⁺ base layer and the N ⁺ high conduction path layer, the P ⁺ base layer having a depth from the upper surface to the upper surface of the N ⁺ buried layer is provided on the N type layer. Emitter, N
A semiconductor device, comprising: a P-type parasitic PNP transistor / collector layer having the same potential as the P-type substrate, wherein the P-type substrate has a P-type substrate as a base and a P-type substrate as a collector.