JPS6344306B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to an integrated semiconductor device in which an insulating isolation diffusion region and a collector region are short-circuited, an emitter is surrounded by the collector region, and a base electrode is outside the collector. The present invention relates to a semiconductor device including a circuit type transistor.

Conventionally, in a standard bipolar integrated circuit, an n ⁺ type buried diffusion region is formed in an npn transistor formation region of a p type semiconductor substrate, an n type epitaxial layer is formed, and a
P ⁺ type isolation diffusion regions are formed, and P + type is formed in each isolation region.
npn type base diffusion and n ⁺ type emitter diffusion
It constitutes a type of transistor. In this process, in order to form a pnp transistor at the same time, an emitter is formed by p-type diffusion in parallel with the p-type diffusion when forming the base of the npn transistor, so that the epitaxial layer is used as a base region, and the p-type substrate is This results in a vertical type pnp transistor whose collector is . The vertical type npn transistor cannot achieve a sufficiently large current gain due to variations in the thickness of the epitaxial layer and the conditions for forming the npn type transistor, and the lateral type transistor cannot achieve a sufficiently large current gain due to the breakdown voltage and the precision of forming the diffusion region. The effective length between the collectors can only be around 10μ, making it impossible to achieve a sufficiently large current gain. However, if the collector region is short-circuited with the isolation diffusion region and the semiconductor substrate, the parasitic PNP transistor is actively utilized without forming the N ⁺ type buried diffusion region directly under the lateral type PNP transistor formation region. This allows the PNP transistor to operate in both the lateral and vertical directions, and in this case, the current gain is much larger than when the above two types of PNP transistors operate alone, for example, the grounded-emitter current gain is 100. You will be able to get more than a certain amount.

However, in a PNP transistor with such a structure, the emitter region is surrounded by the collector region so that a large current gain can be obtained, and the emitter region and the collector region of a lateral type PNP transistor are narrow to increase the current gain. Therefore, the base electrode must be taken out outside the collector region. For that reason,
When the base-collector voltage of a pnp transistor increases, a parasitic junction field effect transistor that uses the collector and semiconductor substrate as a gate and the epitaxial layer as a channel will pinch off.
Because of this, there was a drawback that the PNP transistor did not work. This will be explained in more detail with reference to the drawings.

FIGS. 1a and 1b are a plan view and a sectional view taken along the line AA of an integrated circuit type pnp transistor, which is included in a conventional semiconductor device and whose collector region is short-circuited to an isolation region.

In FIGS. 1a and 1b, an n-type epitaxial layer 3' is laminated on the upper surface of a p-type semiconductor substrate 1,
In this epitaxial layer 3', a P-type isolation region 2 is formed.
is formed into a frame shape, and an epitaxial base region 3 is formed inside the frame. Then, a P-type emitter region 5 is selectively formed in the epitaxial base region 3, and further, this emitter region 5
A P-type collector region 4 is formed which surrounds the periphery of the P-type collector region 4, partially overlaps the isolation region 2, and is short-circuited to the isolation region 2. In the epitaxial base region 3 outside the collector region 4, an n-type base electrode extraction region 6 is formed at a position symmetrical to the emitter region 5 with the collector region 4 in between. and a collector electrode 4a on the upper surface of the base electrode extraction area 6.
An emitter electrode 5a and a base electrode 6a are provided.

FIGS. 2a and 2b are operation explanatory diagrams in which the integrated circuit pnp transistor of FIG. 1 and a power supply circuit for operating this transistor are connected. In the same figure a, a collector power supply is connected between the collector electrode 4a and the base electrode 6a through a load resistor R _L.
V _CB causes a depletion layer 7 based on the p-n junction between the p-type substrate 1 , the isolation region 2 and the epitaxial base region 3 , and a p- between the collector region 5 and the epitaxial base region 3 . A depletion layer 8 based on the n-junction is generated. As is clear from the equivalent circuit shown in FIG. 2c, this situation is explained by the parasitic junction field effect transistor 11 whose gate is the substrate 1 and the collector electrode 4a, and whose channel is the current path from the emitter electrode 5a to the base electrode 6a. This is the same as gate _control by
and 8 further spread, and as seen in Figure 2b, they finally merge above the pinch-off voltage,
The gap between the emitter electrode 5a and the base electrode 6a is cut off by the depletion layers 7 and 8, and no current flows.
The transistor becomes inoperable.

In this way, in conventional integrated circuit type transistors in which the collector region is short-circuited with the isolation region and the current gain is increased by operating in both the lateral and vertical directions, when the voltage between the collector and base increases, the collector region The disadvantage was that the base current no longer flows due to pinch-off of the parasitic junction field effect transistor in which the substrate does not function as a gate, making it inoperable.

An object of the present invention is to prevent the inoperability caused by pinch-off of a parasitic junction field effect transistor due to a short circuit between the collector region, the isolation region, and the semiconductor substrate from occurring with normal collector-base voltage. An object of the present invention is to provide a semiconductor device including an integrated circuit type transistor.

A semiconductor device of the present invention includes a substrate of one conductivity type, an isolation region of one conductivity type formed in a frame shape in an epitaxial layer of an opposite conductivity type laminated on the upper surface of this substrate,
An epitaxial base region surrounded by this isolation region, a base electrode extraction region of an opposite conductivity type and an emitter region of one conductivity type selectively formed at a predetermined interval in this epitaxial base region, and a part of the epitaxial base region. is short-circuited to the separation region and is selected as the epitaxial base region by surrounding the periphery of the emitter region while having a cut gap in the width direction at a position sandwiched between the base electrode extraction region and the emitter region. an integrated circuit type transistor including a collector region of one conductivity type formed in a conventional manner, and a base electrode, a collector electrode, and an emitter electrode provided on the upper surface of the base electrode extraction region, the collector region, and the emitter region, respectively. have

Next, the present invention will be explained by examples.

FIGS. 3a, 3b and 3c are a plan view of an embodiment of the present invention, and a sectional view taken along line AA and line BB in FIG. 3a.

In FIGS. 3a and 3b, the integrated circuit type transistor included in the semiconductor device of the present invention has an n-type epitaxial layer laminated on the upper surface of a P-type semiconductor substrate 1, and a frame-shaped P-type epitaxial layer on this epitaxial layer. An isolation region 2 is formed in an n-type epitaxial base region 3 surrounded by the isolation region 2, and a p-type collector region 14 that partially overlaps the p-type isolation region 2 and is short-circuited to this isolation region. and a P-type emitter region 5 surrounded by the collector region 14, an n ⁺ -type base electrode extraction region 6 formed in the epitaxial base region 3 facing the emitter region 5 outside the collector region, etc. is the conventional first
It is the same as shown in the figure. However, it differs from the conventional one in that a cut gap 15 in the forward direction is provided in the collector region 14 surrounding the emitter region 5 at a position sandwiched between the base electrode extraction region 6 and the emitter region 5. It's on.

By having such a cut gap 15,
Even when the collector-base voltage V _CB is high enough to pinch off the parasitic junction field effect transistor as shown in FIG. does not fully expand, leaving a tunnel-like channel 16, which does not pinch off in practical V _CB , and the current path between the emitter electrode 5a and the base electrode 6a is never opened. For example, traditionally 25-30V V _CB
There were many things that pinched off with 50
Improved to ~60V.

In the above embodiment, one conductivity type corresponds to P type and the opposite conductivity type corresponds to n type, but one conductivity type corresponds to n type,
It goes without saying that the present invention is also applicable to npn transistors whose conductivity type is P type.

[Brief explanation of drawings]

Figures 1a and b are a plan view and a cross-sectional view of an integrated circuit type transistor in a conventional semiconductor device;
Figures a, b and c are operation explanatory diagrams and equivalent circuit diagrams for explaining the operation of the transistor shown in Figure 1 with a power supply added, and Figures a, b and c are plan views of one embodiment of the present invention. and A-A' cross-sectional view and B
-B' cross-sectional view. 1... P-type semiconductor substrate, 2... P-type isolation region,
3...n-type epitaxial base region, 3'...
n-type epitaxial layer, 4...collector region, 4
a... Collector electrode, 5... Emitter region, 5a
... Emitter electrode, 6 ... Base electrode extraction region, 6a ... Base electrode, 7, 8 ... Depletion layer, 1
4...Collector region with cut gap, 14a...
...Collector electrode, 15... Cut gap.

Claims (1)

[Claims] 1 A semiconductor board of one conductivity type, an isolation region of one conductivity type formed in a frame shape in an epitaxial layer of the opposite conductivity type laminated on the upper surface of this substrate, and an epitaxial base region surrounded by this isolation region. A base electrode extraction region of opposite conductivity type and an emitter region of one conductivity type are selectively formed at predetermined intervals in this epitaxial base region, and a portion thereof is short-circuited to the separation region and the base electrode a collector region of one conductivity type selectively formed in the epitaxial base region surrounding the emitter region while having a cut gap in the width direction at a position sandwiched between the take-out region and the emitter region; and a base electrode, a collector electrode, and an emitter electrode provided on the upper surface of the base electrode extraction region, collector region, and emitter region, respectively.