JPS6236864A - Lateral transistor - Google Patents

Abstract

PURPOSE:To enhance the current amplification factor by forming an N<+> type well region in a region to become a base to narrow the base width, thereby obtaining high frequency characteristic. CONSTITUTION:A well region 35 which has a specific resistance rho lower than an epitaxial layer 25 is formed on an insular region 25 between an emitter region 26 and a collector region 27. Thus, the region 35 suppresses a depletion layer generated in a base-emitter junction and a base-collector junction to prevent the contacts of the right and left depletion layers in the suppressed amount, thereby narrowing the base width while maintaining the prescribed withstand voltage. If the base width can be narrowed, a carrier traveling time in the base can be reduced. Thus, the high frequency characteristic fT of the transistor increases, and the current amplification factor hFE accordingly increases. However, since the hFE is decreased by the fact that the impurity density of the well region 35 is higher than the epitaxial layer 25, it does not become extremely high.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to improvements in lateral PNP transistors incorporated into semiconductor integrated circuits.

(B) Conventional technology Conventionally, as a lateral PNP type transistor incorporated in a semiconductor integrated circuit, for example, Japanese Patent Application Laid-Open No. 59-159566
There are some that are listed in the publication.

That is, as shown in FIG. 3, an N-type epitaxial layer (2) formed on a P-type semiconductor substrate (1), an N-type buried layer (3) provided on the surface of the substrate (1), and this buried layer (3) are formed on a P-type semiconductor substrate (1). Layer (3)
A P+ type isolation region (4) penetrating the epitaxial layer (2) so as to surround it, an island region (5) separated into islands by the isolation region (4), and a P+ type isolation region (5) separated on the surface of the island region (5). P-type emitter region (6) and P-type collector region (7) arranged in
) and N+ type base contact region (8), an oxide film (9) covering the epitaxial layer (2), and an oxide film (9) covering the epitaxial layer (2).
) is in ohmic contact with the emitter region (6), collector region (7), and base contact region (8) through the electrode holes of the emitter electrode (10, consisting of 0 υ collector electrodes and 0 base electrodes. Island region) (5) is the base, and the island region (5) between the emitter region (6) and the collector region (force) is the substantial base, and the distance between them is the base width.

(c) Problems to be solved by the invention However, in such a lateral PNP transistor, the specific resistance ρ of the epitaxial layer (2) is high (1 to 4 Ω).
Therefore, the depletion layer tends to expand at the base-emitter junction and the base-collector junction, and the base width cannot be reduced in order to prevent the left and right depletion layers from coming into contact with each other and to obtain a predetermined withstand voltage.

As a result, the traveling time of the carrier within the base becomes long and there is a drawback that the high frequency characteristics f cannot be improved.

The present invention has been made in view of the above-mentioned drawbacks, and the base width is narrowed (
The purpose of this is to realize a lateral PNP transistor with a high value of f.
The feature is that a mold well region (c) is formed.

(E) Function According to the present invention, since the well region 0!19 suppresses the depletion layer generated at the base-emitter junction and the base-collector junction, the base width or The distance between the emitter region (A) and the collector region (5) can be reduced.

(f) Example The present invention will be explained below with reference to the drawings.

FIG. 1 shows a first embodiment of the present invention, in which P-type separation reaches from the surface of an N-type epitaxial layer (2) formed on a P-type semiconductor substrate 01) to the substrate 01). Region H, an island region (c) electrically separated from other regions by a separation region (goods), and island region r2!
9, an N-type buried layer (c) buried in the bottom of the island region (to), a P-type emitter region (5) and a P-type well region (5) spaced apart on the surface of the island region (to), and an N-type base contact region. C
An oxide film covering the N-type well region 09 formed on the surface of the island region (c) between the emitter region (a) and the collector region, that is, the region that essentially becomes the base, and the epitaxial layer Q. Then, each region CI'6) @ (lateral PNP from the emitter electrode (to) that makes 2 (to) K ohmic contact, the collector electrode 01) and the base electrode 0) is connected through the electrode hole opened in the oxide film. It is configured. In the present invention, substantially the well region G
9 acts as a base, and is led out by the base contact region (to) via the island region (251).The specific resistance ρ of the well region C3S1 is at least lower than that of the three epitaxial layers, and in this example, the emitter region (
a) and the collector region (2'7) are provided so as to slightly overlap each other.

The most distinctive feature of the present invention is the six groups of well regions. In other words, the resistivity ρ is lowered by the epitaxial layer (c) on the surface of the island region (c) between the emitter region (e) and the collector region.
Since a well region 0 with low impurity concentration (high impurity concentration) is provided, the well region C3 suppresses the depletion layers generated at the base-emitter junction and the base-collector junction, and the left and right depletion layers contact each other by the suppressed amount. This makes it possible to reduce the base width while maintaining a predetermined withstand voltage.

If the base width can be narrowed, the carrier transit time within the base will be reduced, so the high frequency characteristics of the transistor f? This has the effect of increasing the current amplification factor h□ and further increasing the current amplification factor h□. However, h□ does not become extremely high because the fact that the impurity concentration in the well region I35+ is higher than that in the epitaxial layer (c) acts to lower h□.

FIG. 2 shows a second embodiment of the present invention, in which an emitter region (e) and a collector region (5) are provided on the surface of the well region (c).
). In this embodiment as well, the same effects as in the first embodiment can be obtained.

A method for manufacturing a lateral PNP transistor according to the present invention will be briefly described below. First, P-type semiconductor substrate C! A region to become a buried layer (c) on the υ surface is doped with a KN-type impurity, such as phosphorus, and then an epitaxial layer (c) is formed by vapor phase growth.
form c). Next, using selective diffusion method, P-type impurity,
For example, boron is diffused to form the isolation region 124).

This doped N-type impurity is diffused in the vertical direction to form a buried layer (c). Next, the N-type impurity is diffused again using the selective diffusion method to form a well region 05). The diffusion depth is determined by the emitter region (
(e) or slightly deeper than the collector region (b), and the impurity concentration is set higher than that of the epitaxial layer c22. Then, selective diffusion is performed twice again to form the emitter region (a), collector region (5), and base contact region (c), and finally each region (26), (27), and (28) is formed.
The electrode (30) C31) is disposed on j and the process is completed.

(G) As described in detail, according to the present invention, the base width can be narrowed by the well region G, so that high frequency characteristics f
? It has the advantage that it can be obtained.

Furthermore, it also has the advantage that hfl can be increased because the base width can be narrowed.

[Brief explanation of the drawing]

1 and 2 are sectional views showing a first embodiment and a second embodiment of the present invention, respectively, and FIG. 3 is a sectional view showing a conventional lateral PNP transistor. Explanation of the main figure numbers (102+) is the semiconductor substrate, (5)+2 is the island region, (
6) (261 is the emitter area, +7) (2η is the collector area, 0 town is the well area. Applicant Sanyo Electric Co., Ltd. and one other representative Patent attorney Shizuka Sano Mistake 1 Figure 2

Claims (1)

[Claims] 1) Separated into islands by an epitaxial layer of opposite conductivity type formed on a semiconductor substrate of one conductivity type, a buried layer of opposite conductivity type provided on the surface of the substrate, and a separation region of one conductivity type penetrating the epitaxial layer. In a lateral transistor comprising an island region, and an emitter region and a collector region of one conductivity type that are spaced apart from each other on the surface of the island region, by forming a well region of an opposite conductivity type in a region that substantially becomes a base, A lateral transistor characterized by suppressing the spread of a depletion layer at the base.