JPS5914897B2 - semiconductor equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to a semiconductor integrated circuit including complementary transistors.

Generally, in semiconductor integrated circuits including complementary transistors, that is, NPN transistors and PNP transistors, it is difficult to obtain so-called high performance 10 PNP transistors, which have higher breakdown voltage and better current characteristics and high frequency characteristics than NPN transistors.

That is, a semiconductor integrated circuit including this type of complementary transistor is, for example, a vcP type semiconductor substrate 1 as shown in FIG.
First and second N-type epitaxial growth layers 2 and 3 are sequentially formed on the top, and a P-type buried layer and an N-type buried layer are respectively formed in 15 divided regions of the P-type isolation region 4, respectively. A PNP transistor (PNPTr) having a collector 5, a base 6, and an emitter T is formed in one region, and an NPN transistor (NPNTr) having a collector 8, a base 9, and an emitter 10 is formed in the other region. . Note that Cl, B, and E1 represent the collector electrode, base electrode, and emitter electrode of the PNP transistor, and C2, B2, and E2 represent the collector electrode, base electrode, and emitter electrode of the NPN transistor. 25 However, in the case of a PNP transistor in which the epitaxially grown layer is used as the base region 6, the current characteristics of the current amplification factor hFE are poor because the base region 6 has a low concentration.

To improve this, it is desirable to make the impurity concentration profile of the base and emitter of the PNP transistor double-diffused, but this is difficult in semiconductor integrated circuits. or,
Since the emitter region T and the collector region 5 are highly doped and the base region 6 is lightly doped, the depletion layer from the collector junction jc flows into the base region 6 during operation of the PNP transistor.
It mainly spreads to the side, and the withstand voltage is determined by punch-through, making it impossible to obtain a high withstand voltage. On the other hand, in order to increase the withstand voltage, the base width may be increased, but since the base width mainly determines the frequency characteristics, in this case, although the withstand voltage increases, the cutoff frequency FT deteriorates.

In order to avoid this deterioration of the cutoff frequency FT, for example, a higher concentration N-type impurity is diffused into the lower concentration base region 6 to form a higher concentration base region, and the emitter diffusion is deepened to increase the base width. Although it is conceivable to reduce the concentration, in this case, since the collector region 5 is highly concentrated, the withstand voltage of the collector junction Jc will be lowered. The present invention aims to introduce a PNP transistor with high breakdown voltage and good HFE current characteristics and frequency characteristics, and to provide a semiconductor integrated circuit having complementary transistors with high performance.

The present invention also provides a semiconductor integrated circuit in which a low concentration emitter type transistor (1,(5)D) previously developed by the applicant can be introduced as a complementary transistor.

After referring to FIG. 2, we will first explain the LEC transistor.

To explain the NPN transistor, in this case, N
A type semiconductor substrate 11 having a high impurity concentration is provided, an N type semiconductor layer 12 having a low impurity concentration is epitaxially grown on this, and this semiconductor layer 12 is used as a first region to be in contact with this, P surrounded by this
A third region 14 having an impurity concentration equal to or sufficiently lower than that of the region 13, for example, about 1015/Crll, is provided in contact with this region 13 and surrounded by it. and this third region 14
A potential barrier is formed within the region 14 opposite to the junction J34 formed between the region 14 and the second region 13 and having a distance from the region 13 that is smaller than the diffusion distance of minority carriers in the region 14. Form JB. Although this potential barrier JB has the same conductivity type as the region 14, for example,
A high concentration region 15 having a concentration sufficiently higher than this is defined as region 1.
4 and formed by this region 15.
It can be constructed by joining. With such a configuration, an NPN transistor is constructed in which region 14 is an emitter region and region 12 is a collector region.

16, 17, and 18 are emitter, base, and collector electrodes, respectively.

A voltage is applied to each electrode 16, 17, and 18 to apply a forward bias to the PN junction between the regions 14 and 13, that is, the emitter junction J34, and to apply a reverse bias to the PN junction between the regions 13 and 12, that is, the collector junction J32. If you give it,
Electrons injected into the base region 13 from the emitter region 14 can reach the collector region 12 by selecting the spacing between junctions J34 and J32 to be smaller than the diffusion distance of minority carriers in the region 13, and can reach the collector region 12 of the transistor. make an action. In this case, the emitter injection efficiency γ
Therefore, in order to increase HFE and therefore γ, if the carrier injected into the base, that is, the current due to electron diffusion in FIG. In the example shown in FIG. 2, a barrier J formed by an L-H junction is placed opposite the junction J34.
For example, this barrier JB lowers the impurity concentration in the low concentration portion of the region 14 to 1015.4d.
When the concentration in region 15 is set to about 102 degrees/CJ, a potential barrier of about 0.2 eV is generated for holes, and in this case, the minority carriers injected from region 13 into region 4 reach barrier JB. As a result, the concentration gradient in this region 14 is flattened, and the injection of carriers (holes) from the region 13 to the region 14 is suppressed, thereby improving the injection efficiency γ and increasing the HFE. .

Moreover, junction J34 becomes emitter junction and collector junction.
and J3. Since the impurity concentration is selected to be low in the region where the transistor is formed, crystal defects are small and the HFE is sufficiently high compared to a normal high concentration emitter type transistor. Second
In the example shown in the figure, a region 15 is formed in the first region 14 and a barrier JB is formed by L-H junction, but as shown in FIG. It is also possible to form a fourth region 19 of the shape and form the barrier JB by a PN junction.

In this case, the minority carriers injected into the region 14 from the region 13 are directed to the region 19, and the potential of the region 19 becomes approximately the same as that of the region 3. By reinjecting the VC holes from the region 19 into the region 14, The hole concentration gradient is flattened to reduce the diffusion current of the holes, thereby improving the emitter injection efficiency γ and increasing the current amplification factor HFE. In addition, in the example of FIG. 3, area 19 is changed to area 14.
Although this is a case in which the region 19 and the region 13 are electrically floating independently of the region 13, the region 19 and the region 13 may be partially electrically connected as shown in FIG. I can do it.

In FIGS. 3 and 4, parts corresponding to those in FIG. 2 are designated by the same reference numerals, and redundant explanation will be omitted. In a semiconductor device having complementary transistors according to the present invention, one transistor of the complementary transistors, that is, an NPN transistor may be formed with the above-mentioned specially constructed LEC transistor.

Hereinafter, one embodiment of the semiconductor device of the present invention will be described in detail together with its manufacturing method with reference to FIG.

In this example, the NPN transistor is formed of an LEC transistor. First, Figure 5 AVC. As shown, for example, the specific resistance is about 15Ω-m (impurity concentration 1×
A P-type semiconductor substrate 21 of 1015/Cd) is prepared, and an impurity concentration of, for example, 5×10
An N-type buried layer 22 of approximately 1× is formed by diffusion,
Further, an N-type buried layer 23 having an impurity concentration of, for example, about 1.times.10@19 /Cril is formed by diffusion at a position corresponding to a portion where an NPN transistor is to be formed (FIG. 5A).

24 is an insulating layer such as a SiO2 film.

Next, the SiO2 film 24VC is photoetched to form a diffusion window on one of the N-type buried layers 22, and P-type impurities are diffused through this diffusion window to form a P-type buried layer that will become the collector buried layer of the PNP transistor. After forming a layer 25 (for example, with an impurity concentration of about 1×10 11 d), a layer 25 with a resistivity of 10Ω-? Form a first epitaxial growth layer 26 of N type (
Figure 5 C and D).

Next, photoetching is performed on the SiO2 film 24 to form diffusion windows in which isolation regions are to be formed in a lattice shape when viewed from above at positions that separate the parts where PNP transistors and NPN transistors are to be formed, and through these diffusion windows. P-type impurity is diffused to form a P-type isolation region 27 that reaches the sub-snoft rate 21 (
Figure 5E).

Next, one region divided by the isolation region 27 of the first epitaxial growth layer 26, that is, the region 26A where a PNP transistor is to be formed, is coated with a lower concentration than the P-type buried layer 25, for example, about 5×10 15 /Crl. The P-shaped region 28 of P
Formed by diffusion so as to reach the shape buried layer 25,
Subsequently, a P-type region 29 is formed, for example, by ion implantation in the other region, that is, the region 26B where the NPN transistor is to be formed.

This P-type region 29 will eventually become the base region of an NPN transistor of LEC structure. Thereafter, an N-type second epitaxial growth layer 30 is formed on the first epitaxial growth layer 26. In this case, the impurity concentration of the second epitaxial growth layer 30 is, for example, about 5×101'/Cd (FIGS. 5F and G). Next, a high concentration P-type impurity is selectively diffused into the second epitaxial growth layer 30, and the isolation region 31 that separates the portions where the PNP transistor and the NPN transistor are to be formed is formed into the lower isolation region 2.
At the same time, in the respective regions 30A and 30B separated by the isolation region 27 of the second epitaxial growth layer 30, an annular high-concentration layer is formed so as to reach the P-type regions 28 and 29, respectively. P-type regions 32 and 33 are formed by diffusion (FIG. 5H).

Next, a second epitaxial growth layer is formed, consisting of a P-type region 3.
Finally, P is formed in the low concentration N-type region 30A surrounded by
N-type diffusion region 3 that becomes the base region of the NP transistor
form 4.

This N-type diffusion region 34 is in contact with the VCP-type region 28 and P
a higher impurity concentration than the shaped region 28, for example 1×101'd
It has a certain degree. (Figure 5 1). Next, this N
For example, a P-type region 35 with an impurity concentration of about 1×1020/Cil is formed in the type diffusion region 34 to serve as an emitter region (FIG. 5J), and then a high concentration of N-type impurity is selectively diffused to form an N-type region. A high concentration region 36 for taking out the base electrode is provided in the diffusion region 34, and a high concentration region 38 is provided in the low concentration region 37 which becomes the emitter surrounded by the P type region 33 in the divided region 30B made of the second epitaxial growth layer. In addition, a high concentration region 39 for extracting the collector electrode is formed in a region not surrounded by the P-type region 33 of the region 30B.

In this case, the region 38 is used for taking out the emitter electrode, and at the same time, the L-H junction JB serves as a potential barrier for minority carriers in the region 37 between the region 38 and the low concentration region 37.
This L-H junction JB is an additional region forming VC! between regions 37 and 29. The joint J formed
They may be formed so that they face each other and the distance therebetween is smaller than the diffusion distance of minority carriers in the region 37 (FIG. 5K). Thereafter, the collector electrode Cl, the emitter electrode E1, and the base electrode Bl of the PNP transistor are formed in the regions 32, 35, and 36, respectively, and the regions 39, 33, and 3
8, a collector electrode C2, a base electrode B2, and an emitter electrode E2 of the NPN transistor are formed, respectively.

Thus, as shown in FIG. 5L, in the first island region divided by the separation regions 27 and 31, the P-type regions 25 and 38 are used as collector regions, the N-type diffusion region 34 is used as a base region, A PNP transistor Trl is formed using the P-type region 35 as an emitter region, and a region 2 consisting of the first and second epitaxial growth layers is formed in the divided second island region.
6B and 30B are collector regions, the P type region 29 made of, for example, ion implantation is used as a base region, and the L-H junction J is made of a second epitaxial growth layer.
A semiconductor device having an intended complementary transistor is obtained in which an NPN transistor Tr2 having an LEC structure is formed and has an N-type low concentration region 37 containing B as an emitter region.

According to the semiconductor device described above, it is possible to obtain a high-performance PNP transistor that coexists with a high-performance NPN transistor having excellent breakdown voltage, HFE current characteristics, and high-frequency characteristics.

That is, as for the NPN transistor, it is already clear that a high-performance transistor can be obtained, so the explanation will be omitted, but in the circular transistor Trl, the P-type region 28 is formed by low concentration diffusion in the first epitaxial growth layer 26. Since the base region 34 and the emitter region 35 are formed by so-called double diffusion using the second epitaxial growth layer 30 formed on the collector region 28, the base width is small and the cut-off frequency FT is high. As a result, high-frequency recognition is improved, and at the same time, the current performance of the HFE is improved, and a PNP transistor for large currents can be obtained. Regarding breakdown voltage, since the collector region 38 in contact with the base region 34 has a low concentration, the depletion layer of the collector junction Jc mainly spreads toward the low concentration collector region 38 side.
Punch-through with respect to 5VC is avoided, and the withstand voltage can be improved.

Incidentally, when having the impurity concentration profile in the embodiment shown in FIG. 5, the cutoff frequency FT can be 100 MHz or more, the withstand voltage can be 50 V or more, and the collector saturation resistance can be low. Furthermore, this PNP transistor Trl can coexist with a high-performance NPN transistor Tr2 having an LEC structure.

Since a semiconductor integrated circuit including a currently desirable LEC (7) NPN transistor requires two epitaxial growths, even if the PNP transistor Trl of the present invention is included, it can be formed without increasing epitaxial growth. can. Furthermore, although not shown, the low concentration of P in Figure 5
The shaped region 28 can also be formed by using aluminum, which has a high diffusion rate, for example, and diffusing from the surface of the second epitaxial growth layer 30 after the first and second epitaxial growth layers 26 and 30 are formed. is formed by triple diffusion including the base region 34 and emitter region 35. FIG. 6 shows another embodiment.

First, as shown in Figure 6A, for example, the specific resistance is 3 to 5Ω.
−? A P-type semiconductor substrate 41 is prepared, and a dose amount of 2X1012/Cri. An N-type buried layer 42 of about 100 mL is formed.

43 is an insulating layer such as a SiO2 film (FIG. 6B).

Next, in the N-type buried layer 42 and on the substrate 41, a relatively high concentration P-type region 44 is formed at a position corresponding to the part where the PNP transistor and the NPN transistor are finally separated. P-type separated pirates 45 are formed. This P-type region 44 becomes a buried collector layer of a PNP transistor. Note that the P-type region 44
The sheet resistance ρ8 of the separation region 45 can be set to, for example, about 250 koi (FIG. 6C). Next, a relatively high concentration N-type buried layer 46 is formed by diffusion at a position on the substrate 41 corresponding to a portion where an NPN transistor is to be formed so as to be surrounded by the isolation region 45, and at the same time, the N-type buried layer 46 is An N-type region 47 for isolation is formed at a position surrounding the P-type region 44 (FIG. 6D).

The sheet resistance .rho.8 of the N-type buried layer 46 and the N-type isolation region 47 can be, for example, approximately 5.5 mm.
In particular, NPN transistors with a conventional LEC structure and {
It was difficult to make a VCPNP transistor with good characteristics, but when the emitter region of the LEC transistor and the base region of the PNP transistor are made into the same epitaxial growth layer, N+ is diffused there and the emitter region of the PNP transistor is formed in it. When formed, frequency characteristics can be improved. Further, by configuring the collector region of the PNP transistor by connecting the P-type buried layers 25 and 28 formed above and below the epitaxial growth layer, the collector resistance can be made sufficiently low. Next, Substrate 4
For example, a P with a specific resistance of 5 Ω-m and a thickness of about 8 μm is placed on top of 1.
A first epitaxial growth layer 48 of a type N-type and a second epitaxial growth layer 49 of an N-type, for example, having a resistivity of 2 Ω-m and a thickness of about 4 μm are formed (FIG. 6E). Next, a relatively high concentration of P is selectively applied to the surface of the second epitaxial growth layer 49.
The P type impurity is diffused into a position opposite to the P type region 44 and a P type impurity.
The P-type regions 5 are annular when viewed from above and reach the first epitaxial growth layer 48VC at positions corresponding to the type isolation regions 45, respectively.
0 and a grid-like P-type isolation region 51 is formed when viewed from above.

At the same time, the N-type buried layer 46 and the isolation N-type region 47 are re-diffused and reach the second epitaxial growth layer 49 through the first epitaxial growth layer 48 (FIG. 6F). Next, for example, ion implantation (for example, at a dose of 1×101
3? A P-type region 52, which will become the base region of the NPN transistor, is formed (FIG. 6G), and then a second
For example, on the epitaxial growth layer 49, a resistivity of 2Ω-m is formed.
A third epitaxial growth layer 53 of approximately N type is formed (FIG. 6H).

Next, N-type impurities are selectively diffused from the surface of the third epitaxial growth layer 53 to form a P-type second epitaxial growth layer 4 in a portion where the base region of the PNP transistor is to be formed.
The N-type diffusion region 54, which becomes the base region reaching 8.
An N-type region 55 that surrounds the P-type region 52 serving as a base and is continuous with the N-type buried layer 46 is formed in a portion forming the collector region of the N-transistor, and is also continuous with the isolation region 47 at a position corresponding to the N-type isolation region 47. N type isolation regions 56 are respectively formed.

Note that the sheet resistance ρ8 of each region 54, 55, and 56 is 120Ω/? (Figure 6). Next, a high concentration of P-type impurity is selectively diffused into the N-type region 54 to form a P-type impurity that will eventually become the emitter region of the PNP transistor.
The shaped region 57 is continuous with the P-shaped region 50 and finally becomes PNP.
A high concentration region 58 that will become a region for taking out the collector electrode of the transistor, a high concentration region 59 that will become a region for taking out the base electrode of the final VCNPN transistor, and a P-type isolation region 60 that is continuous with the P-type isolation region 51 are formed. do.

At this time, the sheet resistance Ps of each region 57, 58, 59, and 60 can be set to 10mm (FIG. 6J).
Next, selective diffusion of high-concentration N-type impurities is performed, and finally, L-
The high concentration region 62 forming the H junction is connected to the N type region 55.
High concentration region 6 for extracting the collector electrode of the PN transistor
3, a high concentration region 64 for taking out the base electrode is formed in the N type diffusion region 54 which becomes the base region of the PNP transistor, and a high concentration region 65 for taking out the electrode for isolation is formed in the N type isolation region 56. .

At this time, the sheet resistance ρ8 of each region 62, 63, 64, and 65 can be set to 109j (FIG. 6K). Thereafter, emitter electrodes E, base electrodes B, and collector electrodes C of PNP transistors are formed in regions 57, 64, and 58, respectively, and regions 62, 59, and 63VCN are formed.
Emitter electrode E2 and base electrode B2 of PN transistor
A collector electrode C2 is formed, and a separation electrode 66 is further formed in the region 65. Thus, as shown in FIG. 6L, a P type region 48A consisting of a p+ type region 44 and a first epitaxial growth layer is formed in the first island region divided by the buried layer 42 and isolation regions 47 and 56. Let be the collector area,
A PNP transistor Trl is formed with the N-type diffusion region 54 as a base region and the P-type region 57 as an emitter region. A region 49B consisting of two epitaxially grown layers is used as a collector region. For example, a P-type region 52 made of ion implantation is used as a base region, and an N-type low concentration region 61 formed with an L-H junction JB made of an N-type third epitaxial growth layer is used as an emitter region. LECf) NPN transistor T
A semiconductor device having its own complementary transistor formed by r2 is obtained.

According to such a semiconductor device, the structure is similar to the semiconductor device obtained in FIG. 5.

That is, in the circular transistor Trl, the collector region is formed by forming the low concentration region 48A. 1! : A region 44 with a high concentration is formed by embedding, and a base region 54 and an emitter region 57 are formed by double diffusion using second and third epitaxial growth layers. Therefore, a high-performance PNP transistor with improved high frequency characteristics and HFE current characteristics and improved collector junction breakdown voltage can be obtained. Regarding manufacturing, P-type and N-type epitaxial growth layers 48 and 49 are formed, and medium concentration (for example, 101
7 to 1018/Cd) and the N-type buried layer 46 with a high concentration (for example, 1028/Cd) to the P-type epitaxial growth layer 48. On the NPN transistor side, a low concentration portion 48A and a high concentration portion 44 are formed as a collector, and a low concentration portion 49B and a high concentration portion 46 as a collector are formed on the NPN transistor side.
is formed, and then the base region 5 of the NPN transistor is formed.
2 is formed, a third N-type epitaxial growth layer 53 is formed, and then the base and emitter of the PNP transistor are deeply diffused. Furthermore, the emitter diffusion of the PNP transistor is performed in the same process as the high concentration diffusion for extracting the base electrode of the NPN transistor. Therefore, the number of steps is relatively small, making it easy to manufacture this type of semiconductor device. FIG. 7 shows yet another embodiment.

In addition, in this example, LEC (7) NPN transistor and P
This is a case where the present invention is applied to a semiconductor integrated circuit that combines an NP transistor and a resistor. First, as shown in Figure 7A,
For example, a P-type semiconductor substrate 71 with a specific resistance of about 3 to 5 Ω-m is prepared, and a P-type semiconductor substrate 71 with a specific resistance of about 3 to 5 Ω-m is prepared, and a P-type semiconductor substrate 71 is placed on one surface thereof at a position corresponding to a portion where an NPN transistor is to be formed and a portion where a PNP transistor and a resistor are to be formed. High concentration N-type buried layers 72 and 73 having a sheet resistance ρ8 of about 20 Ω/hole, for example, are formed at corresponding common positions by diffusion (FIG. 7B).

Note that 74 is an insulating layer made of a SiO2 film or the like. Next, on the substrate 71, P-type isolation regions 75 are formed in a lattice shape when viewed from above dividing the N-type buried layers 72 and 73, respectively.
(Sheet resistance ρ8 is about 10Ω) is formed by diffusion,
After that, the entire surface of the substrate 71 has a specific resistance of, for example, 4 to 7 Ω-? The first N-type epitaxial growth layer 7 of
form 6. 74' is an insulating layer such as a SiO2 film (FIG. 7D).

Next, P-type impurities are selectively diffused into the N-type epitaxial growth layer 76 to form a P-type isolation region 77 continuous with the region 75 in a portion facing the P-type isolation region 75, and at the same time to form a P-type isolation region 77 in a portion where a PNP transistor is to be formed. A P-type region 78 is formed to serve as a collector region (FIG. 7E).

Next, a P-type region 79, which will later become a base region, is formed by diffusion at a position corresponding to a portion of the N-type epitaxial growth layer 76 where an NPN transistor is to be formed, and a P-type region 79, which will later become a base region, is formed by diffusion in a portion where a resistor is to be formed in the N-type epitaxial growth layer 76. A P-type region 80 that becomes a resistor is formed.

In this case, the sheet resistance of regions 79 and 80 is 10
It can be set to 00 甐Ij (FIG. 7F). After that,
A second N-type epitaxial growth layer 81 is formed on the N-type epitaxial growth layer 76 (FIG. 7G). Next, the second
By selectively diffusing P-type impurities into the N-type epitaxial growth layer 81, a P-type isolation region 82 continuous to the isolation region 77 and a part of the base region of the NPN transistor The P-type region 83 constituting the P-type region 78 is continuous to the P-type region 84 constituting a part of the collector region of the PNP transistor. Shape areas 85A, 85B
(Fig. 7H). Next, N-type impurities are selectively diffused into the second N-type epitaxial growth layer 81ffC (sheet resistance is approximately 100 mm), and N-type impurities are deposited on the portion that will become the collector of the NPN transistor to take out the collector electrode.
An L-H junction JB is formed in a region 86 surrounded by a base region 83 which becomes a low concentration emitter, and an N type high concentration region 87 is formed into a part which becomes a base of a PNP transistor and becomes a collector. The N-type high concentration region 90 is further divided by a P-type isolation region 82 so as to leave a low concentration region 89 between it and the P-type region 78, and an N-type region on the side where the PNP transistor and resistor are formed. High concentration regions 91 for taking out electrodes for separation are formed respectively (FIG. 7, 1).
Next, selective diffusion of high concentration P type impurity is performed (sheet resistance is about 10Ω/hole), and the high concentration region 92 for extracting the base electrode of the PNP transistor, the P type region 93 which will become the emitter of the PNP transistor, and the P High concentration region 94 for extracting the collector electrode of the transistor and P serving as a resistor
High concentration regions 95A and 95B for electrode extraction in the shaped region 80 are formed. After that, NP is applied to areas 87, 92, and 88, respectively.
The emitter electrode E1, base electrode B1 and collector electrode C1 of the N transistor are formed, and the regions 93, 90 and 94 are formed.
An emitter electrode E2, a base electrode B2, and a collector electrode C2 of a PNP transistor are respectively formed in the area 9.5A.
and 95B, a pair of resistor electrodes R1 and 95B, respectively. A region 91VC isolation electrode 96 is further formed.

In this way, as shown in FIG. 7J, the N-type region 78A made of the first epitaxial growth layer is used as a collector region, the P-type region 79 is made a base region, and the region 87 made of the second epitaxial growth layer is used as a collector region. A LECPN transistor Tr2 is formed in which the N-type low concentration region 86 in which the L-H junction JB is formed is used as an emitter region, and the P-type region 78 is used as a collector region, and is formed by second epitaxial growth. N-type low concentration region 89 and N-type region 90 due to diffusion
A PNP transistor Trl is formed, which has a base region and a diffused P-type region 93 as an emitter region,
Further, a target semiconductor integrated circuit in which a resistor R is formed in the P-type region 80 is obtained.

According to such a semiconductor integrated circuit, a high-performance PN transistor coexists with a high-performance NPN transistor as shown in FIGS. 5 and 6.
A P transistor is obtained.

In other words, although a description of the NPN transistor will be omitted, in the PNP transistor Trl, the base region 90 and emitter region 93 are formed by double diffusion using the second epitaxial growth layer 76, so that high frequency characteristics and H
The current characteristics of FE are improved. Further, since the portion of the base region in contact with the collector region is a low concentration region 89 formed by an epitaxial growth layer, the withstand voltage of the collector junction can be maintained.
However, since the portion of the base region away from the collector junction is a highly concentrated region 90, punch-through during operation can be avoided and the withstand voltage can be improved. As described above, according to the present invention, it is possible to obtain a high-performance NPN transistor as well as a high-performance PNP transistor with high breakdown voltage and good current characteristics and frequency characteristics, thereby obtaining a semiconductor integrated circuit having excellent complementary transistors.

Further, in the present invention, the PNP transistor Trl can be formed coexisting with the LECf)NPN transistor Tr2, so it is suitable for introducing the LEC transistor into a semiconductor integrated circuit.

In the above example, the NPN transistor is formed using an LEC transistor, but it can also be formed using a normal high-concentration emitter transistor.

Furthermore, although the NPN transistor of the LEC in the above example has a configuration having an L-H junction, the LEC configuration shown in FIGS. 3 and 4 can also be used.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing an example of a semiconductor device having a conventional complementary transistor, FIGS. 2 to 4 are cross-sectional views showing examples of an LEC transistor applied to the present invention, and FIG. 5 is a cross-sectional view showing an example of a semiconductor device having a conventional complementary transistor. FIGS. 6 and 7 are cross-sectional views showing steps in order of steps showing one embodiment of a semiconductor device, and FIGS. 6 and 7 are cross-sectional views showing steps in order of steps showing other embodiments, respectively. 21 is a semiconductor substrate of the first conductivity type, 26, 30
35 is an epitaxial growth layer of the second conductivity type, 35 is an emitter region of the first conductivity type, 34 is a base region of the second conductivity type formed by diffusion, 38 is a collector region of the first conductivity type, and 37 is an epitaxial growth layer of the first conductivity type. emitter region of two conductivity types,
29 is a base region of the first conductivity type, 26B is a collector region made of an epitaxial growth layer, El, B, Cl are P
The emitter, base and collector electrodes of the NP transistor, E2, B2 and C2 are the emitter, base and collector electrodes of the NPN transistor.

Claims (1)

[Claims] 1 A semiconductor substrate of a first conductivity type, first and second semiconductor layers of a second conductivity type sequentially formed on the substrate, and a first conductivity that separates the semiconductor layer between the first and second portions. first and second regions of a second conductivity type formed in the first and second portions, respectively, between the substrate and the first semiconductor layer; a third region of the first conductivity type; and the first and second semiconductor layers between the first and second semiconductor layers.
a seventh region of the second semiconductor layer separated from other parts by fourth and fifth regions of the first conductivity type formed in the portion, and a sixth region of the first conductivity type connected to the fourth region; and the fifth above
a ninth region of the second semiconductor layer separated from other parts by an eighth region of the first conductivity type connected to the region; a higher impurity concentration portion formed in the seventh region; a tenth region of the first conductivity type formed in the portion; a portion with a higher impurity concentration formed on the surface of the ninth region;
A semiconductor device comprising a first transistor having the tenth, seventh and fourth regions, and a second transistor having the ninth, fifth and second regions.