CA1048655A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- CA1048655A CA1048655A CA76245057A CA245057A CA1048655A CA 1048655 A CA1048655 A CA 1048655A CA 76245057 A CA76245057 A CA 76245057A CA 245057 A CA245057 A CA 245057A CA 1048655 A CA1048655 A CA 1048655A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 41
- 239000012535 impurity Substances 0.000 claims abstract description 64
- 238000009792 diffusion process Methods 0.000 claims abstract description 46
- 239000000758 substrate Substances 0.000 claims abstract description 41
- 238000002955 isolation Methods 0.000 claims description 39
- 230000015572 biosynthetic process Effects 0.000 claims description 25
- 239000000969 carrier Substances 0.000 claims description 14
- 230000004888 barrier function Effects 0.000 claims description 11
- 230000015556 catabolic process Effects 0.000 claims 1
- 230000005684 electric field Effects 0.000 claims 1
- 230000000295 complement effect Effects 0.000 abstract description 13
- 238000010276 construction Methods 0.000 abstract description 3
- 230000012010 growth Effects 0.000 description 57
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 238000005468 ion implantation Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 238000005036 potential barrier Methods 0.000 description 5
- 235000012239 silicon dioxide Nutrition 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 5
- 229910052681 coesite Inorganic materials 0.000 description 4
- 229910052906 cristobalite Inorganic materials 0.000 description 4
- 229910052682 stishovite Inorganic materials 0.000 description 4
- 229910052905 tridymite Inorganic materials 0.000 description 4
- 230000003321 amplification Effects 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 238000003199 nucleic acid amplification method Methods 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 241000353097 Molva molva Species 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- KRTSDMXIXPKRQR-AATRIKPKSA-N monocrotophos Chemical compound CNC(=O)\C=C(/C)OP(=O)(OC)OC KRTSDMXIXPKRQR-AATRIKPKSA-N 0.000 description 1
- 229920000136 polysorbate Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8222—Bipolar technology
- H01L21/8228—Complementary devices, e.g. complementary transistors
- H01L21/82285—Complementary vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/082—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only
- H01L27/0823—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only including vertical bipolar transistors only
- H01L27/0826—Combination of vertical complementary transistors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Bipolar Transistors (AREA)
- Bipolar Integrated Circuits (AREA)
Abstract
ABSTRACT OF THE DISCLOSURE
A semiconductor integrated circuit device having a con-struction of complementary PNP-NPN semiconductor devices in a mono-lithic integrated form. First and second N type epitaxial layers are formed on a common P type semiconductor substrate. A base region of the PNP transistor is produced by the diffusion of an impurity into the second epitaxial layer. The NPN transistor is formed as low emitter concentration type transistor and a part of the second epitaxial layer serves as the transmitter region of the NPN transistor.
A semiconductor integrated circuit device having a con-struction of complementary PNP-NPN semiconductor devices in a mono-lithic integrated form. First and second N type epitaxial layers are formed on a common P type semiconductor substrate. A base region of the PNP transistor is produced by the diffusion of an impurity into the second epitaxial layer. The NPN transistor is formed as low emitter concentration type transistor and a part of the second epitaxial layer serves as the transmitter region of the NPN transistor.
Description
1~48~55 B~CKGROUND OF THE INVENTION
Field of the Invention: -This invention relates generally to-a semiconductor device, and more particularly pertains to a semiconductor integrated circuit device having PNP type and NPN type transistor structures incorporated in a common semiconductor substrate.
`
Description of the Prior ~rt:
Generally, in a semlconductor integrated circuit~device containing complementary transistors or NPN type and PNP type tran-sistors, it is difficult to provide a so-called high property PNP
transistor which is high in withstanding voltage and high frequency characteristics as compared with an NPN type transistor. In othe~r words, such a semiconductor integrated circuit device having com-plementary transistors is constructed as shown in, for example, Figure 1. That is, a P type semiconductor substrate 1 is prepared, first and second N type epitaxial growth layers 2 and 3 are sequentially formed on the substrate 1, P type and N type layers are embedded in regions which are separated by P type isolation regions 4, thus a PNP type transistor PNP Tr having a collector 5, a base 6 and an emitter 7 is formed in one region and an NPN type transistor NPN Tr having a -collector 8, a base 9 and an emitter 10, respectively is formed in an~
other region. Further, in Figure l; Gl, Bl and El designate collector, base and emitter electrodes of the PNP type transistor PNP Tr, while C2, B2 and E2 indicate collector,base and emitter electrodes of the NPN
type transistor NPN Tr, respectively. However, in such a case where
Field of the Invention: -This invention relates generally to-a semiconductor device, and more particularly pertains to a semiconductor integrated circuit device having PNP type and NPN type transistor structures incorporated in a common semiconductor substrate.
`
Description of the Prior ~rt:
Generally, in a semlconductor integrated circuit~device containing complementary transistors or NPN type and PNP type tran-sistors, it is difficult to provide a so-called high property PNP
transistor which is high in withstanding voltage and high frequency characteristics as compared with an NPN type transistor. In othe~r words, such a semiconductor integrated circuit device having com-plementary transistors is constructed as shown in, for example, Figure 1. That is, a P type semiconductor substrate 1 is prepared, first and second N type epitaxial growth layers 2 and 3 are sequentially formed on the substrate 1, P type and N type layers are embedded in regions which are separated by P type isolation regions 4, thus a PNP type transistor PNP Tr having a collector 5, a base 6 and an emitter 7 is formed in one region and an NPN type transistor NPN Tr having a -collector 8, a base 9 and an emitter 10, respectively is formed in an~
other region. Further, in Figure l; Gl, Bl and El designate collector, base and emitter electrodes of the PNP type transistor PNP Tr, while C2, B2 and E2 indicate collector,base and emitter electrodes of the NPN
type transistor NPN Tr, respectively. However, in such a case where
2 ~ :
, :, ' : `' . - ' the PNP type transistor has the base region 6 made in the epitaxial grown layer, the base region 6 is low in impurity concentration, so that the current characteristic of itS current amplification factor hFE
is low. In order to improve such a defect, it is preferred that the impurity concentration profile of base and emitter regions of the PNP
type transistor be formed as a double diffusion-type. However, this is ~ -difficult in a semiconductor integrated circuit. Purther, since the emitter region 7 and collector region 5 of the PNP type transistor are high in impurity concentration while its base region 6 is low in impurity concentration, the depletion layer from a collector junction JC is expanded mainly to the base region 6 upon operation of the PNP type transistor PNP Tr, and hence its withstanding voltage is determined by punch-through and a high withstanding voltage transistor can not be formed.
It is sufficient for making the withstanding voltage of the transistor high, if the base width thereof is selected wide. However, since the frequency characteristic of the transistor is determined mainly by the base width, the withstanding voltage of the transistor can be improved only by causing its cut-off frequency fT to be deteriorated.
In order to avoid the deterioration of the cut-o~f frequency fT, it may be considered that an N type impurity of relatively high concentration is diffused into, for example, the base region 6 of low impurity concentra-tion to form a base region of high concentration and the base width is made narrow by carrying the emitter diffusion deep. However, in such a case, the collector region 5 is of high concentration, so that the withstanding voltage across the collector junction JC is deteriorated.
.
' SUMMARY OF THE lNVENTION
According to an aspect of the present invention, there is provided a semiconductor imegrated circuit device which comprises a semiconductor substrate of a first conductivity type, an epitaxial growth layer of a second conductivity type formed on said substrate, a first region of the first conductivity ~ype which faces the major surface of -said epitaxial growth layer; a second re~ion of the second conductivity type made of said epitaxial growth layer surrounded by sa~d first region, a diffusion region of the second conductivity type formed in said second region, a third region of the first conductivity type formed in said diffusion region, a fourth region of the second conductivity type made of said epitaxial growth layer which faces the surface of said epitaxial growth layer and is isolated through a PN junction from said first region, a fifth region of the first conductivity type ~ -formed in said fourth region, and a sixth region of the second conductivity type made of said epitaxial growth layer surrounded by said fifth region.
Accordingly~ it is an object of this invention to provide a semiconductor integrated circuit device which has provided with a PNP
type transistor high in withstandin~ voltage and good in current and frequency characteristics of current amplification factor hFE and a complementary transistor of high property.
It is another object of the invention to provide a semicon- -ductor integrated circuit device in which a low emitter concentration (LEC) transislor already developed as a complementary transistor by the .:
same applicant can be used.
.
,.1 - . : , ~ .. , 1~486SS
In accordance with the foregoing objects, there is provided: -a semiconductor integrated circuit having firstand second transistors of opposite conductivity type, comprising:
a. a semiconductor substrate of a first conductivity type:
b. an epitaxial layer formation of a second conductivity type and relatively low impurity concentration formed on said substrate and having a major face opposite the substrate;
c. said first transistor comprising:
i. a first region of first conductivity type in said epitaxial layer of formation spaced below said major face, and a conductive path region of first conductivity type and higher impurity concentra-tion than said first region extending from the first region up to the major face;
ii. a second region of second conductivity type being formed of said epitaxial layer formation and partially surrounded by said first region and conductive path region; and iii. a third region of first conductivity type formed in said second region~ spaced from said first ~--region by said second region;
d. an isolating PN junction between said first transistor and said second transistor said second transistor comprising:
i. a fourth region of second conductivety type formed of a portion of said epitaxial layer formation isolated from the first transistor by the isolating PN junction;
ii. a fifth region of first conductivity type spaced beIow said major face; and a conductive path region of first conductivity type ana -4a-1~486S5 higher impurity concentration than said fifth region from the fifth region up to the major face.
iii. a sixth region of second conductivity type being formed of said relatively low concentra-tion epitaxial layer formation and partially surrounded by said fifth region and conductive path region, said sixth region being spaced from said fourth region by said fifth region;
and iv. a seventh region of second conductivity type and concentration relatively higher than said sixth region formed in said sixth region and forming a low-high concentration barrier junction therewith, said junction being spaced from said fifth region by a distance less than the diffusion length of minority carriers in said sixth region injected from said fifth region when a forward bias is applied between said fifth and sixth regions;
whereby a first transistor is formed in an integrated circuit with a second transistor of low emitter ccncentration.
There is further provided: -A semiconductor integrated circuit having firs~and second transistors of opposite conductivity type, com-prising:
a. a semiconductor substrate of a first conductivity type: ~-b. an epitaxial layer formation of a second conductivity type and relatively low concentration formed on said substrate and having a major face opposite substrate;
-4b-. : . . : .
1~4~f~55 c. a first conductivity type isolation region in said epitaxial layer formation from said major face down to said substrate;
d. a first transistor formed on one side of said isolation region comprising;
i. a first embedded region of second conductivity type formed in said substrate, ii. a second embedded region of first conductivity type formed in said first embedded region and ~ . -extending upwardly in said epitaxial layer foxmation.
iii. a first region of first conductivity type formed in said epitaxial layer formation spaced below said major face in contact with said second embedded region, and a conductive path region of first conductivity type and higher impurity concentration than said first region from the first region up to the major face, iv, a second region of second conductivity type being formed of said epitaxial layer formation and partially surrounded by said first region and conductive path region, -v. a diffused region of second conductivity type and relatively higher concentration formed in ~:
said second region between said first region and major face; .
vi. a third region of first conductivity type formed in said diffusion region and spaced from said first region by said diffusion region, e. a second transistor formed on the other side of said isolation region comprising: .
i. a third embedded region of second conductivity type formed in said substrate, ~ -4c-```1~48655 ii. a fourth region of second conductivity type and lower concentration than said third embedded region formed by said epitaxial layer formation in contact with said third embedded regio~.
iii. a fifth region of first conductivity type in said ~ :
fourth region spaced below said epitaxial layer formation major face and a conductive path re-gion of first conductivity type and high `
impurity concentration than said fifth region from the fifth region up to the major face, iv. a sixth region of second conductivity type being -formed of said epitaxial layer formation of rela- -tively l~w concentration and partially surrounded by said fifth region and conductive path region, said sixth region being spaced from said fourth region by said fifth region and v. a seventh region of second conductivity type and concentration relatively higher than said sixth region formed in said sixth region and forming a low-high concentration barrier junction therewith, said junction being spaced from said fifth region by a distance less than the diffusion leng:th of minority carriers in said sixth region in-jected from said fifth region when a forward-bias is applied between said fifth and sixth ¦
reglons, whereby a first transistor of relatively high base concen-tration is formed with a second transistor of low emitter :
concentration. .
The other objects, features and advantages of th2 present __ .
'' .' -4d-~.~
.
.
1[)48655 invention will become apparent from the following description taken in conjunction with the accompanying drawings.
RIEF DESCRIPTION OF THE DRAWINGS
Figure:1 is a simplified cross-sectional view of one form ~f prior art complementary transistors.formed in a common sémicon-..
du.ctor substrate;
Figures 2 through~ 4, are cross-sectional views of LEC
transistors; ~ ~
Figures 5A through 5L are cross-sectional views of complementary transistors of the present invention at successive stages in the fabrication process thereof; and ......
Figures 6A through 6L, and Figures 7A through 7J are cross-sectional views of other type complementary transistors of the present invention at successive stages in the fabrication process thereof.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
For better understanding the present invention, a low emitter concentration (LEC) transistor will be described with reference to Figure 2. By way of example, an NPN type transistor will be described. An N type semiconductor substrate 11 of high impurity concentration is prepared, an N type semiconductor layer 12 of low impurity concentration is formed on the substrate 11 by epitaxial growth which is a first region. A second region 13 of a P type conductivity is formed adjacent to and surrounded by the first region 12. A third region 14 of an N type whose impurity concentratlon is substantially the ~ 048655 same as or sufficiently lower than that of the second region 13 is formed - -adjacent to and surrounded by the second region 13, and a potential barrier JE~ is formed in the third region 14 such that the barrier JB
opposes a PN junction J34 formed between the regions 14 and 13 and the distance between the barrier JB and the region 13 is selected smaller than the diffusion distance of minority carriers in the region 14. The potential barrier JB has, for example, the same conductivity type as that of the region 14, but an N type region 15 of impurity concentration - -sufficiently higher than that of the region 14 is formed therein to make an LH junction which is formed as the potential barrier. The term "LH junction" as used herein refers to the interface between a region of low impurity- concentration and a region of high impurity concentra-tlon of the same type. ~ ~ ~-Thus, an NPN type transistor is constructed whose emitter region is made of the region 14 and whose collector region is made of the region 12, respectively. In Figure 2, the numerals 16, 17 and 18 designate emitter, base and collector electrodes, respectively, and E, B and C designate terminals led out therefrom. If voltages are supplied to the electrodes 16, 17 and 18 to apply a forward bias to the PN junction between the regions 14 and 13, i. e., to the emitter junction J34 and to apply a backward bias to the PN junction between the regions 13 and 12, i.e., to collector junction J32~ the electrons injected from the emitter region 14 to the base region 13~ can reach the collector region 12 by selecting the distance be$ween the PN junctions J34 and J32 smaller than the diffusion length of minority carriers in the region 13.
Thus, the transistor operation can be performed. In this case, the ~ 048655 emitter injectlon efficiency ris expressed as follows:
_ majority carrier current in emitter Y majority carrier current in emitter +
minority carrier current in emitter Therefore, in order to increase the factor hFE or r. it is sufficient that if the carriers injected to the base or the current caused b3~ the diffusion of electrons is constant in Figure 2, the carrier injected from the region 13 to the emitter region 14 ,or hole current is decreased as much as possible. With the transistor shown in Figure 2, the barrier JB or LH junction exists in opposed relation to the PN junction J34 and the barrier JB will become a potential barrier of about 0. 2 e~l against the holes when the impùrity concentration in the low concentration part of the region 14 is selected as 1015 cm~3 and that in the region 15 is selected as 102 cm~3, by way of example. Thus, the minority carriers injected from the region 13 to the region 4 are repelled by the barrier JB' SO that the concentration gradient in the region 14 becomes flat and the injection of carriers (holes) from the region 13 to the region 14 is suppressed. As a result, the injection efficiency r is improved and hence the factor hFE becomes high. Further, since the mpurity concentration is selected low in the portion where the PN junctions ~o~, J34 and J32 which serve as emitter~junctions are formed, crystal defects are reduced and the factor hFE is sufficiently high as compared with that of an ordinary high concentration emitter type transistor.
In the example shown in Figure 2, the region 15 is formed in the third region 14 to provide the LH junction and hence the barrier JB therewith, but it is possible that, as shown in Figure 3, a fourth .
region 19 which is different in conductivity from the third region 14 is formed therein to provide a PN junction and hence the barrier JB In such a case, the minority carriers injected from the region 13 to the . .
region 14 moves to the region 19, the potential of the region 19 becomes approximately the same as that of the region 13, the concentration .
gradient of holes in the region 14 is made flat by re-injectlng holes from the region 19 to the region 14 to reduce the hole diffusion current, and hence the emitter injection efficiency r is enhanced to increase the FE
In the example shown in Figure 3, the region 19 is formed in the region 14 electrically isolated from the region 13, but it IS ~.
possible that, as shown in Figure 4, the region 19 be formed such that it is electrically connected in part to the region 13.
Since in Figures 3 and 4 the same reference numerals and letters as those of Figure 2 represent the same elements, their description will be omitted for the sake of .brevity.
In the semiconductor device of this invention which has complementary transistors, one of the complementary transistors or NPN type transistor is preferably formed as the above mentioned LEC ;
transistor.
With reference to Figure 5 or Figures 5A to 5L, an .
embodiment of the semiconductor.integrated circuit devices according to the present invention will be now described together with its manu-facture. In this example, an NPN type transistor is formed as a LEC
transistor.
Beginning with Figure 5A, a semiconductor substrate 21 of , ..
1~48655 a P type conductivity whose specific resistance is selected about 15 Q-cm (impurity concentration of 1X1015 cm 3) is prepared. Then, an embedded layer 22 of an N type conductivity whose impurity concentration is selected as, for example, about 5 x 1015 cm~3 is formed by diffusion in the substrate 21 from its one major surface at the position where a PNP type transistor will be formed later, while` an embedded layer 23 of an N type conductivity whose impurity concentration is selected as, for example, about 1 x 1019 cm~3 is formed by diffusion in the substrate 21 from the major surface thereof at the position where an NPN type tran- -sistor will be formed later (Figure 5B). In the figures, 24 andicates an insulating layer made, for example, of silicon dioxide Sib2.
Then, a diffusion window is formed.through thei SiO2 layer 24 on the N type embedded layer 22 by photo-etching the S~ layer- 24, and a P type impurity is diffused in the N type layer 22 thrd~gh the window to form a P type embedded layer 25 (whose impurity concentration is . selected, for example, about 1 x 1019 cm 3) which will serve as the collector embedded layer of the PNP type transistor (Figure 5C). There-after, a first epitaxial growth layer 26 whose specific resistance is selected as, for example, about 10 Q-cm is formed to cover all the upper surface of the substrate 21 (Figure 5D).
Then, a photo-etching treatment is carried out for the SiO2 layer 24 to form therethrough a diffusion window in a lattice pattern, which window will be used to form an isolation region of a lattice pattern viewed from the upper side, at the positions to isolate the parts where the PNP and NPN type transistors are to be formed. A P type impurity is diffused Ihrough the window into the substrate 21 through the epitaxial layer 26 to form P type isolation regions 27 (Figure 5E).
. . . - .
..
. - .~. ~. . ,. - . ., ., . ~ -.. - . . . .
A P type region 28, whose impurity concentration is lower - -than that of the P type embedded layer 25 or, for example, about 5 x 1015 cm~ 3, is formed by diffusion in one of the regions of the first epitaxial layer 26 isolated by the isolation region 27 or region 26A
where the PNP transistor is to be formed. In thls case, the P cype region 28 is selected to reach the P tyE~e embedded layer 25. Then, a P type region 29 is formed by, for example, the ion implantation in the other region ~ior region 26B where the NPN type transistor is to be formed. This P1 type region 29 finally serves as the base region of the NPN ~ransistor of an LEC type. Thereafter, a second epitaxial ; -growth layer 3~ of an N type is formed on the first epitaxial growth layer 26. In this case, the impurity concentration of the second epitaxial growth layer 30 is selected, for example, tO be about 5 x 1015 cm 3 (Refer to Figures 5F and 5G, respectively).
Then, a P type impurity of high concentration is selectively diffused in the second epitaxial growth layer 30 to form isolation regions 31 for isolating the parts where the PNP and NPN type transistors are to be formed. In this ca~e, the isolation regions 31 reach the isolation regions 27 in the lower layer. At the same time, P type regions 32 and 33, which are annular when viewed from the above, are formed in regions 30A and 30B of the second epitaxial growth layer 30 isolated by the isolation regions 31, respectively. The P type regions 32 and 33 are so formed that they reach the P type regions 28 and 29, respectively (Figure 5H).
An N type diffusion region 34, which will serve finally as the base region of the PNP type transistor, is formed in the N type region 30A of low impurity concentration which is formed of the second - , :, - :
~ 0486S5 epitaxial growth layer 30 and surrounded by the P type region 32. The N type diffusion region 34 contacts with the P type region 28 and has the impurity concentration higher than that of the P type region 28, for example, about 1 x 1018 cm~3 (Pigure 5I).
A P type region 35 of the impurity concentration of, for example, about 1 x 102 cm~3, which will serve as the emitter region of the PNP transistor, is formed in the N type diffusion region 34 (Figure 5J). Then, an N type impurity of high concentration is selectively diffused in the region 34 to form therein a high irnpurity concentration region 36 which serves for leading out the base electrode.
At the same time, an N type region 38 of high impurity concentration is formed in an N type low impurity concentration region 37 which exists in the region 30B made of the second epitaxial growth layer 30, is surrounded by the P type region 33 and will serve as the emitter region of the NPN transistor and a high impurity concentration region 39 of N type is also formed in the region 30B which is not surrounded by the P type re~ion 33. The region 39 will serve for leading out the collector electrode of the NPN transistor. In this case, the region 38 serves for deriving the emitter electrode as well as becomes an additional region which form an LH junction JB with the low concentration region 37. This LH junction JB acts as a potential barrier for the minority carriers in the region 37. Purther, the LH junction JB faces a junction Je formed be-tween the regions 37 and 29 and is formed at such a location that the distance between the junction JB and Je is smaller than the diffusion length of the minority carriers in the region 37 (Figure 5K).
Thereafter, collector, emitter and base electrodes Cl, E
... . .
1~48655 and B1 of the PNP transistor are formed on the regions 32, 35 and 36, respectively. Further, collector, base and emitter electrodes C2, B2 and E2 of the NPN transistor are formed on the regions 39, 33 and 38, respectively (Figure 5L).
Thus, as shown in Figure SL, in the first island region isolated by the isolation regions 27 and 31, there is formed the PNP
type transistor PNP Tr1 whose collector region is made of the P type regions 25 and 28, whose base region is made of the, N type diffusion region 34 and whose emitter region is made of the P t~ype region 35, while in the second isiand region there is formed the NPN transistor NPN Tr2 whose collector region is made of the N type regions 26B
and 30B which are formed in the first and second-epitaxial growth ~-layers, whose base region is formed by the P type region 29 which is formed by ion implantation, and whose emitter region is made of the N type low concentration region 37 which is formed in the second epitaxial growth layer and has the LH junction JB. Thus, a semicon-ductor integrated circuit device comprising desired complementary tran-sistors is obtained.
With the semiconductor integrated circuit device of the in-vention described above, the NPN type transistor, which is superior in withstanding voltage, current characteristic and high frequency char-acteristic of the factor hFE, and also the PNP type transistor, which is similarly superior in the same characteristics, are both obtained. That is, it is already known that an NPN transistor of high property is ob-tained, so that its description will be omitted. In the PNP transistor PNP Tr1, the P type region 28 made in the first epitaxial growth layer - .
. ~ . ~ ' ',, . ' ~
26 by low impurity concentration diffusion is used as the collector region of the PNP transistor, and the base region 34 and emitter region 35 thereof are formed in the second epitaxial growth layer 30 by a so-called double diffusion, so that the base width becomes narrow and hence a high cut-off frequency fT is obtained.- Thus, the PNP translstor is improved in high frequency characteristic and the current characteris-tic of its factor hFE. Accordingly, this PNP transistor can be used as a high power transistor. Since the collector region 28 contacting with the base region 34 is of low impurity concentration, the depl~etion layer of the collector junction JCl expands to the collector region 28 mainly.
Thus, a punch-through for the emitter region 35 is avoided, and accordingly, the withstanding voltage thereof is improved. If the PNP
transistor has the impurity concentration profile- of Figures 5A to 5L, its cut-off frequency fT can be made more than 100 MHz, its with-standing voltage more than 50 V, and its collector saturation resistance low.
In addition, the PNP transistor PNP Trl can coexist with the high property NPN translstor NPN Tr2 of the LEC type. At present, a desired semiconductor integrated circuit device including a LEC type NPN transistor requires two types of epitaxial growths, so that if the -PNP transistor PNP Trl of this invention is contained in the semicon- ~;
ductor integrated circuit device, there is no need to increase the number of epitaxial growth steps.
Although not shown, the P type region 28 of low Impurity concentration shown in ~igure 5 can be formed in such a manner that a P type impurity of high diffusion speed, for example, aluminum can be ... . ..
.~ . .
: -., ... . :
~ 04865S
diffused into the second epitaxial growth layer 30 from its surface after the first and second epitaxial growth layers 26 and 30 are formed. -In this case, a triple diffusion is carried out in consideration of the base region 34 and the emittèr region 35. - ~ -Another embodiment of the present invention will be described with reference to Figure 6 or Figures 6A to 6L, which are substantially the same as that of Figure 5 in construction but different in the method of making it.
As shown in Figure 6A, a P type semiconductor substrate 41 whose'specific resistance is selected as, for example, 3~5 S2-cm is prepared.
Then, an N type embedded layer 42, whose doping a-mounts to about 2 x 1012 cm 2, is formed for example, by ion implantation in the substrate 41 from its one major surface at the location where a PNP
type transistor will be formed later. In the figure, 43 indicates an insulating layer made, for example, of SiO2 (Figure 6B).
Thereafter, a P type region 44 of relatively high impurity concentration and a P type isolation region 45 of relatively high impurity concentration, which has a lattice shape when viewed from the upper side, are formed in the N type embedded region 42 and the substrate 41 at the positions for isolating PNP and NPN transistors, which will be formed finally, respectively. The P type region 44 will become the collector embedded layer of the PNP transistor. It is preferable that the sheet resistance ts of the P type region44-and P type isolation regions 45 be selected, for example, to be about 250 ~?/a (Figure 6C).
An N type embedded layer 46 of relatively high impurity concentration is formed by dif~usion in the substrate 41 at its part ''' ' - ~
~ 048~55 surrounded by the isolation regions 45 where the NPN transistor will be formed. At the same time, an N type region 47 for isolation is formed in the N type region 42 at the location to surround the P type region 44 (Figure 6D). It may be possible that the sheet resistance PS f the N type embedded layer 46 and the N type region 47 for isolatlon can be selected to be, for example, about 5 S~/a -Then, a first epitaxial growth layer 48 of P type, whosespecific resistance is, for example, about 5 ,52-cm and whose thickness is about 8 ~S (micron), and a second epitaxial growth layer 4~ of N type, whose specific resistance is, for example, 2 Q-cm and whose thickness is about 4,4, are formed sequentially-on the substrate 41 (Figure 6E).
A P type impurity of relatively high concentration is selectively diffused into the second epitaxial~ growth layer 49 from ies - -surface to form a P type region 50, which is annular when viewed from the upper side and reaches the first epitaxial growth layer 48, at the location opposing the P type region 44 and a P type isolation region 51 which is of lattice shape when viewed from the upper side and reaches the first epitaxial growth layer 48 at the location opposing the P type re-gion 45. At the same time, the N type embedded layer 46 and the N
type region 47 for isolation are again diffused and arrive at the second epitaxial growth layer 49 through the first epitaxial growth layer 48 (Figure 6F). -A P type region 52, which will serve as the base region of the NPN transistor, is formed by, for example, ion implantation (at a `
doping amount of, for example, about 1 x 1013 cm~2) in a region 49B
made of the second epitaxial growth layer 49 defined by the P type isola-tion region 51 (Figure 6G).
. . - , ' .
.: . . . . . .
. . . . .
Thereafter, a third epitaxial growth layer 53 of N type, whose specific resistance is selected to be about 2 52-cm, is formed on the second epitaxial growth layer 49 (Figure 6H).
Then, an N type diffusion region 5g, which will serve as the base region of the PNP transistor and reaches the first epitaxlal growth layer 48, is formed by selectively diffusing an N type impurity into the third epitaxial growth layer 53 from its surface at the location where the base region of the PNP transistor will be formed. An N type region 55, which surrounds the P type region 52 to be served as the base of the NPN transistor and is connected to the N type embedded layer 46, is formed by selective-ly diffusing an N type impurity into the third epitaxial growth 53 at the location where the collector region of the NPN tran-sistor will be formed. An N type isolation region 56 is formed by selectively- diffusing an N type impurity into the third epitaxial growth layer 53 at the location corresponding to the N type isolation region 47 to which the N type isolation region 56 reaches. In this case, it is possible that the sheet resistance ~S of the respective regions 54, 55 and 56 be selected as about 120 Q/L~ (Figure 6I). At this time, the regions 45 and Sl become connected to each other. -Then, a P type impurity is selectively diffused into the respective regions at high concentration to form a P type region 57 in the N type region 54 which region 57 will serve as the emitter region of the PNP transistor; a P type region 5~ of high concentration which is connected to the P type region 50 and will serve as the region for leading out the collector electrode of the PNP transistor; a P type re~on 59 of high concentration which will serve as the region for leading out the ~ al486SS
base electrode of the NPN transistor; and a P type isolation region 60 which is connected to the P type region 51. In this case, it is possible that the sheet resistance ~S of the respective regions 57, 58, 59 and 60 is selected as about 10 Q/o (Figure 6J).
An N type impurity of high concentration is selectively diffused to form an N type region 62 of high concentration In the N type region 61, which is made of the third epitaxial growth layer 3, will serve as the low emitter concentration region of the NPN transistor arrl -forms the LH junction with the region 62; an N type region 63 of high -concentration, which will serve for leading out the collector electrode ;
of the NPN transistor, in the N type region 55; an N type region 64 of high concentration, which will serve for leading out the base electrode of the PNP transistor, in the N type diffusion region 54 which will serve as the base region of the PNP transistor; and an N type region 65 of high concentration in the N type isolation region 56, which will serve for leading out the isolation electrode, respectively. In this case, it is possible that the sheet resistance ~S of the respective regions 62, 63, 64 and 65 can be selected as, for example, about 10 Q/~ (Figure : ~
6K)- : -Thereafter~ on the regions 57, 64 and 58, there are formed an emitter electrode El, a base electrode Bl and a collector electrode ;:~
Cl of the PNP transistor, respectively, while on the regions 62, 59 and 63, there are formed an emitter electrode E2, a base electrode B2 and a collector electrode C2 of the NPN transistor, respectively. Further, an electrode 66 for isolation is formed on the region 65 (Figure 6L).
Thus, as shown in Figure 6L, the PNP transistor PNP Tr ,. . : . . . :
, - . - , :.
~ 48655 is formed in the first island region defined by the embedded region 42 and the isolation regions 47 and 56, whose collector region is made of a P type region 48A consisting of the P type region 44 and the ffrst epitaxial growth layer 48, whose base region is made of the N type diffusion region 54 and whose emitter region is made o~ the P type region 57, while the NPN transistor NPN Tr2 of the LEC type is formed in the second island region defined by the P type isolation region.s 45, 51 and 60 whose collector region is made of a region 49B consisting of the second epitaxial growth layer 49, whose base region is made -of the .P type region 52 formed by the ion implantation and wh ose emitter region is made of the N ty~e region 61 of low concentration which consists of the .
third epitaxial growth layer 53 and forms the~~ junction JB~with the N
type region 62 of high impurity. That is, a semiconductor integrated circuit device is provided which has desired~complementary transistors.
The semiconductor device described immediately above is substantially the same as that described in connection with ~igures 5A
.
to 5L. That is, with the PNP transistor PNP Trl shown in Figure 6L, its collector region is made of the P type region 48A of low concentration of the first epitaxial layer 48 and the P type embedded region 44 of high concentration and its base and emitter regions 54 and ~7 are made by the double diffusion in the second and third epitaxial growth layers 49 and 53.
Accordingly, the PNP transistor PNP Trl is high in property, namely, its high frequency characteristic. and current characteristic of its current .
amplification factor hpE are improved and the withstanding voltage across . .
the collector junction thereof is made high. ~:
As to the manufacture of the semiconductor integrated circuit.
device showr~ in Figure 6, the P and N type epitaxial growth layers 48 and - ........ ........
~48655 49 are formed; the P type region 48A of low concentration and the P
type region 44 of high concentration, which serve as the collector region of the PNP transistor, the N type region 49B of low impurity and the N
type region 46 of high concentration which serve as the collector region of the PNP transistor, are formed by utilizlng the difference of the diffusion lengths of the P type region 44 of middle concentration, for example, 1017~1018 cm~3 and the N type region 46 of high concentra- ;-tion, for example, 102 cm 3, which were previously embedded Into the substrate 41, to the P type epitaxial growth layer 48; then the base region 52 of the NPN transistor is formed; the third epitaxial growth layer 53 of N type is formed; and thereafter the base and emitter diffu-sions of the PNP transistor are deeply carried out. Further, upon the ~ -process of the emitter diffusion of the PNP transistor, the diffusion of impurity at high concentration forming the region for leading out the base electrode of the NPN transistor is carried out at the same time.
Accordingly, such a semiconductor integrated circuit device can be made by a relatively small number of process steps.
Figure 7 or Figures 7A to 7J show a further embodimert of the present invention in which such a semiconductor integrated circuit device having an LEC type of PNP transistor, a PNP transistor and a resistor.
As shown in Figure 7A, a P type semiconductor substrate 71 whose specific resistance is selected, for example, to be in the order of 3 tO 5 ~?-cm is prepared. N type embedded layers 72 and 73, which are of high impurity concentration and have a sheet resistance ~S
of, for example, about 20 Qjo . are formed by diffusion on the substrate .
1~48655 71 from the surface thereof at the location where an NPN transistor must be formed later and at the common location where a PNP transistor :.
and a resistor must be formed later, respectively (Refer to Figure 7B).
In the figures, 74 indicates an insulating layer made of, for example, , si2 . ' - . .
Then, a P type isolation region 75 is formed in the.sub- .
strate 71 by diffusion for isolating the N type embedded layer~ 72 and 73 in such that it is shaped like a lattice when viewed from the upper side and its sheet resistance ~S is selected about 10 S2/n . Tihen, a first epitaxial' growth layer 76 of N type is .formed to cover all the substrate 71 whose specific resistance is selected, for example, about 4 to 7 52-cm (Figure 7D). In Figure 7D, 74' designates an insulating layer made, for example, of SiO2.
Thereafter, a P type impurity is selectively diffused into the .
N type epitaxial growth layer 76 to form therethrough a P type isolation region 77 at a location corresponding to the P type isolation region 75 which is connected to 77 through the layer 76, and at the same time a -- -P type region 78 which will serve as the collector region of a PNP
transistor to be formecl later (Figure 7E).
A P type region 79 is formed by diffusion in the N type epitaxial growth layer 76 at the location where the base region of an NPN transistor will be made, and at the same time or process a P
t~,pe region 80 is formed in the layer 76 by diffusion at the location where a resistor is to be formed later. In this case, the regions 79 and 80 can ~e selected to have a sheet resistance of 1000 52/~ (Figure 7F).
: :
10~865S
Thereafter, a second N type epitaxial growth layer 81 of the N type is formed on the N type epitaxial growth layer 76 (Figure :
7G). :
A P type impurity is, then, diffused into the second N type epitaxial growth layer 81 selectively to form a P type isolation region 82 which is connected to the isolation region 77; a P type region. 83, ~ :
which is connected to the P type region 79 and will serve as part of the base region of the NPN transistor; a P type region 84, which is connected to-the P type region 78 and will serve as a part of the collector region of the PNP transistor; and P type regions 85A and 85B which are - ~ -connected to both ends of the P type region 80, which will be a resistor ~:
body, respectively (Figure 7H).
An N type impurity is selectively diffused into the P type second epitaxial layer 81 (whose sheet resistance is selected to be ~
about 100 Q/D ) ~0 form an N type region 88 of high concentratlon at :
the position, which will become the collector of the NPN transistor, for leading out its collector electrode; an N type region 87 of high concen- :
tration in an N type region 86, which will serve as the low concentra- - -tion emitter, is surralnded by the base region 83 and forms an LH
junction JB with the N type region 87; an N type region 90 of high concentration in the region which will become the base of the PNP
transistor to provide an N type region 89 of low concentration between the region 90 and ~he P type region 7g which will become the collector of the PNP transistor; and an N type region 91 of high concentration in the N type region defined by the P type isolation region 82 and at the -side where the PNP transistor and resistor are provided, which region 91 serves for the electrode severing as isolation, respectively (Figure 7I). - :
~ . . . ~ . . .
1~486SS
A P type impurity is selectively diffused at high concentra-tion into the second epitaxial growth layer 81 (with a sheet resistance of about 10 S2/n ) to form a P type region 92 of high concentration on ~-the region 83, which will serve for deriving the base electrode of the NPN transistor; a P type region 93 of high concentration on the re~;Lon 90, which will become the emitter of the PNP transistor; a P type region 94 of high concentration on the region 84, wh'ich will serve for deriving the collector electrode of the PNP transistor; and P type regions 95A and 95B
of high concentration on the regions 85A and 85B, which will serve for deriving the electrodes of the P type region 80 which will become the resistor.
Thereafter, an emitter electrode E2, a base electrode B2 and a collector electrode C2 of the NPN transistor are formed on the regions 87, 92 and 88; an emitter elect:~de-El, a base electrode Bi and a collector electrode Cl of the PNP transistor are formed on the -regions 93, 90 and 94; a pair of electrodes Rl and R2 are formed on the regions 95A and 95B; and an electrode 96 is formed on the region 91, respectively.
Thus, as shown in Figure 7J, a semiconductor integrated circuit device is provided. In this case, it has an NPN transistor NPN Tr2 of LEC type whose collector region is made of parts of the first and second epitaxial growth layers 76 and 81 which is surrounded by the P
type isolation regions 82 and 77, whose base region is made of the P type region 79 and whose emitter region is made of the N type region 86 of low concentration which consists of the second epitaxial growth layer 81 and forms an LH junction JB with the N type region 87 of high concen-tration; a PNP transistor PNP Trl whose collector region is made of the 1C~4~3~55 P type region 78, whose base region is made of the N type region 89 of low concentration consisting of the second epitaxial growth layer 81 and the N type diffusion region 90 of high concentration and whose emitter region is made of the P type diffusion region 93 of high concentration;
and a resistor R is made of the P type region 80, respectively.
According to the semiconductor integrated circult devlce of the invention described just above, a PNP transistor of high property is obtained, together with an NPN transistor of high property similar to those shown in Figures 5 and 6. That is, ~although a description on the NPN transistor will be omitted, the base region 90 and emitter region 93 of the PNP transistor PNP Tr1 are formed by double diffusions into the second epitaxial growth layer 81, so that its high frequency characteristic and the current characteristic of its factor hFE are improved. Further, since the base region of the PNP transistor, which contacts with its collector region, is made of the region 89 of low concentration consisting of the second epitaxial growth layer 81, its withstanding voltage across the collector junction is improved. In addi- :
tion, the part of the base region apart from the collector junction consists of the region 90 of high concentration, so that the punch-through upon the operation can be avoided to increase its withstanding voltage.
As described in the foregGing, with the semiconductor integrated circuit device of the present invention, it has provided with the PNP transistor of high property or of high withstanding voltage and superior in high frequency and current characteristics as well as the NPN transistor of LEC type and hence good complementary transistors.
Further, with the present invention, since the PNP transis- -tor PNP Tr1 coexists with the NPN transistor NPN Tr2 of LEC type, it 1~4865S :
is easy to introduce an LEC transistor imo a semiconductor integrated ci rcuit devi ce.
The foregoing description is given on the case that the NPN
transistor is made as an LEC type, but it is also possible that an ordinary-NPN transistor with the emitter of high COnCentraliOn be used as the NPN transistor of the invention.
Further, the NPI\l transistors formed in the examples shown in Figures 5 to 7 include the LH junction, but they can be made to have the form of the construction shown in Figures 3 and 4.
lt will be apparent to those skilled in the art that many modifications and valiations may be effected without departin~ from the spirit and scope of the novel concepts of the present invention.
~,r* ~ 2 4 ~
~1~
, :, ' : `' . - ' the PNP type transistor has the base region 6 made in the epitaxial grown layer, the base region 6 is low in impurity concentration, so that the current characteristic of itS current amplification factor hFE
is low. In order to improve such a defect, it is preferred that the impurity concentration profile of base and emitter regions of the PNP
type transistor be formed as a double diffusion-type. However, this is ~ -difficult in a semiconductor integrated circuit. Purther, since the emitter region 7 and collector region 5 of the PNP type transistor are high in impurity concentration while its base region 6 is low in impurity concentration, the depletion layer from a collector junction JC is expanded mainly to the base region 6 upon operation of the PNP type transistor PNP Tr, and hence its withstanding voltage is determined by punch-through and a high withstanding voltage transistor can not be formed.
It is sufficient for making the withstanding voltage of the transistor high, if the base width thereof is selected wide. However, since the frequency characteristic of the transistor is determined mainly by the base width, the withstanding voltage of the transistor can be improved only by causing its cut-off frequency fT to be deteriorated.
In order to avoid the deterioration of the cut-o~f frequency fT, it may be considered that an N type impurity of relatively high concentration is diffused into, for example, the base region 6 of low impurity concentra-tion to form a base region of high concentration and the base width is made narrow by carrying the emitter diffusion deep. However, in such a case, the collector region 5 is of high concentration, so that the withstanding voltage across the collector junction JC is deteriorated.
.
' SUMMARY OF THE lNVENTION
According to an aspect of the present invention, there is provided a semiconductor imegrated circuit device which comprises a semiconductor substrate of a first conductivity type, an epitaxial growth layer of a second conductivity type formed on said substrate, a first region of the first conductivity ~ype which faces the major surface of -said epitaxial growth layer; a second re~ion of the second conductivity type made of said epitaxial growth layer surrounded by sa~d first region, a diffusion region of the second conductivity type formed in said second region, a third region of the first conductivity type formed in said diffusion region, a fourth region of the second conductivity type made of said epitaxial growth layer which faces the surface of said epitaxial growth layer and is isolated through a PN junction from said first region, a fifth region of the first conductivity type ~ -formed in said fourth region, and a sixth region of the second conductivity type made of said epitaxial growth layer surrounded by said fifth region.
Accordingly~ it is an object of this invention to provide a semiconductor integrated circuit device which has provided with a PNP
type transistor high in withstandin~ voltage and good in current and frequency characteristics of current amplification factor hFE and a complementary transistor of high property.
It is another object of the invention to provide a semicon- -ductor integrated circuit device in which a low emitter concentration (LEC) transislor already developed as a complementary transistor by the .:
same applicant can be used.
.
,.1 - . : , ~ .. , 1~486SS
In accordance with the foregoing objects, there is provided: -a semiconductor integrated circuit having firstand second transistors of opposite conductivity type, comprising:
a. a semiconductor substrate of a first conductivity type:
b. an epitaxial layer formation of a second conductivity type and relatively low impurity concentration formed on said substrate and having a major face opposite the substrate;
c. said first transistor comprising:
i. a first region of first conductivity type in said epitaxial layer of formation spaced below said major face, and a conductive path region of first conductivity type and higher impurity concentra-tion than said first region extending from the first region up to the major face;
ii. a second region of second conductivity type being formed of said epitaxial layer formation and partially surrounded by said first region and conductive path region; and iii. a third region of first conductivity type formed in said second region~ spaced from said first ~--region by said second region;
d. an isolating PN junction between said first transistor and said second transistor said second transistor comprising:
i. a fourth region of second conductivety type formed of a portion of said epitaxial layer formation isolated from the first transistor by the isolating PN junction;
ii. a fifth region of first conductivity type spaced beIow said major face; and a conductive path region of first conductivity type ana -4a-1~486S5 higher impurity concentration than said fifth region from the fifth region up to the major face.
iii. a sixth region of second conductivity type being formed of said relatively low concentra-tion epitaxial layer formation and partially surrounded by said fifth region and conductive path region, said sixth region being spaced from said fourth region by said fifth region;
and iv. a seventh region of second conductivity type and concentration relatively higher than said sixth region formed in said sixth region and forming a low-high concentration barrier junction therewith, said junction being spaced from said fifth region by a distance less than the diffusion length of minority carriers in said sixth region injected from said fifth region when a forward bias is applied between said fifth and sixth regions;
whereby a first transistor is formed in an integrated circuit with a second transistor of low emitter ccncentration.
There is further provided: -A semiconductor integrated circuit having firs~and second transistors of opposite conductivity type, com-prising:
a. a semiconductor substrate of a first conductivity type: ~-b. an epitaxial layer formation of a second conductivity type and relatively low concentration formed on said substrate and having a major face opposite substrate;
-4b-. : . . : .
1~4~f~55 c. a first conductivity type isolation region in said epitaxial layer formation from said major face down to said substrate;
d. a first transistor formed on one side of said isolation region comprising;
i. a first embedded region of second conductivity type formed in said substrate, ii. a second embedded region of first conductivity type formed in said first embedded region and ~ . -extending upwardly in said epitaxial layer foxmation.
iii. a first region of first conductivity type formed in said epitaxial layer formation spaced below said major face in contact with said second embedded region, and a conductive path region of first conductivity type and higher impurity concentration than said first region from the first region up to the major face, iv, a second region of second conductivity type being formed of said epitaxial layer formation and partially surrounded by said first region and conductive path region, -v. a diffused region of second conductivity type and relatively higher concentration formed in ~:
said second region between said first region and major face; .
vi. a third region of first conductivity type formed in said diffusion region and spaced from said first region by said diffusion region, e. a second transistor formed on the other side of said isolation region comprising: .
i. a third embedded region of second conductivity type formed in said substrate, ~ -4c-```1~48655 ii. a fourth region of second conductivity type and lower concentration than said third embedded region formed by said epitaxial layer formation in contact with said third embedded regio~.
iii. a fifth region of first conductivity type in said ~ :
fourth region spaced below said epitaxial layer formation major face and a conductive path re-gion of first conductivity type and high `
impurity concentration than said fifth region from the fifth region up to the major face, iv. a sixth region of second conductivity type being -formed of said epitaxial layer formation of rela- -tively l~w concentration and partially surrounded by said fifth region and conductive path region, said sixth region being spaced from said fourth region by said fifth region and v. a seventh region of second conductivity type and concentration relatively higher than said sixth region formed in said sixth region and forming a low-high concentration barrier junction therewith, said junction being spaced from said fifth region by a distance less than the diffusion leng:th of minority carriers in said sixth region in-jected from said fifth region when a forward-bias is applied between said fifth and sixth ¦
reglons, whereby a first transistor of relatively high base concen-tration is formed with a second transistor of low emitter :
concentration. .
The other objects, features and advantages of th2 present __ .
'' .' -4d-~.~
.
.
1[)48655 invention will become apparent from the following description taken in conjunction with the accompanying drawings.
RIEF DESCRIPTION OF THE DRAWINGS
Figure:1 is a simplified cross-sectional view of one form ~f prior art complementary transistors.formed in a common sémicon-..
du.ctor substrate;
Figures 2 through~ 4, are cross-sectional views of LEC
transistors; ~ ~
Figures 5A through 5L are cross-sectional views of complementary transistors of the present invention at successive stages in the fabrication process thereof; and ......
Figures 6A through 6L, and Figures 7A through 7J are cross-sectional views of other type complementary transistors of the present invention at successive stages in the fabrication process thereof.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
For better understanding the present invention, a low emitter concentration (LEC) transistor will be described with reference to Figure 2. By way of example, an NPN type transistor will be described. An N type semiconductor substrate 11 of high impurity concentration is prepared, an N type semiconductor layer 12 of low impurity concentration is formed on the substrate 11 by epitaxial growth which is a first region. A second region 13 of a P type conductivity is formed adjacent to and surrounded by the first region 12. A third region 14 of an N type whose impurity concentratlon is substantially the ~ 048655 same as or sufficiently lower than that of the second region 13 is formed - -adjacent to and surrounded by the second region 13, and a potential barrier JE~ is formed in the third region 14 such that the barrier JB
opposes a PN junction J34 formed between the regions 14 and 13 and the distance between the barrier JB and the region 13 is selected smaller than the diffusion distance of minority carriers in the region 14. The potential barrier JB has, for example, the same conductivity type as that of the region 14, but an N type region 15 of impurity concentration - -sufficiently higher than that of the region 14 is formed therein to make an LH junction which is formed as the potential barrier. The term "LH junction" as used herein refers to the interface between a region of low impurity- concentration and a region of high impurity concentra-tlon of the same type. ~ ~ ~-Thus, an NPN type transistor is constructed whose emitter region is made of the region 14 and whose collector region is made of the region 12, respectively. In Figure 2, the numerals 16, 17 and 18 designate emitter, base and collector electrodes, respectively, and E, B and C designate terminals led out therefrom. If voltages are supplied to the electrodes 16, 17 and 18 to apply a forward bias to the PN junction between the regions 14 and 13, i. e., to the emitter junction J34 and to apply a backward bias to the PN junction between the regions 13 and 12, i.e., to collector junction J32~ the electrons injected from the emitter region 14 to the base region 13~ can reach the collector region 12 by selecting the distance be$ween the PN junctions J34 and J32 smaller than the diffusion length of minority carriers in the region 13.
Thus, the transistor operation can be performed. In this case, the ~ 048655 emitter injectlon efficiency ris expressed as follows:
_ majority carrier current in emitter Y majority carrier current in emitter +
minority carrier current in emitter Therefore, in order to increase the factor hFE or r. it is sufficient that if the carriers injected to the base or the current caused b3~ the diffusion of electrons is constant in Figure 2, the carrier injected from the region 13 to the emitter region 14 ,or hole current is decreased as much as possible. With the transistor shown in Figure 2, the barrier JB or LH junction exists in opposed relation to the PN junction J34 and the barrier JB will become a potential barrier of about 0. 2 e~l against the holes when the impùrity concentration in the low concentration part of the region 14 is selected as 1015 cm~3 and that in the region 15 is selected as 102 cm~3, by way of example. Thus, the minority carriers injected from the region 13 to the region 4 are repelled by the barrier JB' SO that the concentration gradient in the region 14 becomes flat and the injection of carriers (holes) from the region 13 to the region 14 is suppressed. As a result, the injection efficiency r is improved and hence the factor hFE becomes high. Further, since the mpurity concentration is selected low in the portion where the PN junctions ~o~, J34 and J32 which serve as emitter~junctions are formed, crystal defects are reduced and the factor hFE is sufficiently high as compared with that of an ordinary high concentration emitter type transistor.
In the example shown in Figure 2, the region 15 is formed in the third region 14 to provide the LH junction and hence the barrier JB therewith, but it is possible that, as shown in Figure 3, a fourth .
region 19 which is different in conductivity from the third region 14 is formed therein to provide a PN junction and hence the barrier JB In such a case, the minority carriers injected from the region 13 to the . .
region 14 moves to the region 19, the potential of the region 19 becomes approximately the same as that of the region 13, the concentration .
gradient of holes in the region 14 is made flat by re-injectlng holes from the region 19 to the region 14 to reduce the hole diffusion current, and hence the emitter injection efficiency r is enhanced to increase the FE
In the example shown in Figure 3, the region 19 is formed in the region 14 electrically isolated from the region 13, but it IS ~.
possible that, as shown in Figure 4, the region 19 be formed such that it is electrically connected in part to the region 13.
Since in Figures 3 and 4 the same reference numerals and letters as those of Figure 2 represent the same elements, their description will be omitted for the sake of .brevity.
In the semiconductor device of this invention which has complementary transistors, one of the complementary transistors or NPN type transistor is preferably formed as the above mentioned LEC ;
transistor.
With reference to Figure 5 or Figures 5A to 5L, an .
embodiment of the semiconductor.integrated circuit devices according to the present invention will be now described together with its manu-facture. In this example, an NPN type transistor is formed as a LEC
transistor.
Beginning with Figure 5A, a semiconductor substrate 21 of , ..
1~48655 a P type conductivity whose specific resistance is selected about 15 Q-cm (impurity concentration of 1X1015 cm 3) is prepared. Then, an embedded layer 22 of an N type conductivity whose impurity concentration is selected as, for example, about 5 x 1015 cm~3 is formed by diffusion in the substrate 21 from its one major surface at the position where a PNP type transistor will be formed later, while` an embedded layer 23 of an N type conductivity whose impurity concentration is selected as, for example, about 1 x 1019 cm~3 is formed by diffusion in the substrate 21 from the major surface thereof at the position where an NPN type tran- -sistor will be formed later (Figure 5B). In the figures, 24 andicates an insulating layer made, for example, of silicon dioxide Sib2.
Then, a diffusion window is formed.through thei SiO2 layer 24 on the N type embedded layer 22 by photo-etching the S~ layer- 24, and a P type impurity is diffused in the N type layer 22 thrd~gh the window to form a P type embedded layer 25 (whose impurity concentration is . selected, for example, about 1 x 1019 cm 3) which will serve as the collector embedded layer of the PNP type transistor (Figure 5C). There-after, a first epitaxial growth layer 26 whose specific resistance is selected as, for example, about 10 Q-cm is formed to cover all the upper surface of the substrate 21 (Figure 5D).
Then, a photo-etching treatment is carried out for the SiO2 layer 24 to form therethrough a diffusion window in a lattice pattern, which window will be used to form an isolation region of a lattice pattern viewed from the upper side, at the positions to isolate the parts where the PNP and NPN type transistors are to be formed. A P type impurity is diffused Ihrough the window into the substrate 21 through the epitaxial layer 26 to form P type isolation regions 27 (Figure 5E).
. . . - .
..
. - .~. ~. . ,. - . ., ., . ~ -.. - . . . .
A P type region 28, whose impurity concentration is lower - -than that of the P type embedded layer 25 or, for example, about 5 x 1015 cm~ 3, is formed by diffusion in one of the regions of the first epitaxial layer 26 isolated by the isolation region 27 or region 26A
where the PNP transistor is to be formed. In thls case, the P cype region 28 is selected to reach the P tyE~e embedded layer 25. Then, a P type region 29 is formed by, for example, the ion implantation in the other region ~ior region 26B where the NPN type transistor is to be formed. This P1 type region 29 finally serves as the base region of the NPN ~ransistor of an LEC type. Thereafter, a second epitaxial ; -growth layer 3~ of an N type is formed on the first epitaxial growth layer 26. In this case, the impurity concentration of the second epitaxial growth layer 30 is selected, for example, tO be about 5 x 1015 cm 3 (Refer to Figures 5F and 5G, respectively).
Then, a P type impurity of high concentration is selectively diffused in the second epitaxial growth layer 30 to form isolation regions 31 for isolating the parts where the PNP and NPN type transistors are to be formed. In this ca~e, the isolation regions 31 reach the isolation regions 27 in the lower layer. At the same time, P type regions 32 and 33, which are annular when viewed from the above, are formed in regions 30A and 30B of the second epitaxial growth layer 30 isolated by the isolation regions 31, respectively. The P type regions 32 and 33 are so formed that they reach the P type regions 28 and 29, respectively (Figure 5H).
An N type diffusion region 34, which will serve finally as the base region of the PNP type transistor, is formed in the N type region 30A of low impurity concentration which is formed of the second - , :, - :
~ 0486S5 epitaxial growth layer 30 and surrounded by the P type region 32. The N type diffusion region 34 contacts with the P type region 28 and has the impurity concentration higher than that of the P type region 28, for example, about 1 x 1018 cm~3 (Pigure 5I).
A P type region 35 of the impurity concentration of, for example, about 1 x 102 cm~3, which will serve as the emitter region of the PNP transistor, is formed in the N type diffusion region 34 (Figure 5J). Then, an N type impurity of high concentration is selectively diffused in the region 34 to form therein a high irnpurity concentration region 36 which serves for leading out the base electrode.
At the same time, an N type region 38 of high impurity concentration is formed in an N type low impurity concentration region 37 which exists in the region 30B made of the second epitaxial growth layer 30, is surrounded by the P type region 33 and will serve as the emitter region of the NPN transistor and a high impurity concentration region 39 of N type is also formed in the region 30B which is not surrounded by the P type re~ion 33. The region 39 will serve for leading out the collector electrode of the NPN transistor. In this case, the region 38 serves for deriving the emitter electrode as well as becomes an additional region which form an LH junction JB with the low concentration region 37. This LH junction JB acts as a potential barrier for the minority carriers in the region 37. Purther, the LH junction JB faces a junction Je formed be-tween the regions 37 and 29 and is formed at such a location that the distance between the junction JB and Je is smaller than the diffusion length of the minority carriers in the region 37 (Figure 5K).
Thereafter, collector, emitter and base electrodes Cl, E
... . .
1~48655 and B1 of the PNP transistor are formed on the regions 32, 35 and 36, respectively. Further, collector, base and emitter electrodes C2, B2 and E2 of the NPN transistor are formed on the regions 39, 33 and 38, respectively (Figure 5L).
Thus, as shown in Figure SL, in the first island region isolated by the isolation regions 27 and 31, there is formed the PNP
type transistor PNP Tr1 whose collector region is made of the P type regions 25 and 28, whose base region is made of the, N type diffusion region 34 and whose emitter region is made of the P t~ype region 35, while in the second isiand region there is formed the NPN transistor NPN Tr2 whose collector region is made of the N type regions 26B
and 30B which are formed in the first and second-epitaxial growth ~-layers, whose base region is formed by the P type region 29 which is formed by ion implantation, and whose emitter region is made of the N type low concentration region 37 which is formed in the second epitaxial growth layer and has the LH junction JB. Thus, a semicon-ductor integrated circuit device comprising desired complementary tran-sistors is obtained.
With the semiconductor integrated circuit device of the in-vention described above, the NPN type transistor, which is superior in withstanding voltage, current characteristic and high frequency char-acteristic of the factor hFE, and also the PNP type transistor, which is similarly superior in the same characteristics, are both obtained. That is, it is already known that an NPN transistor of high property is ob-tained, so that its description will be omitted. In the PNP transistor PNP Tr1, the P type region 28 made in the first epitaxial growth layer - .
. ~ . ~ ' ',, . ' ~
26 by low impurity concentration diffusion is used as the collector region of the PNP transistor, and the base region 34 and emitter region 35 thereof are formed in the second epitaxial growth layer 30 by a so-called double diffusion, so that the base width becomes narrow and hence a high cut-off frequency fT is obtained.- Thus, the PNP translstor is improved in high frequency characteristic and the current characteris-tic of its factor hFE. Accordingly, this PNP transistor can be used as a high power transistor. Since the collector region 28 contacting with the base region 34 is of low impurity concentration, the depl~etion layer of the collector junction JCl expands to the collector region 28 mainly.
Thus, a punch-through for the emitter region 35 is avoided, and accordingly, the withstanding voltage thereof is improved. If the PNP
transistor has the impurity concentration profile- of Figures 5A to 5L, its cut-off frequency fT can be made more than 100 MHz, its with-standing voltage more than 50 V, and its collector saturation resistance low.
In addition, the PNP transistor PNP Trl can coexist with the high property NPN translstor NPN Tr2 of the LEC type. At present, a desired semiconductor integrated circuit device including a LEC type NPN transistor requires two types of epitaxial growths, so that if the -PNP transistor PNP Trl of this invention is contained in the semicon- ~;
ductor integrated circuit device, there is no need to increase the number of epitaxial growth steps.
Although not shown, the P type region 28 of low Impurity concentration shown in ~igure 5 can be formed in such a manner that a P type impurity of high diffusion speed, for example, aluminum can be ... . ..
.~ . .
: -., ... . :
~ 04865S
diffused into the second epitaxial growth layer 30 from its surface after the first and second epitaxial growth layers 26 and 30 are formed. -In this case, a triple diffusion is carried out in consideration of the base region 34 and the emittèr region 35. - ~ -Another embodiment of the present invention will be described with reference to Figure 6 or Figures 6A to 6L, which are substantially the same as that of Figure 5 in construction but different in the method of making it.
As shown in Figure 6A, a P type semiconductor substrate 41 whose'specific resistance is selected as, for example, 3~5 S2-cm is prepared.
Then, an N type embedded layer 42, whose doping a-mounts to about 2 x 1012 cm 2, is formed for example, by ion implantation in the substrate 41 from its one major surface at the location where a PNP
type transistor will be formed later. In the figure, 43 indicates an insulating layer made, for example, of SiO2 (Figure 6B).
Thereafter, a P type region 44 of relatively high impurity concentration and a P type isolation region 45 of relatively high impurity concentration, which has a lattice shape when viewed from the upper side, are formed in the N type embedded region 42 and the substrate 41 at the positions for isolating PNP and NPN transistors, which will be formed finally, respectively. The P type region 44 will become the collector embedded layer of the PNP transistor. It is preferable that the sheet resistance ts of the P type region44-and P type isolation regions 45 be selected, for example, to be about 250 ~?/a (Figure 6C).
An N type embedded layer 46 of relatively high impurity concentration is formed by dif~usion in the substrate 41 at its part ''' ' - ~
~ 048~55 surrounded by the isolation regions 45 where the NPN transistor will be formed. At the same time, an N type region 47 for isolation is formed in the N type region 42 at the location to surround the P type region 44 (Figure 6D). It may be possible that the sheet resistance PS f the N type embedded layer 46 and the N type region 47 for isolatlon can be selected to be, for example, about 5 S~/a -Then, a first epitaxial growth layer 48 of P type, whosespecific resistance is, for example, about 5 ,52-cm and whose thickness is about 8 ~S (micron), and a second epitaxial growth layer 4~ of N type, whose specific resistance is, for example, 2 Q-cm and whose thickness is about 4,4, are formed sequentially-on the substrate 41 (Figure 6E).
A P type impurity of relatively high concentration is selectively diffused into the second epitaxial~ growth layer 49 from ies - -surface to form a P type region 50, which is annular when viewed from the upper side and reaches the first epitaxial growth layer 48, at the location opposing the P type region 44 and a P type isolation region 51 which is of lattice shape when viewed from the upper side and reaches the first epitaxial growth layer 48 at the location opposing the P type re-gion 45. At the same time, the N type embedded layer 46 and the N
type region 47 for isolation are again diffused and arrive at the second epitaxial growth layer 49 through the first epitaxial growth layer 48 (Figure 6F). -A P type region 52, which will serve as the base region of the NPN transistor, is formed by, for example, ion implantation (at a `
doping amount of, for example, about 1 x 1013 cm~2) in a region 49B
made of the second epitaxial growth layer 49 defined by the P type isola-tion region 51 (Figure 6G).
. . - , ' .
.: . . . . . .
. . . . .
Thereafter, a third epitaxial growth layer 53 of N type, whose specific resistance is selected to be about 2 52-cm, is formed on the second epitaxial growth layer 49 (Figure 6H).
Then, an N type diffusion region 5g, which will serve as the base region of the PNP transistor and reaches the first epitaxlal growth layer 48, is formed by selectively diffusing an N type impurity into the third epitaxial growth layer 53 from its surface at the location where the base region of the PNP transistor will be formed. An N type region 55, which surrounds the P type region 52 to be served as the base of the NPN transistor and is connected to the N type embedded layer 46, is formed by selective-ly diffusing an N type impurity into the third epitaxial growth 53 at the location where the collector region of the NPN tran-sistor will be formed. An N type isolation region 56 is formed by selectively- diffusing an N type impurity into the third epitaxial growth layer 53 at the location corresponding to the N type isolation region 47 to which the N type isolation region 56 reaches. In this case, it is possible that the sheet resistance ~S of the respective regions 54, 55 and 56 be selected as about 120 Q/L~ (Figure 6I). At this time, the regions 45 and Sl become connected to each other. -Then, a P type impurity is selectively diffused into the respective regions at high concentration to form a P type region 57 in the N type region 54 which region 57 will serve as the emitter region of the PNP transistor; a P type region 5~ of high concentration which is connected to the P type region 50 and will serve as the region for leading out the collector electrode of the PNP transistor; a P type re~on 59 of high concentration which will serve as the region for leading out the ~ al486SS
base electrode of the NPN transistor; and a P type isolation region 60 which is connected to the P type region 51. In this case, it is possible that the sheet resistance ~S of the respective regions 57, 58, 59 and 60 is selected as about 10 Q/o (Figure 6J).
An N type impurity of high concentration is selectively diffused to form an N type region 62 of high concentration In the N type region 61, which is made of the third epitaxial growth layer 3, will serve as the low emitter concentration region of the NPN transistor arrl -forms the LH junction with the region 62; an N type region 63 of high -concentration, which will serve for leading out the collector electrode ;
of the NPN transistor, in the N type region 55; an N type region 64 of high concentration, which will serve for leading out the base electrode of the PNP transistor, in the N type diffusion region 54 which will serve as the base region of the PNP transistor; and an N type region 65 of high concentration in the N type isolation region 56, which will serve for leading out the isolation electrode, respectively. In this case, it is possible that the sheet resistance ~S of the respective regions 62, 63, 64 and 65 can be selected as, for example, about 10 Q/~ (Figure : ~
6K)- : -Thereafter~ on the regions 57, 64 and 58, there are formed an emitter electrode El, a base electrode Bl and a collector electrode ;:~
Cl of the PNP transistor, respectively, while on the regions 62, 59 and 63, there are formed an emitter electrode E2, a base electrode B2 and a collector electrode C2 of the NPN transistor, respectively. Further, an electrode 66 for isolation is formed on the region 65 (Figure 6L).
Thus, as shown in Figure 6L, the PNP transistor PNP Tr ,. . : . . . :
, - . - , :.
~ 48655 is formed in the first island region defined by the embedded region 42 and the isolation regions 47 and 56, whose collector region is made of a P type region 48A consisting of the P type region 44 and the ffrst epitaxial growth layer 48, whose base region is made of the N type diffusion region 54 and whose emitter region is made o~ the P type region 57, while the NPN transistor NPN Tr2 of the LEC type is formed in the second island region defined by the P type isolation region.s 45, 51 and 60 whose collector region is made of a region 49B consisting of the second epitaxial growth layer 49, whose base region is made -of the .P type region 52 formed by the ion implantation and wh ose emitter region is made of the N ty~e region 61 of low concentration which consists of the .
third epitaxial growth layer 53 and forms the~~ junction JB~with the N
type region 62 of high impurity. That is, a semiconductor integrated circuit device is provided which has desired~complementary transistors.
The semiconductor device described immediately above is substantially the same as that described in connection with ~igures 5A
.
to 5L. That is, with the PNP transistor PNP Trl shown in Figure 6L, its collector region is made of the P type region 48A of low concentration of the first epitaxial layer 48 and the P type embedded region 44 of high concentration and its base and emitter regions 54 and ~7 are made by the double diffusion in the second and third epitaxial growth layers 49 and 53.
Accordingly, the PNP transistor PNP Trl is high in property, namely, its high frequency characteristic. and current characteristic of its current .
amplification factor hpE are improved and the withstanding voltage across . .
the collector junction thereof is made high. ~:
As to the manufacture of the semiconductor integrated circuit.
device showr~ in Figure 6, the P and N type epitaxial growth layers 48 and - ........ ........
~48655 49 are formed; the P type region 48A of low concentration and the P
type region 44 of high concentration, which serve as the collector region of the PNP transistor, the N type region 49B of low impurity and the N
type region 46 of high concentration which serve as the collector region of the PNP transistor, are formed by utilizlng the difference of the diffusion lengths of the P type region 44 of middle concentration, for example, 1017~1018 cm~3 and the N type region 46 of high concentra- ;-tion, for example, 102 cm 3, which were previously embedded Into the substrate 41, to the P type epitaxial growth layer 48; then the base region 52 of the NPN transistor is formed; the third epitaxial growth layer 53 of N type is formed; and thereafter the base and emitter diffu-sions of the PNP transistor are deeply carried out. Further, upon the ~ -process of the emitter diffusion of the PNP transistor, the diffusion of impurity at high concentration forming the region for leading out the base electrode of the NPN transistor is carried out at the same time.
Accordingly, such a semiconductor integrated circuit device can be made by a relatively small number of process steps.
Figure 7 or Figures 7A to 7J show a further embodimert of the present invention in which such a semiconductor integrated circuit device having an LEC type of PNP transistor, a PNP transistor and a resistor.
As shown in Figure 7A, a P type semiconductor substrate 71 whose specific resistance is selected, for example, to be in the order of 3 tO 5 ~?-cm is prepared. N type embedded layers 72 and 73, which are of high impurity concentration and have a sheet resistance ~S
of, for example, about 20 Qjo . are formed by diffusion on the substrate .
1~48655 71 from the surface thereof at the location where an NPN transistor must be formed later and at the common location where a PNP transistor :.
and a resistor must be formed later, respectively (Refer to Figure 7B).
In the figures, 74 indicates an insulating layer made of, for example, , si2 . ' - . .
Then, a P type isolation region 75 is formed in the.sub- .
strate 71 by diffusion for isolating the N type embedded layer~ 72 and 73 in such that it is shaped like a lattice when viewed from the upper side and its sheet resistance ~S is selected about 10 S2/n . Tihen, a first epitaxial' growth layer 76 of N type is .formed to cover all the substrate 71 whose specific resistance is selected, for example, about 4 to 7 52-cm (Figure 7D). In Figure 7D, 74' designates an insulating layer made, for example, of SiO2.
Thereafter, a P type impurity is selectively diffused into the .
N type epitaxial growth layer 76 to form therethrough a P type isolation region 77 at a location corresponding to the P type isolation region 75 which is connected to 77 through the layer 76, and at the same time a -- -P type region 78 which will serve as the collector region of a PNP
transistor to be formecl later (Figure 7E).
A P type region 79 is formed by diffusion in the N type epitaxial growth layer 76 at the location where the base region of an NPN transistor will be made, and at the same time or process a P
t~,pe region 80 is formed in the layer 76 by diffusion at the location where a resistor is to be formed later. In this case, the regions 79 and 80 can ~e selected to have a sheet resistance of 1000 52/~ (Figure 7F).
: :
10~865S
Thereafter, a second N type epitaxial growth layer 81 of the N type is formed on the N type epitaxial growth layer 76 (Figure :
7G). :
A P type impurity is, then, diffused into the second N type epitaxial growth layer 81 selectively to form a P type isolation region 82 which is connected to the isolation region 77; a P type region. 83, ~ :
which is connected to the P type region 79 and will serve as part of the base region of the NPN transistor; a P type region 84, which is connected to-the P type region 78 and will serve as a part of the collector region of the PNP transistor; and P type regions 85A and 85B which are - ~ -connected to both ends of the P type region 80, which will be a resistor ~:
body, respectively (Figure 7H).
An N type impurity is selectively diffused into the P type second epitaxial layer 81 (whose sheet resistance is selected to be ~
about 100 Q/D ) ~0 form an N type region 88 of high concentratlon at :
the position, which will become the collector of the NPN transistor, for leading out its collector electrode; an N type region 87 of high concen- :
tration in an N type region 86, which will serve as the low concentra- - -tion emitter, is surralnded by the base region 83 and forms an LH
junction JB with the N type region 87; an N type region 90 of high concentration in the region which will become the base of the PNP
transistor to provide an N type region 89 of low concentration between the region 90 and ~he P type region 7g which will become the collector of the PNP transistor; and an N type region 91 of high concentration in the N type region defined by the P type isolation region 82 and at the -side where the PNP transistor and resistor are provided, which region 91 serves for the electrode severing as isolation, respectively (Figure 7I). - :
~ . . . ~ . . .
1~486SS
A P type impurity is selectively diffused at high concentra-tion into the second epitaxial growth layer 81 (with a sheet resistance of about 10 S2/n ) to form a P type region 92 of high concentration on ~-the region 83, which will serve for deriving the base electrode of the NPN transistor; a P type region 93 of high concentration on the re~;Lon 90, which will become the emitter of the PNP transistor; a P type region 94 of high concentration on the region 84, wh'ich will serve for deriving the collector electrode of the PNP transistor; and P type regions 95A and 95B
of high concentration on the regions 85A and 85B, which will serve for deriving the electrodes of the P type region 80 which will become the resistor.
Thereafter, an emitter electrode E2, a base electrode B2 and a collector electrode C2 of the NPN transistor are formed on the regions 87, 92 and 88; an emitter elect:~de-El, a base electrode Bi and a collector electrode Cl of the PNP transistor are formed on the -regions 93, 90 and 94; a pair of electrodes Rl and R2 are formed on the regions 95A and 95B; and an electrode 96 is formed on the region 91, respectively.
Thus, as shown in Figure 7J, a semiconductor integrated circuit device is provided. In this case, it has an NPN transistor NPN Tr2 of LEC type whose collector region is made of parts of the first and second epitaxial growth layers 76 and 81 which is surrounded by the P
type isolation regions 82 and 77, whose base region is made of the P type region 79 and whose emitter region is made of the N type region 86 of low concentration which consists of the second epitaxial growth layer 81 and forms an LH junction JB with the N type region 87 of high concen-tration; a PNP transistor PNP Trl whose collector region is made of the 1C~4~3~55 P type region 78, whose base region is made of the N type region 89 of low concentration consisting of the second epitaxial growth layer 81 and the N type diffusion region 90 of high concentration and whose emitter region is made of the P type diffusion region 93 of high concentration;
and a resistor R is made of the P type region 80, respectively.
According to the semiconductor integrated circult devlce of the invention described just above, a PNP transistor of high property is obtained, together with an NPN transistor of high property similar to those shown in Figures 5 and 6. That is, ~although a description on the NPN transistor will be omitted, the base region 90 and emitter region 93 of the PNP transistor PNP Tr1 are formed by double diffusions into the second epitaxial growth layer 81, so that its high frequency characteristic and the current characteristic of its factor hFE are improved. Further, since the base region of the PNP transistor, which contacts with its collector region, is made of the region 89 of low concentration consisting of the second epitaxial growth layer 81, its withstanding voltage across the collector junction is improved. In addi- :
tion, the part of the base region apart from the collector junction consists of the region 90 of high concentration, so that the punch-through upon the operation can be avoided to increase its withstanding voltage.
As described in the foregGing, with the semiconductor integrated circuit device of the present invention, it has provided with the PNP transistor of high property or of high withstanding voltage and superior in high frequency and current characteristics as well as the NPN transistor of LEC type and hence good complementary transistors.
Further, with the present invention, since the PNP transis- -tor PNP Tr1 coexists with the NPN transistor NPN Tr2 of LEC type, it 1~4865S :
is easy to introduce an LEC transistor imo a semiconductor integrated ci rcuit devi ce.
The foregoing description is given on the case that the NPN
transistor is made as an LEC type, but it is also possible that an ordinary-NPN transistor with the emitter of high COnCentraliOn be used as the NPN transistor of the invention.
Further, the NPI\l transistors formed in the examples shown in Figures 5 to 7 include the LH junction, but they can be made to have the form of the construction shown in Figures 3 and 4.
lt will be apparent to those skilled in the art that many modifications and valiations may be effected without departin~ from the spirit and scope of the novel concepts of the present invention.
~,r* ~ 2 4 ~
~1~
Claims (5)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A semiconductor integrated circuit having first and second transistors of opposite conductivity type, comprising:
a. a semiconductor substrate of a first conductivity type:
b. an epitaxial layer formation of a second conductivity type and relatively low impurity concentration formed on said substrate and having a major face opposite the substrate;
c. said first transistor comprising:
i. a first region of first conductivity type in said epitaxial layer of formation spaced below said major face, and a conductive path region of first conductivity type and higher impurity concentra-tion than said first region extending from the first region up to the major face;
ii. a second region of second conductivity type being formed of said epitaxial layer formation and partially surrounded by said first region and conductive path region; and iii. a third region of first conductivity type formed in said second region spaced from said first region by said second region;
d. an isolating PN junction between said first transistor and said second transistor said second transistor comprising:
i. a fourth region of second conductivety type formed of a portion of said epitaxial layer formation isolated from the first transistor by the isolating PN junction;
ii. a fifth region of first conductivity type spaced below said major face; and a conductive path region of first conductivity type and higher impurity concentration than said fifth region from the fifth region up to the major face.
iii. a sixth region of second conductivity type being formed of said relatively low concentra-tion epitaxial layer formation and partially surrounded by said fifth region and conductive path region, said sixth region being spaced from said fourth region by said fifth region;
and iv. a seventh region of second conductivity type and concentration relatively higher than said sixth region formed in said sixth region and forming a low-high concentration barrier junction therewith, said junction being spaced from said fifth region by a distance less than the diffusion length of minority carriers in said sixth region injected from said fifth region when a forward bias is applied between said fifth and sixth regions;
whereby a first transistor is formed in an integrated circuit with a second transistor of low emitter concentration.
a. a semiconductor substrate of a first conductivity type:
b. an epitaxial layer formation of a second conductivity type and relatively low impurity concentration formed on said substrate and having a major face opposite the substrate;
c. said first transistor comprising:
i. a first region of first conductivity type in said epitaxial layer of formation spaced below said major face, and a conductive path region of first conductivity type and higher impurity concentra-tion than said first region extending from the first region up to the major face;
ii. a second region of second conductivity type being formed of said epitaxial layer formation and partially surrounded by said first region and conductive path region; and iii. a third region of first conductivity type formed in said second region spaced from said first region by said second region;
d. an isolating PN junction between said first transistor and said second transistor said second transistor comprising:
i. a fourth region of second conductivety type formed of a portion of said epitaxial layer formation isolated from the first transistor by the isolating PN junction;
ii. a fifth region of first conductivity type spaced below said major face; and a conductive path region of first conductivity type and higher impurity concentration than said fifth region from the fifth region up to the major face.
iii. a sixth region of second conductivity type being formed of said relatively low concentra-tion epitaxial layer formation and partially surrounded by said fifth region and conductive path region, said sixth region being spaced from said fourth region by said fifth region;
and iv. a seventh region of second conductivity type and concentration relatively higher than said sixth region formed in said sixth region and forming a low-high concentration barrier junction therewith, said junction being spaced from said fifth region by a distance less than the diffusion length of minority carriers in said sixth region injected from said fifth region when a forward bias is applied between said fifth and sixth regions;
whereby a first transistor is formed in an integrated circuit with a second transistor of low emitter concentration.
2. The integrated circuit of claim 1 in which a diffused portion of second conductivity type and concentration higher than said first transistor second region is formed in said second region to extend at least between said first region and third region, whereby said first trans-istor has a base of high impurity concentration and high breakdown voltage.
3. The integrated circuit of claim 1 in which the impurity concentration and gradient of said low-high junc-tion is selected to have an electric field such that a drift current of minority carriers produced thereby substan-tially balances said diffusion current of minority carriers injected from the fifth region.
4. A semiconductor integrated circuit having first and second transistors of opposite conductivity type, com-prising:
a. a semiconductor substrate of a first conductivity type:
b. an epitaxial layer formation of a second conductivity type and relatively low concentration formed on said substrate and having a major face opposite substrate;
c. a first conductivity type isolation region in said epitaxial layer formation from said major face down to said substrate;
d. a first transistor formed on one side of said isolation region comprising;
i. a first embedded region of second conductivity type formed in said substrate, ii. a second embedded region of first conductivity type formed in said first embedded region and extending upwardly in said epitaxial layer formation.
iii. a first region of first conductivity type formed in said epitaxial layer formation spaced below said major face in contact with said second embedded region, and a conductive path region of first conductivity type and higher impurity concentration than said first region from the first region up to the major face, iv. a second region of second conductivity type being formed of said epitaxial layer formation and partially surrounded by said first region and conductive path region, v. a diffused region of second conductivity type and relatively higher concentration formed in said second region between said first region and major face;
vi. a third region of first conductivity type formed in said diffusion region and spaced from said first region by said diffusion region, e. a second transistor formed on the other side of said isolation region comprising:
i. a third embedded region of second conductivity type formed in said substrate, ii. a fourth region of second conductivity type and lower concentration than said third embedded region formed by said epitaxial layer formation in contact with said third embedded region.
iii. a fifth region of first conductivity type in said fourth region spaced below said epitaxial layer formation major face and a conductive path re-gion of first conductivity type and high impurity concentration than said fifth region from the fifth region up to the major face, iv. a sixth region of second conductivity type-being formed of said epitaxial layer formation of rela-tively low concentration and partially surrounded by said fifth region and conductive path region, said sixth region being spaced from said fourth region by said fifth region and v. a seventh region of second conductivity type and concentration relatively higher than said sixth region formed in said sixth region and forming a low-high concentration barrier junction therewith, said junction being spaced from said fifth region by a distance less than the diffusion length of minority carriers in said sixth region in-jected from said fifth region when a forward-bias is applied between said fifth and sixth regions, whereby a first transistor of relatively high base concen-tration is formed with a second transistor of low emitter concentration.
a. a semiconductor substrate of a first conductivity type:
b. an epitaxial layer formation of a second conductivity type and relatively low concentration formed on said substrate and having a major face opposite substrate;
c. a first conductivity type isolation region in said epitaxial layer formation from said major face down to said substrate;
d. a first transistor formed on one side of said isolation region comprising;
i. a first embedded region of second conductivity type formed in said substrate, ii. a second embedded region of first conductivity type formed in said first embedded region and extending upwardly in said epitaxial layer formation.
iii. a first region of first conductivity type formed in said epitaxial layer formation spaced below said major face in contact with said second embedded region, and a conductive path region of first conductivity type and higher impurity concentration than said first region from the first region up to the major face, iv. a second region of second conductivity type being formed of said epitaxial layer formation and partially surrounded by said first region and conductive path region, v. a diffused region of second conductivity type and relatively higher concentration formed in said second region between said first region and major face;
vi. a third region of first conductivity type formed in said diffusion region and spaced from said first region by said diffusion region, e. a second transistor formed on the other side of said isolation region comprising:
i. a third embedded region of second conductivity type formed in said substrate, ii. a fourth region of second conductivity type and lower concentration than said third embedded region formed by said epitaxial layer formation in contact with said third embedded region.
iii. a fifth region of first conductivity type in said fourth region spaced below said epitaxial layer formation major face and a conductive path re-gion of first conductivity type and high impurity concentration than said fifth region from the fifth region up to the major face, iv. a sixth region of second conductivity type-being formed of said epitaxial layer formation of rela-tively low concentration and partially surrounded by said fifth region and conductive path region, said sixth region being spaced from said fourth region by said fifth region and v. a seventh region of second conductivity type and concentration relatively higher than said sixth region formed in said sixth region and forming a low-high concentration barrier junction therewith, said junction being spaced from said fifth region by a distance less than the diffusion length of minority carriers in said sixth region in-jected from said fifth region when a forward-bias is applied between said fifth and sixth regions, whereby a first transistor of relatively high base concen-tration is formed with a second transistor of low emitter concentration.
5. The integrated circuit of claim 4 in which the first transistor first region first portion has an impurity concentration relatively lower than impurity concentration of said second embedded region whereby a low concentration collector region is formed adjacent a base in said first transistor.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP50016561A JPS5914897B2 (en) | 1975-02-08 | 1975-02-08 | semiconductor equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1048655A true CA1048655A (en) | 1979-02-13 |
Family
ID=11919681
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA76245057A Expired CA1048655A (en) | 1975-02-08 | 1976-02-05 | Semiconductor integrated circuit device |
Country Status (8)
| Country | Link |
|---|---|
| JP (1) | JPS5914897B2 (en) |
| CA (1) | CA1048655A (en) |
| CH (1) | CH607332A5 (en) |
| DE (1) | DE2604735A1 (en) |
| FR (1) | FR2300417A1 (en) |
| GB (1) | GB1533156A (en) |
| IT (1) | IT1055132B (en) |
| NL (1) | NL7601307A (en) |
Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56126960A (en) * | 1980-03-11 | 1981-10-05 | Nec Corp | Manufacture of semiconductor device |
| EP0093304B1 (en) * | 1982-04-19 | 1986-01-15 | Matsushita Electric Industrial Co., Ltd. | Semiconductor ic and method of making the same |
| JPS6062595U (en) * | 1983-10-04 | 1985-05-01 | 井上 八郎 | Cutting edge of ground drilling bit |
| JPS61164399U (en) * | 1985-03-30 | 1986-10-11 | ||
| IT1218471B (en) * | 1985-05-09 | 1990-04-19 | Ates Componenti Elettron | BIPOLAR INTEGRATED CIRCUIT INCLUDING VERTICAL PNP TRANSISTORS WITH COLLECTOR ON THE SUBSTRATE |
| JPS6386192U (en) * | 1986-11-19 | 1988-06-06 | ||
| JPH053587Y2 (en) * | 1986-11-19 | 1993-01-28 | ||
| EP0301468B1 (en) * | 1987-07-29 | 1993-08-25 | Fairchild Semiconductor Corporation | Process for fabricating complementary contactless vertical bipolar transistors |
| JPH02296994A (en) * | 1989-05-09 | 1990-12-07 | Fujita Corp | Cutter head for slurry shield machine |
| JPH03128793U (en) * | 1990-04-10 | 1991-12-25 | ||
| JPH0450493U (en) * | 1990-08-31 | 1992-04-28 | ||
| FR3106931B1 (en) | 2020-01-30 | 2022-02-18 | St Microelectronics Crolles 2 Sas | Method for manufacturing a device comprising a PNP bipolar transistor and an NPN bipolar transistor for radio frequency applications |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5147583B2 (en) * | 1972-12-29 | 1976-12-15 |
-
1975
- 1975-02-08 JP JP50016561A patent/JPS5914897B2/en not_active Expired
-
1976
- 1976-02-04 GB GB440076A patent/GB1533156A/en not_active Expired
- 1976-02-05 CA CA76245057A patent/CA1048655A/en not_active Expired
- 1976-02-05 IT IT1995076A patent/IT1055132B/en active
- 1976-02-06 DE DE19762604735 patent/DE2604735A1/en not_active Withdrawn
- 1976-02-06 FR FR7603362A patent/FR2300417A1/en active Granted
- 1976-02-06 CH CH146276A patent/CH607332A5/xx not_active IP Right Cessation
- 1976-02-09 NL NL7601307A patent/NL7601307A/en not_active Application Discontinuation
Also Published As
| Publication number | Publication date |
|---|---|
| FR2300417A1 (en) | 1976-09-03 |
| JPS5914897B2 (en) | 1984-04-06 |
| DE2604735A1 (en) | 1976-08-19 |
| FR2300417B1 (en) | 1980-03-21 |
| GB1533156A (en) | 1978-11-22 |
| IT1055132B (en) | 1981-12-21 |
| JPS5191680A (en) | 1976-08-11 |
| CH607332A5 (en) | 1978-12-15 |
| NL7601307A (en) | 1976-08-10 |
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