JP3260561B2 - Insulated gate semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulated gate semiconductor device, and more particularly to an improvement for suppressing conduction of a parasitic transistor.

[0002]

2. Description of the Related Art In an insulated gate semiconductor device, p-type and n-type semiconductor layers are alternately joined, main electrodes through which a main current flows are electrically connected to semiconductor layers at both ends, and at least one semiconductor layer is formed. Is a semiconductor device having a structure in which a gate electrode for forming a channel by applying an electric field is connected via an insulating film. In this insulated gate semiconductor device, the voltage applied to the gate electrode causes
The current flowing between the two main electrodes, that is, the main current, is controlled. MOS transistor and insulated gate bipolar transistor (Insulated Gate Bipolar Transistor)
: Hereinafter abbreviated as IGBT) is a typical example.

The structure of a conventional IGBT is described in, for example,
As shown in FIG. 2 of 163974, a so-called planar gate structure in which a gate electrode is provided on one main surface of a semiconductor substrate and a channel is formed along the main surface has been the mainstream. On the other hand, for example, JP-A-2-328
As shown in FIG. 1 of Japanese Patent Application Laid-Open No. 8 (1996) -1994, a groove (trench) is formed on one main surface of a semiconductor substrate, and a gate electrode, that is, a trench gate is embedded in the groove.
An insulated gate semiconductor device having a trench gate structure in which a channel is formed along the side wall of the trench has recently been developed and attracts attention.

This device has excellent features that it can be easily miniaturized to increase the degree of integration, the manufacturing process is simplified, and that the saturation current can be increased. Comparing the devices having the same structure and the same chip size, the device having the trench gate structure can obtain a saturation current ten times or more as compared with the device having the planar gate structure.

FIG. 6 is a sectional perspective view showing the structure of a conventional N-channel IGBT having a trench gate structure. IG
The BT generally has a structure in which a number of unit IGBT elements (hereinafter, referred to as “unit cells”) are connected in parallel. This is the same for MOS transistors. FIG. 6 illustrates one unit cell of the IGBT.

In the IGBT 100 shown in FIG. 6, an N ⁺ -type buffer layer 2, an N ^-- type base layer 3, and a P-type base layer 4 are sequentially stacked on a P ⁺ -type anode layer 1. Further, an N ⁺ -type emitter layer 5 is provided on the upper surface of the P-type base layer 4.
Are selectively formed. These semiconductor layers are formed in a semiconductor substrate whose base material is silicon, and P ⁺
The anode layer 1 is exposed on the lower main surface of the semiconductor substrate, and the P-type base layer 4 and the N ⁺ -type emitter layer 5 are selectively exposed on the upper main surface. P ⁺ type anode layer 1 and N ⁺ type buffer layer 2
A PN junction J ₁ is formed at the interface of the N ⁻ -type base layer 3.
Another PN junction J ₂ is formed at the interface between the P-type base layer 4 and the N ⁺ -type emitter layer 5, and another PN junction J ₃ is formed at the interface between the P-type base layer 4 and the N ⁺ -type emitter layer 5.

The N ⁺ -type buffer layer 2 and the N ⁺ -type emitter layer 5 contain N-type impurities at a higher concentration than the N ^-- type base layer 3, and the P ⁺ -type anode layer 1 has a P-type base layer. 4
It contains a higher concentration of P-type impurities.

Further, a groove is etched from the upper main surface of the semiconductor substrate so as to penetrate both the N ⁺ -type emitter layer 5 and the P-type base layer 4 to reach the N ^-- type base layer 3. Is formed with an insulating film 6 composed of a silicon oxide film. A gate electrode 7 made of polysilicon is buried inside the insulating film 6. The inner wall of the groove and the gate electrode 7 are electrically insulated by the insulating film 6.

On the upper main surface of the semiconductor substrate, both the P-type base layer 4 and the N ⁺ -type emitter layer 5 are electrically short-circuited.
An emitter electrode 8 made of a metal such as aluminum is provided, and a collector electrode 9 made of a metal is provided on the lower main surface so as to be electrically short-circuited to the P ⁺ type anode layer 1. The insulating film 6 also covers the upper surface of the gate electrode 7, thereby maintaining electrical insulation between the gate electrode 7 and the emitter electrode 8.

A P ⁺ type anode layer 1, an N ⁺ type buffer layer 2,
Each semiconductor layer of the N ⁻ type base layer 3 and the P type base layer 4 is continuous with each other between the unit cells. The same applies to the emitter electrode 8 and the collector electrode 9.

Next, the operation of the conventional device 100 will be described. First, the emitter electrode 8 is grounded, and a predetermined positive collector voltage V _CE is applied to the collector electrode 9. At this time, between the emitter electrode 8 and the gate electrode 7,
When a gate voltage V _GE exceeding the gate threshold voltage inherent to the device is applied, the channel region 11, which is the region of the P-type base layer 4 facing the gate electrode 7, is inverted to N-type. A channel is formed. Through this channel, electrons as carriers are injected into the N ⁻ type base layer 3 from the N ⁺ type emitter layer 5.

By the injected electrons, a forward bias voltage is applied to the PN junction J ₁ between the P ⁺ type anode layer 1 and the N ⁺ type buffer layer 2, and holes as carriers from the P ⁺ type anode layer 1 are formed. Is implanted into the N ⁻ -type base layer 3.
As a result, the resistance of N ⁻ type base layer 3 is greatly reduced, and collector current I _C flowing from collector electrode 9 to emitter electrode 8 reaches a high value. That is, the device becomes conductive (turns on).

When the gate voltage V _GE is set to a value equal to or lower than the gate threshold voltage, for example, zero or a negative value while the collector voltage V _CE of a predetermined magnitude is applied, the N channel disappears,
The channel region 11 returns to the original P-type conductivity type.
As a result, the collector current I _C is blocked. That is,
The IGBT 100 is turned off (turns off).

When the collector voltage V _CE is applied to the IGBT 100 to a value close to the breakdown voltage, the depletion layer extending from the P-type base layer 4 reaches the N ⁺ -type buffer layer 2. When the depletion layer reaches the P ⁺ -type anode layer 1, the conduction between the P ⁺ -type anode layer 1 and the P-type base layer 4 (referred to as "punch through"). The N ⁺ type buffer layer 2 has a role of preventing punch-through by preventing the depletion layer from penetrating into the P ⁺ type anode layer 1.

[0015]

The IGBT 1
At N00, an NPN-type bipolar transistor is parasitically formed by the N ⁺ -type emitter layer 5, the P-type base layer 4, and the N ⁻ -type base layer 3. This parasitic transistor is an original transistor existing in the IGBT 100, that is, the P-type base layer 4 and the N ⁻ -type base layer 3.
A thyristor is parasitically configured in combination with a PNP-type bipolar transistor including the N ⁺ -type buffer layer 2 and the P ⁺ -type anode layer 1.

When the IGBT 100 is in a conductive state, a current using electrons as carriers, ie, an electron current, and a current using holes as carriers, ie, a hole current, are IGB.
It flows inside T100. The electron current flows from the N ⁺ type emitter layer 5 via the channel region 11 to the N ⁻ type base layer 3.
And recombine with holes injected from the P ⁺ type anode layer 1. On the other hand, the hole current flows from P ⁺ -type anode layer 1 N ^- flows into type base layer 3, some of N ^-
The electrons recombine with the electrons flowing to the mold base layer 3, but the rest flows into the emitter electrode 8 via the P-type base layer 4.

No problem occurs when the hole current flowing into the emitter electrode 8 is sufficiently small. However, when the hole current exceeds a certain level and becomes large, the voltage drop due to the resistance of the P-type base layer 4 causes N ⁺ forward bias voltage is applied to the PN junction J ₃ between the type emitter layer 5 and the P-type base layer 4. As a result, electrons are injected from the N ⁺ -type emitter layer 5 to the P-type base layer 4 and the parasitic NPN
The current gain of the transistor increases, turning on the parasitic thyristor.

That is, once the parasitic NPN transistor becomes conductive, the parasitic thyristor is triggered and turns conductive (this state is called "latch-up"). When the latch-up state is reached, the IGBT 100 can no longer control the collector current I _C by the gate voltage V _GE applied to the gate electrode 7. That is,
Collector current I _C continues to flow independent of gate voltage V _GE . Therefore, when the parasitic transistor is turned on, I
Causes GBT 100 to be destroyed. This is common to IGBTs in general, not limited to trench gate structures.

For this reason, increasing the maximum controllable current, that is, the maximum value of the collector current I _{C that} can be controlled by the gate voltage V _GE by suppressing the latch-up, is difficult to achieve by IGB.
This is one of the issues in improving the characteristics of T.
To increase the maximum controllable current, as is apparent from the above description, suppressing the generation of the forward bias voltage of the PN junction J _3, parasitic and suppressing the current amplification factor of the NPN transistor, conduction of the parasitic NPN transistor by their Need to be suppressed.

Further, the same can be said for MOS transistors. Also in a MOS transistor, a bipolar transistor is formed in a parasitic manner, and when the parasitic transistor becomes conductive, the drain current can no longer be controlled by the gate voltage applied to the gate electrode. Therefore, when the parasitic transistor is turned on, the MOS transistor is destroyed.

When a MOS transistor is used by connecting it to an inductive load, a voltage exceeding an avalanche voltage may be applied to the MOS transistor when the MOS transistor turns from on to off. At this time, M
An avalanche current flows through the OS transistor, and the parasitic transistor conducts due to the avalanche current. As a result, the MOS transistor is led to destruction. The upper limit of the avalanche current that does not lead to breakdown is called avalanche withstand capability. If the parasitic transistor is easy to conduct, the avalanche resistance decreases.

In particular, an IGBT or M having a trench gate structure
In the OS transistor, since the saturation current is large, conduction of the parasitic transistor easily occurs. Therefore, in a device having a trench structure, it is a particularly important technical subject to suppress conduction of a parasitic transistor, thereby increasing a maximum controllable current or avalanche resistance and securing a wide safe operation area.

The present invention has been made in view of the above-mentioned problems, and suppresses conduction of a parasitic transistor. As a result, a sufficiently large controllable current or avalanche resistance can be obtained, and a sufficiently wide safe operation area can be obtained. An object of the present invention is to provide an insulated gate semiconductor device.

[0024]

According to a first aspect of the present invention, there is provided an insulated gate semiconductor device including a semiconductor substrate, the semiconductor substrate comprising a first semiconductor layer of a first conductivity type and a first semiconductor layer formed on the first semiconductor layer. A second semiconductor layer of a second conductivity type, which is stacked on the semiconductor substrate and is exposed on the upper surface of the semiconductor substrate; a third semiconductor layer of the first conductivity type, which is selectively formed in a substantially band shape on the upper surface of the second semiconductor layer; An upper surface of the second semiconductor layer is selectively formed substantially in a band shape, is formed deeper than the third semiconductor layer and intersects with the third semiconductor layer, and has an impurity concentration lower than that of the second semiconductor layer. And a fourth semiconductor layer of a second conductivity type having a high
A groove penetrating the third and second semiconductor layers and reaching the first semiconductor layer is formed along an upper surface of the substantially band-shaped third semiconductor layer. A control electrode buried in the trench with an electrically insulating insulating film interposed between the base and a base; and a control electrode formed on an upper surface of the semiconductor base, the second, third, and fourth semiconductor layers being formed on the upper surface. The semiconductor device further includes a first main electrode electrically connected to any of the exposed surfaces, and a second main electrode formed on the lower surface of the semiconductor base and electrically connected to the lower surface.

An insulated gate semiconductor device according to a second aspect of the present invention is the device according to the first aspect, wherein the third semiconductor on an exposed surface of the second semiconductor layer and the fourth semiconductor layer on an upper surface of the semiconductor substrate. The ratio L / M when the width in the direction along the layer is L and M is set in the range of 1 to 5.

According to a third aspect of the present invention, there is provided an insulated gate semiconductor device according to the first aspect, wherein the semiconductor substrate is
A second conductive type fifth semiconductor layer formed on a lower surface of the first semiconductor layer; the fifth semiconductor layer being exposed on a lower surface of the semiconductor substrate; It is electrically connected to the semiconductor layer.

[0027]

In the device according to the first aspect of the invention, the fourth semiconductor layer having a higher impurity concentration and lower resistance than the second semiconductor layer is deeper than the third semiconductor layer on the upper surface of the second semiconductor layer, and is provided in the third semiconductor layer. It is formed so as to intersect. Therefore, the base current of the parasitic transistor composed of the first, second, and third semiconductor layers flows while bypassing the fourth semiconductor layer. As a result, the PN between the second semiconductor layer and the third semiconductor layer
Since the bias voltage applied to the junction is suppressed low, conduction of the parasitic transistor is suppressed.

Further, in addition to the PN junction between the second semiconductor layer and the third semiconductor layer, there is a PN junction between the fourth semiconductor layer and the third semiconductor layer. The electron injection efficiency is reduced. This also contributes to suppressing conduction of the parasitic transistor.

Further, since the fourth semiconductor layer is formed in a substantially strip shape, a channel having a high gate threshold voltage occupies only a part of the entire channel. Therefore, conduction of the parasitic transistor can be suppressed without greatly reducing the saturation current.

In the device according to the second aspect of the invention, the ratio of the width of the exposed surface of the second semiconductor layer and the exposed surface of the fourth semiconductor layer to the upper surface of the semiconductor substrate in the direction along the third semiconductor layer is optimally in the range of 1 to 5. Has been If the width ratio is within this range, the maximum controllable current is twice or more as compared with the conventional device, and moreover,
The decrease in the saturation current can be suppressed to 以下 or less.

The device according to the third aspect of the present invention has a fifth semiconductor layer connected to the second main electrode, and thus functions as an IGBT.

[0032]

【Example】

<First Embodiment> FIG. 1 is a sectional perspective view showing the structure of an IGBT according to a first embodiment. The IGBT 101 is an N-channel IGBT having a trench gate structure. FIG. 2 is a cross-sectional view taken along the line AA 'in FIG. 1, and FIG. 3 is a top view illustrating the emitter electrode 8 removed. The IGBT 101 has a structure in which a number of IGBT unit cells are connected in parallel, and FIG. 1 to FIG. 3 show one unit cell.

Hereinafter, I will be described with reference to FIGS.
The structure and operation of the GBT 101 will be described. FIG. 1
In the following drawings, the same parts as those of the conventional apparatus 100 shown in FIG. 6 are denoted by the same reference numerals, and detailed description thereof will be omitted.

The IGBT 101 is characteristically different from the conventional IGBT 100 in that a semiconductor region 10 containing a high concentration of P-type impurities is formed on an upper main surface of a semiconductor substrate. The impurity concentration of this P ⁺ semiconductor region 10 is:
It is set higher than in the P-type base layer 4, and more preferably, lower than the concentration of N-type impurities in the N ⁺ -type emitter layer 5. The N ⁺ -type emitter layer 5 selectively formed on the upper surface of the P-type base layer 4 is adjacent to both sides of the groove, and is striped (strip-like) along the groove.
Is formed. On the other hand, the P ⁺ semiconductor region 10
Are also formed selectively in the form of stripes on the upper surface of the P-type base layer 4, are orthogonal to the N ⁺ -type emitter layer 5 (FIGS. 1 and 3), and moreover than the N ⁺ -type emitter layer 5. It is formed deep (FIG. 2).

In a portion where the N ⁺ -type emitter layer 5 and the P ⁺ semiconductor region 10 intersect, the structure is such that the N ⁺ -type emitter layer 5 is selectively formed on the upper surface of the P ⁺ semiconductor region 10.
Therefore, the PN junction J ₃ is constituted by an interface with the P-type base layer 4 and an interface with the P ⁺ semiconductor region 10 arranged in parallel with each other along the striped N ⁺ -type emitter layer 5.

The P ⁺ semiconductor region 10 is exposed on the upper surface of the P-type base layer 4. Therefore, the emitter electrode 8 is electrically connected to the P ⁺ semiconductor region 10 together with the N ⁺ -type emitter layer 5 and the P-type base layer 4. Is short circuited. Further, as shown in FIG. 3, a plurality of P ⁺ semiconductor regions 10 are preferably arranged at equal intervals from each other.

Since the IGBT 101 is constructed as described above, the gate voltage exceeding the gate threshold voltage is applied to the gate electrode 7 with the collector voltage V _CE of a predetermined magnitude applied, similarly to the conventional IGBT 100. The IGBT 101 conducts when V _GE is applied, and shuts off when the gate voltage V _GE falls below the gate threshold voltage.

However, in the IGBT 101, P ⁺
Due to the presence of the semiconductor region 10, the IGBT 1
A characteristic operation different from 00 appears. First, P
^{Since the +} semiconductor region 10 has a low resistance, the hole current serving as the base current of the parasitic NPN transistor including the three layers of the N ⁻ -type base layer 3, the P-type base layer 4, and the N ⁺ -type emitter layer 5 can be quickly increased. To bypass to the emitter electrode 8,
Bias voltage applied to the PN junction J ₃ is reduced.
As a result, conduction of the parasitic NPN transistor is suppressed, so that latch-up hardly occurs.

Second, since part of the PN junction J ₃ is formed at the interface between the N ⁺ -type emitter layer 5 and the P ⁺ semiconductor region 10, the injection of electrons at this part of the PN junction J ₃ is performed. Efficiency is reduced. For this reason, the current amplification factor of the parasitic NPN transistor does not increase. This also means that the parasitic NPN
It suppresses transistor conduction and contributes to suppression of latch-up.

Third, the P ⁺ semiconductor region 10 is formed in a stripe shape and occupies only a part of the channel region 11. The channel region 11 is composed of a portion composed of a P-type base layer 4 having a low gate threshold voltage and a portion composed of a P ⁺ semiconductor region 10 having a high gate threshold voltage arranged in parallel along the trench. You. Since the collector current I _C is lower or zero in the channel portion where the gate threshold voltage is high as compared with the portion where the gate threshold voltage is low, the saturation current is reduced by the amount of the P ⁺ semiconductor region 10. However, since the P ⁺ semiconductor region 10 occupies only a part of the channel region 11, the effect on the saturation current is not dramatic.

From the above-mentioned first to third features, latch-up is suppressed while the saturation current is maintained at a high level without being significantly reduced. That is, the maximum controllable current increases, and the safe operation area expands.

It is desirable to set the width of the stripe-shaped P ⁺ semiconductor region 10 in an optimum range. The optimum width of the P ⁺ semiconductor region 10 is desirably set small enough not to excessively reduce the saturation current and large enough to obtain a sufficient latch-up suppressing effect.

As shown in FIG. 3, the width M of the P ⁺ semiconductor region 10, and defines the width L of the upper surface exposed portion of the P-type base layer 4 except for the P ⁺ semiconductor region 10. P ⁺ semiconductor region 1
0 means that a plurality of lines are arranged at equal intervals, and
And the exposed surface of the corresponding P ⁺ semiconductor region 10 and the P-type base layer 4 corresponding to the width L to have to repeatedly arranged alternately along the groove.

When the ratio L / M between the width L and the width M is set to, for example, 5, the maximum controllable current is about twice as large as that of the conventional IGBT 100, while the reduction of the saturation current is only about 80%. . When the ratio L / M is set to 1, the saturation current is about half that of the IGBT 100, but the maximum controllable current is about five times. In this case, the saturation current is largely reduced, but the saturation current is at least five times as large as that of the IGBT having the planar gate structure, which is sufficient. Ratio L
Although / M is appropriately selected depending on the required specifications of the apparatus, it is generally desirable to set it to 1 or more and 5 or less. In this range, the maximum controllable current and the saturation current more than twice as large as those of the conventional IGBT 100 are obtained, and the saturation current more than five times as large as the IGBT with the planar gate structure is obtained.

As will be described below, the IGBT 101 can be easily manufactured by utilizing a conventionally known wafer processing technique. In order to manufacture the IGBT 101, first, a silicon semiconductor having an N ⁺ type buffer layer 2 and an N ⁻ type base layer 3 sequentially formed by epitaxial growth on a P ⁺ type anode layer 1 doped with a P type impurity. Prepare a substrate.

Next, a P-type impurity is introduced into the upper surface of the N ⁻ -type base layer 3 by ion implantation or the like, whereby
A P-type base layer 4 having a predetermined depth is formed.

Further, an oxide film having a stripe-shaped opening is formed on the upper surface of the P-type base layer 4, and P-type impurities are introduced by ion implantation or the like using this as a mask. Thereby, stripe-shaped P ⁺ semiconductor region 1 having an impurity concentration higher than the impurity concentration of P-type base layer 4.
0 is formed shallower than the bottom surface of the P-type base layer 4.

Next, after removing the oxide film, a new oxide film having a stripe-shaped opening orthogonal to the opening of the previous oxide film is formed on the upper surface of the P-type base layer 4, and this is used as a mask. Is used to selectively introduce an N-type impurity. Thereby, a stripe-shaped N having a higher impurity concentration than P ⁺ semiconductor region 10 is formed.
^{The +} type emitter layer 5 is formed shallower than the P ⁺ semiconductor region 10. The formed N ⁺ -type emitter layer 5 is a P ⁺ semiconductor region 1
0 is orthogonal to each other.

Next, a groove opening in the upper main surface of the semiconductor substrate is formed in a stripe shape along the center line of the stripe-shaped N ⁺ -type emitter layer 5. The trench is formed by selectively performing etching so that the N ⁺ -type emitter layer 5 and the P ⁺
It is formed so as to penetrate the mold base layer 4 and reach the N ⁻ type base layer 3.

Next, after an insulating film 6 made of a silicon oxide film is formed with a predetermined thickness on at least the inner wall of the groove, a gate electrode 7 made of polysilicon is formed inside the insulating film 6. . The insulating film 6 is also formed on the upper surface of the gate electrode 7.

Further, an emitter electrode 8 made of a metal is formed on the upper main surface of the semiconductor substrate, and a collector electrode 9 also made of the same metal is formed on the lower main surface.
BT101 is completed.

As described above, no special new manufacturing technology is required to manufacture the IGBT 101. It can be easily manufactured by combining conventionally known wafer processing techniques. In particular, in the process of forming the P ⁺ semiconductor region 10 which is a characteristic part of the IGBT 101, the P ⁺ semiconductor region 1
0 and the N ⁺ -type emitter layer 5 are orthogonal to each other, so that P ⁺
No mask alignment is required between the semiconductor region 10 and the N ⁺ -type emitter layer 5. This is because the conventional IGBT 10
This means that the IGBT 101 having excellent characteristics in controllable current can be realized as easily as 0.

<Second Embodiment> In the first embodiment, the IGBT
Has been described, but a MOS having a trench gate structure is described.
A similar structure can be applied to a transistor. FIG.
FIG. 5 shows an example. FIG. 4 shows an N-channel type MO.
FIG. 3 is a cross-sectional perspective view of an S transistor. FIG. 5 is FIG.
3 is a cross-sectional view taken along the line BB ′ in FIG. This M
Similarly to the IGBT 101, the OS transistor 102 has a structure in which a number of unit cells are connected in parallel, and FIG. 4 and FIG. 5 show one unit cell.

As shown in FIGS. 4 and 5, the structure above the N ⁻ type base layer 3 is the same as that of the IGBT 101, and there is no P ⁺ type anode layer 1 and the N ⁺ type buffer layer 2 has a drain electrode. 9 is directly connected to IGBT 10
Characteristically different from 1. In the MOS transistor, the N-type semiconductor layer 5 is called an N-type source layer, and the two main electrodes 8 and 9 are called a source electrode and a drain electrode, respectively.

When a predetermined magnitude of the drain voltage V _DS is applied between the drain electrode 9 and the source electrode 8 so that the drain electrode 9 has a positive voltage, the gate voltage exceeding the gate threshold voltage is applied to the gate electrode 7. When _VGE is applied, the MOS transistor 102 conducts. That is, the drain electrode 9
, A drain current flows to the source electrode 8. Conversely, when the gate voltage V _{GE is set} to be equal to or lower than the gate threshold voltage, the MOS transistor 102 is cut off.

In the MOS transistor 102, P
⁺ The presence of semiconductor region 10 realizes a characteristic operation similar to that of IGBT 101. That is, conduction of the parasitic transistor is suppressed without significantly lowering the saturation current. Therefore, the avalanche resistance is improved, the maximum controllable current is increased, and the safe operation area is expanded.

For the same reason as in the first embodiment, it is desirable to set the ratio L / M in the range of 1 to 5.

<Other Embodiments> In the above embodiments, P
^{The +} semiconductor region 10 was formed so as to be orthogonal to the N ⁺ -type emitter layer 5. However, the same effects as those of these embodiments can be obtained even if they are formed so as to intersect not only at right angles but also at arbitrary angles. That is, it is possible to easily manufacture without requiring mask alignment, and to increase the controllable current without significantly lowering the saturation current.

[0059]

According to the device of the first invention, the fourth semiconductor layer having a higher impurity concentration and a lower resistance than the second semiconductor layer is formed by the second semiconductor layer.
Since the upper surface of the semiconductor layer is formed to be deeper than the three semiconductor layers and to intersect the third semiconductor layer, conduction of the parasitic transistor is suppressed while the saturation current is kept high without being significantly reduced. That is,
An insulated gate semiconductor device having a large maximum controllable current and a wide safe operation area can be obtained.

Further, since the third semiconductor layer and the fourth semiconductor layer are both substantially band-shaped and cross each other, it is not necessary to align mask patterns used in the process of forming these semiconductor layers. That is, it can be easily manufactured without requiring any difficult steps as compared with the conventional apparatus.

In the device according to the second aspect of the present invention, the ratio of the width of the exposed surface of the second semiconductor layer to the upper surface of the semiconductor substrate in the direction along the third semiconductor layer is optimally in the range of 1 to 5. As a result, the maximum controllable current more than twice as large as that of the conventional device can be obtained, and the reduction of the saturation current can be suppressed to 以下 or less. That is, a characteristic in the most preferable range for practical use is realized.

The device of the third invention functions as an IGBT because it has the fifth semiconductor layer connected to the second main electrode. That is, in an IGBT in which conduction of a parasitic transistor is particularly important, occurrence of latch-up can be suppressed while maintaining a high saturation current.

[Brief description of the drawings]

FIG. 1 is a sectional perspective view of an IGBT of a first embodiment.

FIG. 2 is a cross-sectional view of the device of FIG. 1 taken along the line AA ′.

FIG. 3 is a top view of the device of FIG. 1 with the emitter electrode 8 removed.

FIG. 4 is a sectional perspective view of an IGBT of a second embodiment.

FIG. 5 is a cross-sectional view of the device of FIG. 4 taken along section line BB ′.

FIG. 6 is a sectional perspective view of a conventional IGBT.

[Explanation of symbols]

1 P ⁺ type anode layer (fifth semiconductor layer), 2 N ⁺ type buffer layer (first semiconductor layer), 3 N ⁻ type base layer (first semiconductor layer), 4 P type base layer (second semiconductor layer) , 5 N
⁺ Type emitter layer (third semiconductor layer), 6 insulating film, 7 gate electrode (control electrode), 8 emitter electrode (first main electrode), 9 collector electrode (second main electrode), 10 P ⁺ semiconductor region (first 4 semiconductor layers), 11 channels.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 29/78

Claims (3)

(57) [Claims] 1. An insulated gate semiconductor device comprising a semiconductor substrate, wherein the semiconductor substrate has a first conductivity type.
A semiconductor layer, a second semiconductor layer of a second conductivity type laminated on the first semiconductor layer and exposed on an upper surface of the semiconductor substrate, and selectively formed in a substantially band shape on the upper surface of the second semiconductor layer. A third semiconductor layer of the first conductivity type and selectively formed in a substantially band shape on the upper surface of the second semiconductor layer, and formed so as to be deeper than the third semiconductor layer and to intersect with the third semiconductor layer. And a fourth semiconductor layer of a second conductivity type having an impurity concentration higher than that of the second semiconductor layer, wherein the first semiconductor layer penetrates the third and second semiconductor layers in the semiconductor substrate. Are formed along the upper surface of the substantially band-shaped third semiconductor layer, and the insulated gate semiconductor device is provided with an electrically insulating insulating film between the semiconductor substrate and the groove. A control electrode embedded in the semiconductor substrate; A first main electrode formed on the upper surface of the semiconductor substrate and electrically connected to any of the exposed surfaces of the second, third, and fourth semiconductor layers on the upper surface, and formed on the lower surface of the semiconductor base; The second electrically connected to the lower surface
And a main electrode. 2. A ratio L / M where widths of the exposed surfaces of the second semiconductor layer and the fourth semiconductor layer on the upper surface of the semiconductor substrate in the direction along the third semiconductor layer are L and M, respectively. 2. The insulated gate semiconductor device according to claim 1, wherein M is set in a range of 1 to 5. 3. The semiconductor substrate further includes a fifth semiconductor layer of a second conductivity type formed on a lower surface of the first semiconductor layer, wherein the fifth semiconductor layer is exposed on a lower surface of the semiconductor substrate. 2. The insulated gate semiconductor device according to claim 1, wherein said second main electrode is electrically connected to said fifth semiconductor layer.